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--W1_select_n_to_the_cfi_flash_0 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0
W1_select_n_to_the_cfi_flash_0 = DFFEAS(W1L62, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_readn is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn
W1_tri_state_bridge_0_readn = DFFEAS(W1L85, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_write_n_to_the_cfi_flash_0 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0
W1_write_n_to_the_cfi_flash_0 = DFFEAS(W1L87, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--YB1_safe_q[9] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[9]
YB1_safe_q[9] = DFFEAS(YB1_counter_comb_bita9, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[8] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[8]
YB1_safe_q[8] = DFFEAS(YB1_counter_comb_bita8, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[7] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[7]
YB1_safe_q[7] = DFFEAS(YB1_counter_comb_bita7, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[6] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[6]
YB1_safe_q[6] = DFFEAS(YB1_counter_comb_bita6, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[5] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[5]
YB1_safe_q[5] = DFFEAS(YB1_counter_comb_bita5, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[4] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[4]
YB1_safe_q[4] = DFFEAS(YB1_counter_comb_bita4, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[3] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[3]
YB1_safe_q[3] = DFFEAS(YB1_counter_comb_bita3, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[2] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[2]
YB1_safe_q[2] = DFFEAS(YB1_counter_comb_bita2, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[1] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[1]
YB1_safe_q[1] = DFFEAS(YB1_counter_comb_bita1, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[0] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[0]
YB1_safe_q[0] = DFFEAS(YB1_counter_comb_bita0, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_counter_comb_bita0 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita0
YB1_counter_comb_bita0 = YB1_safe_q[0] $ VCC;

--YB1L2 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita0~COUT
YB1L2 = CARRY(YB1_safe_q[0]);


--YB1_counter_comb_bita1 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita1
YB1_counter_comb_bita1 = YB1_safe_q[1] & !YB1L2 # !YB1_safe_q[1] & (YB1L2 # GND);

--YB1L4 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita1~COUT
YB1L4 = CARRY(!YB1L2 # !YB1_safe_q[1]);


--YB1_counter_comb_bita2 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita2
YB1_counter_comb_bita2 = YB1_safe_q[2] & (YB1L4 $ GND) # !YB1_safe_q[2] & !YB1L4 & VCC;

--YB1L6 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita2~COUT
YB1L6 = CARRY(YB1_safe_q[2] & !YB1L4);


--YB1_counter_comb_bita3 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita3
YB1_counter_comb_bita3 = YB1_safe_q[3] & !YB1L6 # !YB1_safe_q[3] & (YB1L6 # GND);

--YB1L8 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita3~COUT
YB1L8 = CARRY(!YB1L6 # !YB1_safe_q[3]);


--YB1_counter_comb_bita4 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita4
YB1_counter_comb_bita4 = YB1_safe_q[4] & (YB1L8 $ GND) # !YB1_safe_q[4] & !YB1L8 & VCC;

--YB1L10 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita4~COUT
YB1L10 = CARRY(YB1_safe_q[4] & !YB1L8);


--YB1_counter_comb_bita5 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita5
YB1_counter_comb_bita5 = YB1_safe_q[5] & !YB1L10 # !YB1_safe_q[5] & (YB1L10 # GND);

--YB1L12 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita5~COUT
YB1L12 = CARRY(!YB1L10 # !YB1_safe_q[5]);


--YB1_counter_comb_bita6 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita6
YB1_counter_comb_bita6 = YB1_safe_q[6] & (YB1L12 $ GND) # !YB1_safe_q[6] & !YB1L12 & VCC;

--YB1L14 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita6~COUT
YB1L14 = CARRY(YB1_safe_q[6] & !YB1L12);


--YB1_counter_comb_bita7 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita7
YB1_counter_comb_bita7 = YB1_safe_q[7] & !YB1L14 # !YB1_safe_q[7] & (YB1L14 # GND);

--YB1L16 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita7~COUT
YB1L16 = CARRY(!YB1L14 # !YB1_safe_q[7]);


--YB1_counter_comb_bita8 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita8
YB1_counter_comb_bita8 = YB1_safe_q[8] & (YB1L16 $ GND) # !YB1_safe_q[8] & !YB1L16 & VCC;

--YB1L18 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita8~COUT
YB1L18 = CARRY(YB1_safe_q[8] & !YB1L16);


--YB1_counter_comb_bita9 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9
YB1_counter_comb_bita9 = YB1_safe_q[9] & !YB1L18 # !YB1_safe_q[9] & (YB1L18 # GND);

--YB1L22 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9~COUT
YB1L22 = CARRY(!YB1L18 # !YB1_safe_q[9]);


--YB1L20 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9~9
YB1L20 = !YB1L22;


--C1_inst4 is delay_reset_block:inst3|inst4
C1_inst4 = !KEY[0] # !YB1L20;


--W1_tri_state_bridge_0_address[21] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[21]
W1_tri_state_bridge_0_address[21] = DFFEAS(W1L84, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[20] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]
W1_tri_state_bridge_0_address[20] = DFFEAS(W1L83, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[19] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19]
W1_tri_state_bridge_0_address[19] = DFFEAS(W1L82, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[18] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18]
W1_tri_state_bridge_0_address[18] = DFFEAS(W1L81, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[17] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17]
W1_tri_state_bridge_0_address[17] = DFFEAS(W1L80, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[16] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16]
W1_tri_state_bridge_0_address[16] = DFFEAS(W1L79, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[15] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15]
W1_tri_state_bridge_0_address[15] = DFFEAS(W1L78, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[14] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14]
W1_tri_state_bridge_0_address[14] = DFFEAS(W1L77, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[13] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13]
W1_tri_state_bridge_0_address[13] = DFFEAS(W1L76, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[12] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]
W1_tri_state_bridge_0_address[12] = DFFEAS(W1L75, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[11] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11]
W1_tri_state_bridge_0_address[11] = DFFEAS(W1L74, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[10] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]
W1_tri_state_bridge_0_address[10] = DFFEAS(W1L73, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[9] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]
W1_tri_state_bridge_0_address[9] = DFFEAS(W1L72, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[8] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8]
W1_tri_state_bridge_0_address[8] = DFFEAS(W1L71, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[7] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]
W1_tri_state_bridge_0_address[7] = DFFEAS(W1L70, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[6] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]
W1_tri_state_bridge_0_address[6] = DFFEAS(W1L69, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[5] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]
W1_tri_state_bridge_0_address[5] = DFFEAS(W1L68, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[4] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4]
W1_tri_state_bridge_0_address[4] = DFFEAS(W1L67, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[3] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3]
W1_tri_state_bridge_0_address[3] = DFFEAS(W1L66, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2]
W1_tri_state_bridge_0_address[2] = DFFEAS(W1L65, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1]
W1_tri_state_bridge_0_address[1] = DFFEAS(W1L64, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[0]
W1_tri_state_bridge_0_address[0] = DFFEAS(W1L63, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--A1L6 is altera_internal_jtag~TDO
A1L6 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]
W1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(W1L118, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_F_pc[20] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[20]
H1_F_pc[20] = AMPP_FUNCTION(CLOCK_50, H1L593, E1_data_out, H1_W_valid);


--H1_i_read is DE2_Board:inst|cpu_0:the_cpu_0|i_read
H1_i_read = AMPP_FUNCTION(CLOCK_50, H1_i_read_nxt, E1_data_out);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L28 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~57
W1L28 = H1_F_pc[20] & !H1_i_read & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0];


--W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable
W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(W1L143, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1
W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L59, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_W_alu_result[22] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[22]
H1_W_alu_result[22] = AMPP_FUNCTION(CLOCK_50, H1L735, H1_E_shift_rot_result[22], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_d_read is DE2_Board:inst|cpu_0:the_cpu_0|d_read
H1_d_read = AMPP_FUNCTION(CLOCK_50, H1_d_read_nxt, E1_data_out);


--AB1_d_write is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write
AB1_d_write = AMPP_FUNCTION(CLOCK_50, H1_d_write_nxt, E1_data_out);


--W1_cpu_0_data_master_requests_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1
W1_cpu_0_data_master_requests_cfi_flash_0_s1 = H1_W_alu_result[22] & (H1_d_read # AB1_d_write);


--W1L29 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~58
W1L29 = W1L28 & (!W1_cpu_0_data_master_requests_cfi_flash_0_s1 # !W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1
W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L61, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L135 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~99
W1L135 = H1_F_pc[20] & W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & !H1_i_read;


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1L25, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L19 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176
W1L19 = H1_d_read & (W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]);


--W1L20 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~177
W1L20 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & !W1L19 & (!W1L135 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--J1_cpu_0_data_master_dbs_address[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0]
J1_cpu_0_data_master_dbs_address[0] = DFFEAS(J1L8, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_d_byteenable[3] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[3]
H1_d_byteenable[3] = AMPP_FUNCTION(CLOCK_50, H1L183, E1_data_out);


--H1_d_byteenable[1] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[1]
H1_d_byteenable[1] = AMPP_FUNCTION(CLOCK_50, H1L181, E1_data_out);


--J1_cpu_0_data_master_dbs_address[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]
J1_cpu_0_data_master_dbs_address[1] = DFFEAS(J1L10, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L17 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~333
W1L17 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[3] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[1]));


--H1_d_byteenable[2] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[2]
H1_d_byteenable[2] = AMPP_FUNCTION(CLOCK_50, H1L182, E1_data_out);


--H1_d_byteenable[0] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[0]
H1_d_byteenable[0] = AMPP_FUNCTION(CLOCK_50, H1L185, E1_data_out);


--T1L5 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_byteenable_payload_buffer_s1[0]~60
T1L5 = J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[2] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[0]);


--W1L18 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~334
W1L18 = W1L17 # T1L5 & !J1_cpu_0_data_master_dbs_address[0];


--J1_cpu_0_data_master_no_byte_enables_and_last_term is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term
J1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(J1L179, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L21 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~178
W1L21 = W1L20 & (W1L18 & !J1_cpu_0_data_master_no_byte_enables_and_last_term # !AB1_d_write);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]
W1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(W1L115, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L62 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash_0~0
W1L62 = W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (W1L29 # W1L21) # !W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0] & (W1L29 # W1L21);


--E1_data_out is DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_out
E1_data_out = DFFEAS(E1_data_in_d1, CLOCK_50, !C1_inst4,  ,  ,  ,  ,  ,  );


--W1L27 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_granted_cfi_flash_0_s1~29
W1L27 = W1L29 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1L21 # !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1L137 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31
W1L137 = W1L21 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !W1L29 & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1_cfi_flash_0_s1_in_a_read_cycle is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle
W1_cfi_flash_0_s1_in_a_read_cycle = W1L27 # H1_d_read & W1L137;


--W1_cfi_flash_0_s1_wait_counter[3] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3]
W1_cfi_flash_0_s1_wait_counter[3] = DFFEAS(W1L8, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_reasons_to_wait is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait
W1_d1_reasons_to_wait = DFFEAS(W1L134, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L131 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~36
W1L131 = !W1_d1_reasons_to_wait & (W1L29 # W1L21);


--W1L85 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_readn~1
W1L85 = W1_cfi_flash_0_s1_in_a_read_cycle & !W1_cfi_flash_0_s1_wait_counter[3] & !W1L131;


--W1_in_a_write_cycle is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle
W1_in_a_write_cycle = !W1L137 # !AB1_d_write;


--W1_cfi_flash_0_s1_wait_counter[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[2]
W1_cfi_flash_0_s1_wait_counter[2] = DFFEAS(W1L7, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cfi_flash_0_s1_wait_counter[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1]
W1_cfi_flash_0_s1_wait_counter[1] = DFFEAS(W1L5, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L86 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~104
W1L86 = !W1_cfi_flash_0_s1_wait_counter[2] & !W1_cfi_flash_0_s1_wait_counter[1];


--W1L87 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~105
W1L87 = !W1_in_a_write_cycle & !W1L131 & (W1_cfi_flash_0_s1_wait_counter[3] $ !W1L86);


--H1_W_alu_result[21] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[21]
H1_W_alu_result[21] = AMPP_FUNCTION(CLOCK_50, H1L732, H1_E_shift_rot_result[21], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[19] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[19]
H1_F_pc[19] = AMPP_FUNCTION(CLOCK_50, H1L586, H1L815, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L84 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[21]~198
W1L84 = W1L137 & H1_W_alu_result[21] # !W1L137 & (H1_F_pc[19]);


--H1_W_alu_result[20] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[20]
H1_W_alu_result[20] = AMPP_FUNCTION(CLOCK_50, H1L729, H1_E_shift_rot_result[20], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[18] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[18]
H1_F_pc[18] = AMPP_FUNCTION(CLOCK_50, H1L583, H1L813, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L83 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[20]~199
W1L83 = W1L137 & H1_W_alu_result[20] # !W1L137 & (H1_F_pc[18]);


--H1_W_alu_result[19] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[19]
H1_W_alu_result[19] = AMPP_FUNCTION(CLOCK_50, H1L726, H1_E_shift_rot_result[19], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[17] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[17]
H1_F_pc[17] = AMPP_FUNCTION(CLOCK_50, H1L580, H1L811, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L82 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[19]~200
W1L82 = W1L137 & H1_W_alu_result[19] # !W1L137 & (H1_F_pc[17]);


--H1_W_alu_result[18] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[18]
H1_W_alu_result[18] = AMPP_FUNCTION(CLOCK_50, H1L723, H1_E_shift_rot_result[18], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[16] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[16]
H1_F_pc[16] = AMPP_FUNCTION(CLOCK_50, H1L577, H1L809, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L81 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[18]~201
W1L81 = W1L137 & H1_W_alu_result[18] # !W1L137 & (H1_F_pc[16]);


--H1_W_alu_result[17] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[17]
H1_W_alu_result[17] = AMPP_FUNCTION(CLOCK_50, H1L720, H1_E_shift_rot_result[17], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[15] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[15]
H1_F_pc[15] = AMPP_FUNCTION(CLOCK_50, H1L574, H1L807, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L80 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[17]~202
W1L80 = W1L137 & H1_W_alu_result[17] # !W1L137 & (H1_F_pc[15]);


--H1_W_alu_result[16] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[16]
H1_W_alu_result[16] = AMPP_FUNCTION(CLOCK_50, H1L717, H1_E_shift_rot_result[16], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[14] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[14]
H1_F_pc[14] = AMPP_FUNCTION(CLOCK_50, H1L571, H1L805, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L79 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[16]~203
W1L79 = W1L137 & H1_W_alu_result[16] # !W1L137 & (H1_F_pc[14]);


--H1_W_alu_result[15] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[15]
H1_W_alu_result[15] = AMPP_FUNCTION(CLOCK_50, H1L714, H1_E_shift_rot_result[15], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[13] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[13]
H1_F_pc[13] = AMPP_FUNCTION(CLOCK_50, H1L568, H1L803, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L78 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[15]~204
W1L78 = W1L137 & H1_W_alu_result[15] # !W1L137 & (H1_F_pc[13]);


--H1_W_alu_result[14] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[14]
H1_W_alu_result[14] = AMPP_FUNCTION(CLOCK_50, H1L711, H1_E_shift_rot_result[14], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[12] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[12]
H1_F_pc[12] = AMPP_FUNCTION(CLOCK_50, H1L565, H1L801, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L77 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[14]~205
W1L77 = W1L137 & H1_W_alu_result[14] # !W1L137 & (H1_F_pc[12]);


--H1_W_alu_result[13] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[13]
H1_W_alu_result[13] = AMPP_FUNCTION(CLOCK_50, H1L708, H1_E_shift_rot_result[13], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[11] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[11]
H1_F_pc[11] = AMPP_FUNCTION(CLOCK_50, H1L562, H1L799, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L76 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[13]~206
W1L76 = W1L137 & H1_W_alu_result[13] # !W1L137 & (H1_F_pc[11]);


--H1_W_alu_result[12] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[12]
H1_W_alu_result[12] = AMPP_FUNCTION(CLOCK_50, H1L705, H1_E_shift_rot_result[12], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[10] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[10]
H1_F_pc[10] = AMPP_FUNCTION(CLOCK_50, H1L559, H1L797, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L75 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[12]~207
W1L75 = W1L137 & H1_W_alu_result[12] # !W1L137 & (H1_F_pc[10]);


--H1_W_alu_result[11] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[11]
H1_W_alu_result[11] = AMPP_FUNCTION(CLOCK_50, H1L702, H1_E_shift_rot_result[11], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[9] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[9]
H1_F_pc[9] = AMPP_FUNCTION(CLOCK_50, H1L556, H1L795, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L74 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[11]~208
W1L74 = W1L137 & H1_W_alu_result[11] # !W1L137 & (H1_F_pc[9]);


--H1_W_alu_result[10] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[10]
H1_W_alu_result[10] = AMPP_FUNCTION(CLOCK_50, H1L699, H1_E_shift_rot_result[10], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[8] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[8]
H1_F_pc[8] = AMPP_FUNCTION(CLOCK_50, H1L553, H1L793, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L73 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[10]~209
W1L73 = W1L137 & H1_W_alu_result[10] # !W1L137 & (H1_F_pc[8]);


--H1_W_alu_result[9] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[9]
H1_W_alu_result[9] = AMPP_FUNCTION(CLOCK_50, H1L696, H1_E_shift_rot_result[9], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[7] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[7]
H1_F_pc[7] = AMPP_FUNCTION(CLOCK_50, H1L550, H1L791, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L72 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[9]~210
W1L72 = W1L137 & H1_W_alu_result[9] # !W1L137 & (H1_F_pc[7]);


--H1_W_alu_result[8] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[8]
H1_W_alu_result[8] = AMPP_FUNCTION(CLOCK_50, H1L693, H1_E_shift_rot_result[8], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[6] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[6]
H1_F_pc[6] = AMPP_FUNCTION(CLOCK_50, H1L547, H1L789, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L71 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[8]~211
W1L71 = W1L137 & H1_W_alu_result[8] # !W1L137 & (H1_F_pc[6]);


--H1_W_alu_result[7] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[7]
H1_W_alu_result[7] = AMPP_FUNCTION(CLOCK_50, H1L690, H1_E_shift_rot_result[7], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[5] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[5]
H1_F_pc[5] = AMPP_FUNCTION(CLOCK_50, H1L544, H1L787, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L70 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[7]~212
W1L70 = W1L137 & H1_W_alu_result[7] # !W1L137 & (H1_F_pc[5]);


--H1_W_alu_result[6] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[6]
H1_W_alu_result[6] = AMPP_FUNCTION(CLOCK_50, H1L687, H1_E_shift_rot_result[6], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[4] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[4]
H1_F_pc[4] = AMPP_FUNCTION(CLOCK_50, H1L541, H1L785, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L69 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[6]~213
W1L69 = W1L137 & H1_W_alu_result[6] # !W1L137 & (H1_F_pc[4]);


--H1_W_alu_result[5] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[5]
H1_W_alu_result[5] = AMPP_FUNCTION(CLOCK_50, H1L684, H1_E_shift_rot_result[5], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[3] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[3]
H1_F_pc[3] = AMPP_FUNCTION(CLOCK_50, H1L590, E1_data_out, H1_W_valid);


--W1L68 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[5]~214
W1L68 = W1L137 & H1_W_alu_result[5] # !W1L137 & (H1_F_pc[3]);


--H1_W_alu_result[4] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[4]
H1_W_alu_result[4] = AMPP_FUNCTION(CLOCK_50, H1L681, H1_E_shift_rot_result[4], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[2] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[2]
H1_F_pc[2] = AMPP_FUNCTION(CLOCK_50, H1L537, H1L781, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L67 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[4]~215
W1L67 = W1L137 & H1_W_alu_result[4] # !W1L137 & (H1_F_pc[2]);


--H1_W_alu_result[3] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[3]
H1_W_alu_result[3] = AMPP_FUNCTION(CLOCK_50, H1L678, H1_E_shift_rot_result[3], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[1] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[1]
H1_F_pc[1] = AMPP_FUNCTION(CLOCK_50, H1L534, H1L779, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L66 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[3]~216
W1L66 = W1L137 & H1_W_alu_result[3] # !W1L137 & (H1_F_pc[1]);


--H1_W_alu_result[2] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[2]
H1_W_alu_result[2] = AMPP_FUNCTION(CLOCK_50, H1L675, H1_E_shift_rot_result[2], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[0] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[0]
H1_F_pc[0] = AMPP_FUNCTION(CLOCK_50, H1L531, H1L777, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L65 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[2]~217
W1L65 = W1L137 & H1_W_alu_result[2] # !W1L137 & (H1_F_pc[0]);


--K1_cpu_0_instruction_master_dbs_address[1] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[1]
K1_cpu_0_instruction_master_dbs_address[1] = DFFEAS(K1L10, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L64 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[1]~218
W1L64 = W1L137 & J1_cpu_0_data_master_dbs_address[1] # !W1L137 & (K1_cpu_0_instruction_master_dbs_address[1]);


--K1_cpu_0_instruction_master_dbs_address[0] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[0]
K1_cpu_0_instruction_master_dbs_address[0] = DFFEAS(K1L8, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L63 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[0]~219
W1L63 = W1L137 & J1_cpu_0_data_master_dbs_address[0] # !W1L137 & (K1_cpu_0_instruction_master_dbs_address[0]);


--D1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
D1_hub_tdo = AMPP_FUNCTION(!A1L5, D1L13, !DC1_state[8]);


--W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0]
W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(W1L27, CLOCK_50, E1_data_out,  , W1L130,  ,  ,  ,  );


--W1L136 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~100
W1L136 = W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable & (W1L135 # W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 & W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--W1L129 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_winner[0]~39
W1L129 = W1L136 & W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] # !W1L136 & (W1L27 # W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[0] & !W1L137);


--W1_cfi_flash_0_s1_wait_counter[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0]
W1_cfi_flash_0_s1_wait_counter[0] = DFFEAS(W1L3, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--A1L62 is rtl~6
A1L62 = W1_cfi_flash_0_s1_wait_counter[3] # W1_cfi_flash_0_s1_wait_counter[2] # W1_cfi_flash_0_s1_wait_counter[1] # W1_cfi_flash_0_s1_wait_counter[0];


--W1L16 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_waits_for_read~15
W1L16 = A1L62 # !W1_d1_reasons_to_wait & (W1L29 # W1L21);


--W1L133 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~27
W1L133 = W1L27 # W1L137 & (H1_d_read # AB1_d_write);


--W1L117 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]~186
W1L117 = W1L16 & (W1L133 & W1L137 # !W1L133 & (W1L129)) # !W1L16 & (W1L129);


--W1L118 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]~187
W1L118 = W1L62 & W1L117 # !W1L62 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1]);


--H1_R_ctrl_exception is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_exception
H1_R_ctrl_exception = AMPP_FUNCTION(CLOCK_50, H1_D_ctrl_exception, E1_data_out);


--H1_R_ctrl_break is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_break
H1_R_ctrl_break = AMPP_FUNCTION(CLOCK_50, H1L16, E1_data_out);


--H1L591 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc_nxt[20]~769
H1L591 = AMPP_FUNCTION(H1_R_ctrl_exception, H1_R_ctrl_break);


--H1L777 is DE2_Board:inst|cpu_0:the_cpu_0|add~1425
H1L777 = AMPP_FUNCTION(H1_F_pc[0], GND);

--H1L778 is DE2_Board:inst|cpu_0:the_cpu_0|add~1426
H1L778 = AMPP_FUNCTION(H1_F_pc[0]);


--H1L779 is DE2_Board:inst|cpu_0:the_cpu_0|add~1427
H1L779 = AMPP_FUNCTION(H1_F_pc[1], GND, H1L778);

--H1L780 is DE2_Board:inst|cpu_0:the_cpu_0|add~1428
H1L780 = AMPP_FUNCTION(H1_F_pc[1], H1L778);


--H1L781 is DE2_Board:inst|cpu_0:the_cpu_0|add~1429
H1L781 = AMPP_FUNCTION(H1_F_pc[2], GND, H1L780);

--H1L782 is DE2_Board:inst|cpu_0:the_cpu_0|add~1430
H1L782 = AMPP_FUNCTION(H1_F_pc[2], H1L780);


--H1L783 is DE2_Board:inst|cpu_0:the_cpu_0|add~1431
H1L783 = AMPP_FUNCTION(H1_F_pc[3], GND, H1L782);

--H1L784 is DE2_Board:inst|cpu_0:the_cpu_0|add~1432
H1L784 = AMPP_FUNCTION(H1_F_pc[3], H1L782);


--H1L785 is DE2_Board:inst|cpu_0:the_cpu_0|add~1433
H1L785 = AMPP_FUNCTION(H1_F_pc[4], GND, H1L784);

--H1L786 is DE2_Board:inst|cpu_0:the_cpu_0|add~1434
H1L786 = AMPP_FUNCTION(H1_F_pc[4], H1L784);


--H1L787 is DE2_Board:inst|cpu_0:the_cpu_0|add~1435
H1L787 = AMPP_FUNCTION(H1_F_pc[5], GND, H1L786);

--H1L788 is DE2_Board:inst|cpu_0:the_cpu_0|add~1436
H1L788 = AMPP_FUNCTION(H1_F_pc[5], H1L786);


--H1L789 is DE2_Board:inst|cpu_0:the_cpu_0|add~1437
H1L789 = AMPP_FUNCTION(H1_F_pc[6], GND, H1L788);

--H1L790 is DE2_Board:inst|cpu_0:the_cpu_0|add~1438
H1L790 = AMPP_FUNCTION(H1_F_pc[6], H1L788);


--H1L791 is DE2_Board:inst|cpu_0:the_cpu_0|add~1439
H1L791 = AMPP_FUNCTION(H1_F_pc[7], GND, H1L790);

--H1L792 is DE2_Board:inst|cpu_0:the_cpu_0|add~1440
H1L792 = AMPP_FUNCTION(H1_F_pc[7], H1L790);


--H1L793 is DE2_Board:inst|cpu_0:the_cpu_0|add~1441
H1L793 = AMPP_FUNCTION(H1_F_pc[8], GND, H1L792);

--H1L794 is DE2_Board:inst|cpu_0:the_cpu_0|add~1442
H1L794 = AMPP_FUNCTION(H1_F_pc[8], H1L792);


--H1L795 is DE2_Board:inst|cpu_0:the_cpu_0|add~1443
H1L795 = AMPP_FUNCTION(H1_F_pc[9], GND, H1L794);

--H1L796 is DE2_Board:inst|cpu_0:the_cpu_0|add~1444
H1L796 = AMPP_FUNCTION(H1_F_pc[9], H1L794);


--H1L797 is DE2_Board:inst|cpu_0:the_cpu_0|add~1445
H1L797 = AMPP_FUNCTION(H1_F_pc[10], GND, H1L796);

--H1L798 is DE2_Board:inst|cpu_0:the_cpu_0|add~1446
H1L798 = AMPP_FUNCTION(H1_F_pc[10], H1L796);


--H1L799 is DE2_Board:inst|cpu_0:the_cpu_0|add~1447
H1L799 = AMPP_FUNCTION(H1_F_pc[11], GND, H1L798);

--H1L800 is DE2_Board:inst|cpu_0:the_cpu_0|add~1448
H1L800 = AMPP_FUNCTION(H1_F_pc[11], H1L798);


--H1L801 is DE2_Board:inst|cpu_0:the_cpu_0|add~1449
H1L801 = AMPP_FUNCTION(H1_F_pc[12], GND, H1L800);

--H1L802 is DE2_Board:inst|cpu_0:the_cpu_0|add~1450
H1L802 = AMPP_FUNCTION(H1_F_pc[12], H1L800);


--H1L803 is DE2_Board:inst|cpu_0:the_cpu_0|add~1451
H1L803 = AMPP_FUNCTION(H1_F_pc[13], GND, H1L802);

--H1L804 is DE2_Board:inst|cpu_0:the_cpu_0|add~1452
H1L804 = AMPP_FUNCTION(H1_F_pc[13], H1L802);


--H1L805 is DE2_Board:inst|cpu_0:the_cpu_0|add~1453
H1L805 = AMPP_FUNCTION(H1_F_pc[14], GND, H1L804);

--H1L806 is DE2_Board:inst|cpu_0:the_cpu_0|add~1454
H1L806 = AMPP_FUNCTION(H1_F_pc[14], H1L804);


--H1L807 is DE2_Board:inst|cpu_0:the_cpu_0|add~1455
H1L807 = AMPP_FUNCTION(H1_F_pc[15], GND, H1L806);

--H1L808 is DE2_Board:inst|cpu_0:the_cpu_0|add~1456
H1L808 = AMPP_FUNCTION(H1_F_pc[15], H1L806);


--H1L809 is DE2_Board:inst|cpu_0:the_cpu_0|add~1457
H1L809 = AMPP_FUNCTION(H1_F_pc[16], GND, H1L808);

--H1L810 is DE2_Board:inst|cpu_0:the_cpu_0|add~1458
H1L810 = AMPP_FUNCTION(H1_F_pc[16], H1L808);


--H1L811 is DE2_Board:inst|cpu_0:the_cpu_0|add~1459
H1L811 = AMPP_FUNCTION(H1_F_pc[17], GND, H1L810);

--H1L812 is DE2_Board:inst|cpu_0:the_cpu_0|add~1460
H1L812 = AMPP_FUNCTION(H1_F_pc[17], H1L810);


--H1L813 is DE2_Board:inst|cpu_0:the_cpu_0|add~1461
H1L813 = AMPP_FUNCTION(H1_F_pc[18], GND, H1L812);

--H1L814 is DE2_Board:inst|cpu_0:the_cpu_0|add~1462
H1L814 = AMPP_FUNCTION(H1_F_pc[18], H1L812);


--H1L815 is DE2_Board:inst|cpu_0:the_cpu_0|add~1463
H1L815 = AMPP_FUNCTION(H1_F_pc[19], GND, H1L814);

--H1L816 is DE2_Board:inst|cpu_0:the_cpu_0|add~1464
H1L816 = AMPP_FUNCTION(H1_F_pc[19], H1L814);


--H1L817 is DE2_Board:inst|cpu_0:the_cpu_0|add~1465
H1L817 = AMPP_FUNCTION(H1_F_pc[20], H1L816);


--H1_E_src2[22] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[22]
H1_E_src2[22] = AMPP_FUNCTION(CLOCK_50, H1L380, H1_D_iw[12], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[22] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[22]
H1_E_src1[22] = AMPP_FUNCTION(CLOCK_50, H1L333, H1L817, E1_data_out, H1L639);


--H1_E_src2[21] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[21]
H1_E_src2[21] = AMPP_FUNCTION(CLOCK_50, H1L377, H1_D_iw[11], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[21] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[21]
H1_E_src1[21] = AMPP_FUNCTION(CLOCK_50, H1L330, H1L815, E1_data_out, H1L639);


--H1_E_src2[20] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[20]
H1_E_src2[20] = AMPP_FUNCTION(CLOCK_50, H1L374, H1_D_iw[10], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[20] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[20]
H1_E_src1[20] = AMPP_FUNCTION(CLOCK_50, H1L327, H1L813, E1_data_out, H1L639);


--H1_E_src2[19] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[19]
H1_E_src2[19] = AMPP_FUNCTION(CLOCK_50, H1L371, H1_D_iw[9], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[19] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[19]
H1_E_src1[19] = AMPP_FUNCTION(CLOCK_50, H1L324, H1L811, E1_data_out, H1L639);


--H1_E_src2[18] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[18]
H1_E_src2[18] = AMPP_FUNCTION(CLOCK_50, H1L368, H1_D_iw[8], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[18] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[18]
H1_E_src1[18] = AMPP_FUNCTION(CLOCK_50, H1L321, H1L809, E1_data_out, H1L639);


--H1_E_src2[17] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[17]
H1_E_src2[17] = AMPP_FUNCTION(CLOCK_50, H1L365, H1_D_iw[7], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[17] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[17]
H1_E_src1[17] = AMPP_FUNCTION(CLOCK_50, H1L318, H1L807, E1_data_out, H1L639);


--H1_E_src2[16] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[16]
H1_E_src2[16] = AMPP_FUNCTION(CLOCK_50, H1L362, H1_D_iw[6], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[16] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[16]
H1_E_src1[16] = AMPP_FUNCTION(CLOCK_50, H1L315, H1L805, E1_data_out, H1L639);


--H1_E_src2[15] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[15]
H1_E_src2[15] = AMPP_FUNCTION(CLOCK_50, H1L659, E1_data_out);


--H1_E_src1[15] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[15]
H1_E_src1[15] = AMPP_FUNCTION(CLOCK_50, H1L312, H1L803, E1_data_out, H1L639);


--H1_E_src2[14] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[14]
H1_E_src2[14] = AMPP_FUNCTION(CLOCK_50, H1L658, E1_data_out);


--H1_E_src1[14] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[14]
H1_E_src1[14] = AMPP_FUNCTION(CLOCK_50, H1L309, H1L801, E1_data_out, H1L639);


--H1_E_src2[13] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[13]
H1_E_src2[13] = AMPP_FUNCTION(CLOCK_50, H1L657, E1_data_out);


--H1_E_src1[13] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[13]
H1_E_src1[13] = AMPP_FUNCTION(CLOCK_50, H1L306, H1L799, E1_data_out, H1L639);


--H1_E_src2[12] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[12]
H1_E_src2[12] = AMPP_FUNCTION(CLOCK_50, H1L656, E1_data_out);


--H1_E_src1[12] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[12]
H1_E_src1[12] = AMPP_FUNCTION(CLOCK_50, H1L303, H1L797, E1_data_out, H1L639);


--H1_E_src2[11] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[11]
H1_E_src2[11] = AMPP_FUNCTION(CLOCK_50, H1L655, E1_data_out);


--H1_E_src1[11] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[11]
H1_E_src1[11] = AMPP_FUNCTION(CLOCK_50, H1L300, H1L795, E1_data_out, H1L639);


--H1_E_src2[10] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[10]
H1_E_src2[10] = AMPP_FUNCTION(CLOCK_50, H1L654, E1_data_out);


--H1_E_src1[10] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[10]
H1_E_src1[10] = AMPP_FUNCTION(CLOCK_50, H1L297, H1L793, E1_data_out, H1L639);


--H1_E_src2[9] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[9]
H1_E_src2[9] = AMPP_FUNCTION(CLOCK_50, H1L653, E1_data_out);


--H1_E_src1[9] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[9]
H1_E_src1[9] = AMPP_FUNCTION(CLOCK_50, H1L294, H1L791, E1_data_out, H1L639);


--H1_E_src2[8] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[8]
H1_E_src2[8] = AMPP_FUNCTION(CLOCK_50, H1L652, E1_data_out);


--H1_E_src1[8] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[8]
H1_E_src1[8] = AMPP_FUNCTION(CLOCK_50, H1L291, H1L789, E1_data_out, H1L639);


--H1_E_src2[7] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[7]
H1_E_src2[7] = AMPP_FUNCTION(CLOCK_50, H1L651, E1_data_out);


--H1_E_src1[7] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[7]
H1_E_src1[7] = AMPP_FUNCTION(CLOCK_50, H1L288, H1L787, E1_data_out, H1L639);


--H1_E_src2[6] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[6]
H1_E_src2[6] = AMPP_FUNCTION(CLOCK_50, H1L650, E1_data_out);


--H1_E_src1[6] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[6]
H1_E_src1[6] = AMPP_FUNCTION(CLOCK_50, H1L285, H1L785, E1_data_out, H1L639);


--H1_E_src2[5] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[5]
H1_E_src2[5] = AMPP_FUNCTION(CLOCK_50, H1L649, E1_data_out);


--H1_E_src1[5] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[5]
H1_E_src1[5] = AMPP_FUNCTION(CLOCK_50, H1L282, H1L783, E1_data_out, H1L639);


--H1_E_src2[4] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[4]
H1_E_src2[4] = AMPP_FUNCTION(CLOCK_50, H1L648, E1_data_out);


--H1_E_src1[4] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[4]
H1_E_src1[4] = AMPP_FUNCTION(CLOCK_50, H1L279, H1L781, E1_data_out, H1L639);


--H1_E_src2[3] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[3]
H1_E_src2[3] = AMPP_FUNCTION(CLOCK_50, H1L647, E1_data_out);


--H1_E_src1[3] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[3]
H1_E_src1[3] = AMPP_FUNCTION(CLOCK_50, H1L276, H1L779, E1_data_out, H1L639);


--H1_E_src2[2] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[2]
H1_E_src2[2] = AMPP_FUNCTION(CLOCK_50, H1L646, E1_data_out);


--H1_E_src1[2] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[2]
H1_E_src1[2] = AMPP_FUNCTION(CLOCK_50, H1L273, H1L777, E1_data_out, H1L639);


--H1_E_src2[1] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[1]
H1_E_src2[1] = AMPP_FUNCTION(CLOCK_50, H1L645, E1_data_out);


--H1_E_src1[1] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[1]
H1_E_src1[1] = AMPP_FUNCTION(CLOCK_50, H1L629, E1_data_out);


--H1_E_src2[0] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[0]
H1_E_src2[0] = AMPP_FUNCTION(CLOCK_50, H1L644, E1_data_out);


--H1_E_src1[0] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[0]
H1_E_src1[0] = AMPP_FUNCTION(CLOCK_50, H1L628, E1_data_out);


--H1L819 is DE2_Board:inst|cpu_0:the_cpu_0|add~1467
H1L819 = AMPP_FUNCTION(H1_E_src2[0], H1_E_src1[0], GND);

--H1L820 is DE2_Board:inst|cpu_0:the_cpu_0|add~1468
H1L820 = AMPP_FUNCTION(H1_E_src2[0], H1_E_src1[0]);


--H1L821 is DE2_Board:inst|cpu_0:the_cpu_0|add~1469
H1L821 = AMPP_FUNCTION(H1_E_src2[1], H1_E_src1[1], GND, H1L820);

--H1L822 is DE2_Board:inst|cpu_0:the_cpu_0|add~1470
H1L822 = AMPP_FUNCTION(H1_E_src2[1], H1_E_src1[1], H1L820);


--H1L823 is DE2_Board:inst|cpu_0:the_cpu_0|add~1471
H1L823 = AMPP_FUNCTION(H1_E_src2[2], H1_E_src1[2], GND, H1L822);

--H1L824 is DE2_Board:inst|cpu_0:the_cpu_0|add~1472
H1L824 = AMPP_FUNCTION(H1_E_src2[2], H1_E_src1[2], H1L822);


--H1L825 is DE2_Board:inst|cpu_0:the_cpu_0|add~1473
H1L825 = AMPP_FUNCTION(H1_E_src2[3], H1_E_src1[3], GND, H1L824);

--H1L826 is DE2_Board:inst|cpu_0:the_cpu_0|add~1474
H1L826 = AMPP_FUNCTION(H1_E_src2[3], H1_E_src1[3], H1L824);


--H1L827 is DE2_Board:inst|cpu_0:the_cpu_0|add~1475
H1L827 = AMPP_FUNCTION(H1_E_src2[4], H1_E_src1[4], GND, H1L826);

--H1L828 is DE2_Board:inst|cpu_0:the_cpu_0|add~1476
H1L828 = AMPP_FUNCTION(H1_E_src2[4], H1_E_src1[4], H1L826);


--H1L829 is DE2_Board:inst|cpu_0:the_cpu_0|add~1477
H1L829 = AMPP_FUNCTION(H1_E_src2[5], H1_E_src1[5], GND, H1L828);

--H1L830 is DE2_Board:inst|cpu_0:the_cpu_0|add~1478
H1L830 = AMPP_FUNCTION(H1_E_src2[5], H1_E_src1[5], H1L828);


--H1L831 is DE2_Board:inst|cpu_0:the_cpu_0|add~1479
H1L831 = AMPP_FUNCTION(H1_E_src2[6], H1_E_src1[6], GND, H1L830);

--H1L832 is DE2_Board:inst|cpu_0:the_cpu_0|add~1480
H1L832 = AMPP_FUNCTION(H1_E_src2[6], H1_E_src1[6], H1L830);


--H1L833 is DE2_Board:inst|cpu_0:the_cpu_0|add~1481
H1L833 = AMPP_FUNCTION(H1_E_src2[7], H1_E_src1[7], GND, H1L832);

--H1L834 is DE2_Board:inst|cpu_0:the_cpu_0|add~1482
H1L834 = AMPP_FUNCTION(H1_E_src2[7], H1_E_src1[7], H1L832);


--H1L835 is DE2_Board:inst|cpu_0:the_cpu_0|add~1483
H1L835 = AMPP_FUNCTION(H1_E_src2[8], H1_E_src1[8], GND, H1L834);

--H1L836 is DE2_Board:inst|cpu_0:the_cpu_0|add~1484
H1L836 = AMPP_FUNCTION(H1_E_src2[8], H1_E_src1[8], H1L834);


--H1L837 is DE2_Board:inst|cpu_0:the_cpu_0|add~1485
H1L837 = AMPP_FUNCTION(H1_E_src2[9], H1_E_src1[9], GND, H1L836);

--H1L838 is DE2_Board:inst|cpu_0:the_cpu_0|add~1486
H1L838 = AMPP_FUNCTION(H1_E_src2[9], H1_E_src1[9], H1L836);


--H1L839 is DE2_Board:inst|cpu_0:the_cpu_0|add~1487
H1L839 = AMPP_FUNCTION(H1_E_src2[10], H1_E_src1[10], GND, H1L838);

--H1L840 is DE2_Board:inst|cpu_0:the_cpu_0|add~1488
H1L840 = AMPP_FUNCTION(H1_E_src2[10], H1_E_src1[10], H1L838);


--H1L841 is DE2_Board:inst|cpu_0:the_cpu_0|add~1489
H1L841 = AMPP_FUNCTION(H1_E_src2[11], H1_E_src1[11], GND, H1L840);

--H1L842 is DE2_Board:inst|cpu_0:the_cpu_0|add~1490
H1L842 = AMPP_FUNCTION(H1_E_src2[11], H1_E_src1[11], H1L840);


--H1L843 is DE2_Board:inst|cpu_0:the_cpu_0|add~1491
H1L843 = AMPP_FUNCTION(H1_E_src2[12], H1_E_src1[12], GND, H1L842);

--H1L844 is DE2_Board:inst|cpu_0:the_cpu_0|add~1492
H1L844 = AMPP_FUNCTION(H1_E_src2[12], H1_E_src1[12], H1L842);


--H1L845 is DE2_Board:inst|cpu_0:the_cpu_0|add~1493
H1L845 = AMPP_FUNCTION(H1_E_src2[13], H1_E_src1[13], GND, H1L844);

--H1L846 is DE2_Board:inst|cpu_0:the_cpu_0|add~1494
H1L846 = AMPP_FUNCTION(H1_E_src2[13], H1_E_src1[13], H1L844);


--H1L847 is DE2_Board:inst|cpu_0:the_cpu_0|add~1495
H1L847 = AMPP_FUNCTION(H1_E_src2[14], H1_E_src1[14], GND, H1L846);

--H1L848 is DE2_Board:inst|cpu_0:the_cpu_0|add~1496
H1L848 = AMPP_FUNCTION(H1_E_src2[14], H1_E_src1[14], H1L846);


--H1L849 is DE2_Board:inst|cpu_0:the_cpu_0|add~1497
H1L849 = AMPP_FUNCTION(H1_E_src2[15], H1_E_src1[15], GND, H1L848);

--H1L850 is DE2_Board:inst|cpu_0:the_cpu_0|add~1498
H1L850 = AMPP_FUNCTION(H1_E_src2[15], H1_E_src1[15], H1L848);


--H1L851 is DE2_Board:inst|cpu_0:the_cpu_0|add~1499
H1L851 = AMPP_FUNCTION(H1_E_src2[16], H1_E_src1[16], GND, H1L850);

--H1L852 is DE2_Board:inst|cpu_0:the_cpu_0|add~1500
H1L852 = AMPP_FUNCTION(H1_E_src2[16], H1_E_src1[16], H1L850);


--H1L853 is DE2_Board:inst|cpu_0:the_cpu_0|add~1501
H1L853 = AMPP_FUNCTION(H1_E_src2[17], H1_E_src1[17], GND, H1L852);

--H1L854 is DE2_Board:inst|cpu_0:the_cpu_0|add~1502
H1L854 = AMPP_FUNCTION(H1_E_src2[17], H1_E_src1[17], H1L852);


--H1L855 is DE2_Board:inst|cpu_0:the_cpu_0|add~1503
H1L855 = AMPP_FUNCTION(H1_E_src2[18], H1_E_src1[18], GND, H1L854);

--H1L856 is DE2_Board:inst|cpu_0:the_cpu_0|add~1504
H1L856 = AMPP_FUNCTION(H1_E_src2[18], H1_E_src1[18], H1L854);


--H1L857 is DE2_Board:inst|cpu_0:the_cpu_0|add~1505
H1L857 = AMPP_FUNCTION(H1_E_src2[19], H1_E_src1[19], GND, H1L856);

--H1L858 is DE2_Board:inst|cpu_0:the_cpu_0|add~1506
H1L858 = AMPP_FUNCTION(H1_E_src2[19], H1_E_src1[19], H1L856);


--H1L859 is DE2_Board:inst|cpu_0:the_cpu_0|add~1507
H1L859 = AMPP_FUNCTION(H1_E_src2[20], H1_E_src1[20], GND, H1L858);

--H1L860 is DE2_Board:inst|cpu_0:the_cpu_0|add~1508
H1L860 = AMPP_FUNCTION(H1_E_src2[20], H1_E_src1[20], H1L858);


--H1L861 is DE2_Board:inst|cpu_0:the_cpu_0|add~1509
H1L861 = AMPP_FUNCTION(H1_E_src2[21], H1_E_src1[21], GND, H1L860);

--H1L862 is DE2_Board:inst|cpu_0:the_cpu_0|add~1510
H1L862 = AMPP_FUNCTION(H1_E_src2[21], H1_E_src1[21], H1L860);


--H1L863 is DE2_Board:inst|cpu_0:the_cpu_0|add~1511
H1L863 = AMPP_FUNCTION(H1_E_src2[22], H1_E_src1[22], GND, H1L862);

--H1L864 is DE2_Board:inst|cpu_0:the_cpu_0|add~1512
H1L864 = AMPP_FUNCTION(H1_E_src2[22], H1_E_src1[22], H1L862);


--H1L865 is DE2_Board:inst|cpu_0:the_cpu_0|add~1513
H1L865 = AMPP_FUNCTION(H1_E_src2[0], H1_E_src1[0], GND);

--H1L866 is DE2_Board:inst|cpu_0:the_cpu_0|add~1514
H1L866 = AMPP_FUNCTION(H1_E_src2[0], H1_E_src1[0]);


--H1L867 is DE2_Board:inst|cpu_0:the_cpu_0|add~1515
H1L867 = AMPP_FUNCTION(H1_E_src2[1], H1_E_src1[1], GND, H1L866);

--H1L868 is DE2_Board:inst|cpu_0:the_cpu_0|add~1516
H1L868 = AMPP_FUNCTION(H1_E_src2[1], H1_E_src1[1], H1L866);


--H1L869 is DE2_Board:inst|cpu_0:the_cpu_0|add~1517
H1L869 = AMPP_FUNCTION(H1_E_src2[2], H1_E_src1[2], GND, H1L868);

--H1L870 is DE2_Board:inst|cpu_0:the_cpu_0|add~1518
H1L870 = AMPP_FUNCTION(H1_E_src2[2], H1_E_src1[2], H1L868);


--H1L871 is DE2_Board:inst|cpu_0:the_cpu_0|add~1519
H1L871 = AMPP_FUNCTION(H1_E_src2[3], H1_E_src1[3], GND, H1L870);

--H1L872 is DE2_Board:inst|cpu_0:the_cpu_0|add~1520
H1L872 = AMPP_FUNCTION(H1_E_src2[3], H1_E_src1[3], H1L870);


--H1L873 is DE2_Board:inst|cpu_0:the_cpu_0|add~1521
H1L873 = AMPP_FUNCTION(H1_E_src2[4], H1_E_src1[4], GND, H1L872);

--H1L874 is DE2_Board:inst|cpu_0:the_cpu_0|add~1522
H1L874 = AMPP_FUNCTION(H1_E_src2[4], H1_E_src1[4], H1L872);


--H1L875 is DE2_Board:inst|cpu_0:the_cpu_0|add~1523
H1L875 = AMPP_FUNCTION(H1_E_src2[5], H1_E_src1[5], GND, H1L874);

--H1L876 is DE2_Board:inst|cpu_0:the_cpu_0|add~1524
H1L876 = AMPP_FUNCTION(H1_E_src2[5], H1_E_src1[5], H1L874);


--H1L877 is DE2_Board:inst|cpu_0:the_cpu_0|add~1525
H1L877 = AMPP_FUNCTION(H1_E_src2[6], H1_E_src1[6], GND, H1L876);

--H1L878 is DE2_Board:inst|cpu_0:the_cpu_0|add~1526
H1L878 = AMPP_FUNCTION(H1_E_src2[6], H1_E_src1[6], H1L876);


--H1L879 is DE2_Board:inst|cpu_0:the_cpu_0|add~1527
H1L879 = AMPP_FUNCTION(H1_E_src2[7], H1_E_src1[7], GND, H1L878);

--H1L880 is DE2_Board:inst|cpu_0:the_cpu_0|add~1528
H1L880 = AMPP_FUNCTION(H1_E_src2[7], H1_E_src1[7], H1L878);


--H1L881 is DE2_Board:inst|cpu_0:the_cpu_0|add~1529
H1L881 = AMPP_FUNCTION(H1_E_src2[8], H1_E_src1[8], GND, H1L880);

--H1L882 is DE2_Board:inst|cpu_0:the_cpu_0|add~1530
H1L882 = AMPP_FUNCTION(H1_E_src2[8], H1_E_src1[8], H1L880);


--H1L883 is DE2_Board:inst|cpu_0:the_cpu_0|add~1531
H1L883 = AMPP_FUNCTION(H1_E_src2[9], H1_E_src1[9], GND, H1L882);

--H1L884 is DE2_Board:inst|cpu_0:the_cpu_0|add~1532
H1L884 = AMPP_FUNCTION(H1_E_src2[9], H1_E_src1[9], H1L882);


--H1L885 is DE2_Board:inst|cpu_0:the_cpu_0|add~1533
H1L885 = AMPP_FUNCTION(H1_E_src2[10], H1_E_src1[10], GND, H1L884);

--H1L886 is DE2_Board:inst|cpu_0:the_cpu_0|add~1534
H1L886 = AMPP_FUNCTION(H1_E_src2[10], H1_E_src1[10], H1L884);


--H1L887 is DE2_Board:inst|cpu_0:the_cpu_0|add~1535
H1L887 = AMPP_FUNCTION(H1_E_src2[11], H1_E_src1[11], GND, H1L886);

--H1L888 is DE2_Board:inst|cpu_0:the_cpu_0|add~1536
H1L888 = AMPP_FUNCTION(H1_E_src2[11], H1_E_src1[11], H1L886);


--H1L889 is DE2_Board:inst|cpu_0:the_cpu_0|add~1537
H1L889 = AMPP_FUNCTION(H1_E_src2[12], H1_E_src1[12], GND, H1L888);

--H1L890 is DE2_Board:inst|cpu_0:the_cpu_0|add~1538
H1L890 = AMPP_FUNCTION(H1_E_src2[12], H1_E_src1[12], H1L888);


--H1L891 is DE2_Board:inst|cpu_0:the_cpu_0|add~1539
H1L891 = AMPP_FUNCTION(H1_E_src2[13], H1_E_src1[13], GND, H1L890);

--H1L892 is DE2_Board:inst|cpu_0:the_cpu_0|add~1540
H1L892 = AMPP_FUNCTION(H1_E_src2[13], H1_E_src1[13], H1L890);


--H1L893 is DE2_Board:inst|cpu_0:the_cpu_0|add~1541
H1L893 = AMPP_FUNCTION(H1_E_src2[14], H1_E_src1[14], GND, H1L892);

--H1L894 is DE2_Board:inst|cpu_0:the_cpu_0|add~1542
H1L894 = AMPP_FUNCTION(H1_E_src2[14], H1_E_src1[14], H1L892);


--H1L895 is DE2_Board:inst|cpu_0:the_cpu_0|add~1543
H1L895 = AMPP_FUNCTION(H1_E_src2[15], H1_E_src1[15], GND, H1L894);

--H1L896 is DE2_Board:inst|cpu_0:the_cpu_0|add~1544
H1L896 = AMPP_FUNCTION(H1_E_src2[15], H1_E_src1[15], H1L894);


--H1L897 is DE2_Board:inst|cpu_0:the_cpu_0|add~1545
H1L897 = AMPP_FUNCTION(H1_E_src2[16], H1_E_src1[16], GND, H1L896);

--H1L898 is DE2_Board:inst|cpu_0:the_cpu_0|add~1546
H1L898 = AMPP_FUNCTION(H1_E_src2[16], H1_E_src1[16], H1L896);


--H1L899 is DE2_Board:inst|cpu_0:the_cpu_0|add~1547
H1L899 = AMPP_FUNCTION(H1_E_src2[17], H1_E_src1[17], GND, H1L898);

--H1L900 is DE2_Board:inst|cpu_0:the_cpu_0|add~1548
H1L900 = AMPP_FUNCTION(H1_E_src2[17], H1_E_src1[17], H1L898);


--H1L901 is DE2_Board:inst|cpu_0:the_cpu_0|add~1549
H1L901 = AMPP_FUNCTION(H1_E_src2[18], H1_E_src1[18], GND, H1L900);

--H1L902 is DE2_Board:inst|cpu_0:the_cpu_0|add~1550
H1L902 = AMPP_FUNCTION(H1_E_src2[18], H1_E_src1[18], H1L900);


--H1L903 is DE2_Board:inst|cpu_0:the_cpu_0|add~1551
H1L903 = AMPP_FUNCTION(H1_E_src2[19], H1_E_src1[19], GND, H1L902);

--H1L904 is DE2_Board:inst|cpu_0:the_cpu_0|add~1552
H1L904 = AMPP_FUNCTION(H1_E_src2[19], H1_E_src1[19], H1L902);


--H1L905 is DE2_Board:inst|cpu_0:the_cpu_0|add~1553
H1L905 = AMPP_FUNCTION(H1_E_src2[20], H1_E_src1[20], GND, H1L904);

--H1L906 is DE2_Board:inst|cpu_0:the_cpu_0|add~1554
H1L906 = AMPP_FUNCTION(H1_E_src2[20], H1_E_src1[20], H1L904);


--H1L907 is DE2_Board:inst|cpu_0:the_cpu_0|add~1555
H1L907 = AMPP_FUNCTION(H1_E_src2[21], H1_E_src1[21], GND, H1L906);

--H1L908 is DE2_Board:inst|cpu_0:the_cpu_0|add~1556
H1L908 = AMPP_FUNCTION(H1_E_src2[21], H1_E_src1[21], H1L906);


--H1L909 is DE2_Board:inst|cpu_0:the_cpu_0|add~1557
H1L909 = AMPP_FUNCTION(H1_E_src2[22], H1_E_src1[22], GND, H1L908);

--H1L910 is DE2_Board:inst|cpu_0:the_cpu_0|add~1558
H1L910 = AMPP_FUNCTION(H1_E_src2[22], H1_E_src1[22], H1L908);


--H1_E_alu_sub is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_sub
H1_E_alu_sub = AMPP_FUNCTION(CLOCK_50, H1L129, E1_data_out);


--H1L132 is DE2_Board:inst|cpu_0:the_cpu_0|E_arith_result[22]~164
H1L132 = AMPP_FUNCTION(H1L863, H1L909, H1_E_alu_sub);


--H1_W_cmp_result is DE2_Board:inst|cpu_0:the_cpu_0|W_cmp_result
H1_W_cmp_result = AMPP_FUNCTION(CLOCK_50, H1L138, E1_data_out);


--H1_R_ctrl_br is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_br
H1_R_ctrl_br = AMPP_FUNCTION(CLOCK_50, H1L17, E1_data_out);


--H1_R_ctrl_uncond_cti is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_uncond_cti
H1_R_ctrl_uncond_cti = AMPP_FUNCTION(CLOCK_50, H1L46, E1_data_out);


--H1L592 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc_nxt[20]~770
H1L592 = AMPP_FUNCTION(H1_W_cmp_result, H1_R_ctrl_br, H1_R_ctrl_uncond_cti);


--H1L593 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc_nxt[20]~771
H1L593 = AMPP_FUNCTION(H1L591, H1L817, H1L132, H1L592);


--H1_W_valid is DE2_Board:inst|cpu_0:the_cpu_0|W_valid
H1_W_valid = AMPP_FUNCTION(CLOCK_50, H1L773, E1_data_out);


--M1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register
M1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register = DFFEAS(M1L7, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--T1L15 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register_in~64
T1L15 = !H1_i_read & !H1_F_pc[20] & !H1_F_pc[19] & !H1_F_pc[18];


--T1L16 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register_in~65
T1L16 = !H1_F_pc[17] & !H1_F_pc[16] & !H1_F_pc[13] & !H1_F_pc[12];


--M1L8 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_requests_data_RAM_s1~276
M1L8 = !H1_F_pc[11] & !H1_F_pc[10];


--M1L9 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_requests_data_RAM_s1~277
M1L9 = T1L15 & T1L16 & M1L8 & !H1_F_pc[15];


--M1L10 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_requests_data_RAM_s1~278
M1L10 = H1_F_pc[14] & M1L9 & !H1_F_pc[9] & !H1_F_pc[8];


--T1L17 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register_in~66
T1L17 = H1_F_pc[15] & T1L15 & T1L16 & !H1_F_pc[14];


--T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register
T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register = DFFEAS(T1L18, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--T1L12 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_qualified_request_payload_buffer_s1~80
T1L12 = T1L17 & (H1_i_read # !T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register);


--T1_payload_buffer_s1_slavearbiterlockenable is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_slavearbiterlockenable
T1_payload_buffer_s1_slavearbiterlockenable = DFFEAS(T1L62, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--T1_last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1
T1_last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1 = DFFEAS(T1L22, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--A1L77 is rtl~2820
A1L77 = !H1_W_alu_result[22] & !H1_W_alu_result[21] & !H1_W_alu_result[20] & !H1_W_alu_result[19];


--P1L8 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_requests_firmware_ROM_s1~286
P1L8 = !H1_W_alu_result[18] & (H1_d_read # AB1_d_write);


--T1L10 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_requests_payload_buffer_s1~267
T1L10 = !H1_W_alu_result[14] & H1_W_alu_result[17] & !H1_W_alu_result[16];


--T1L11 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_requests_payload_buffer_s1~268
T1L11 = !H1_W_alu_result[15] & A1L77 & P1L8 & T1L10;


--T1L13 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_qualified_request_payload_buffer_s1~81
T1L13 = T1L12 & (!T1L11 # !T1_last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1 # !T1_payload_buffer_s1_slavearbiterlockenable);


--P1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register
P1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register = DFFEAS(P1L13, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--P1L12 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_in~13
P1L12 = M1L9 & !H1_F_pc[14] & (H1_i_read # !P1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register);


--K1L11 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~191
K1L11 = !T1L13 & !P1L12 & (M1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register # !M1L10);


--W1L34 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_requests_cfi_flash_0_s1~181
W1L34 = H1_F_pc[20] & !H1_i_read;


--K1L59 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_1~9
K1L59 = W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & K1_cpu_0_instruction_master_dbs_address[1] & K1_cpu_0_instruction_master_dbs_address[0] # !W1L34;


--K1L58 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|r_1~2
K1L58 = K1_cpu_0_instruction_master_dbs_address[1] & T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register;


--K1L12 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~192
K1L12 = K1L59 & !W1L29 & (K1L58 # !T1L17);


--P1L14 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_instruction_master_requests_firmware_ROM_s1~246
P1L14 = M1L9 & !H1_F_pc[14];


--M1L6 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_in~11
M1L6 = M1L10 & (H1_i_read # !M1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register);


--K1L13 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_run~193
K1L13 = K1L12 & !M1L6 & (P1_cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register # !P1L14);


--H1_i_read_nxt is DE2_Board:inst|cpu_0:the_cpu_0|i_read_nxt
H1_i_read_nxt = AMPP_FUNCTION(H1_W_valid, K1L11, K1L13, H1_i_read);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in = W1L27 & !W1L16;


--W1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter[0]
W1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] = DFFEAS(W1L124, CLOCK_50, E1_data_out,  , W1_tri_state_bridge_0_avalon_slave_arb_counter_enable,  ,  ,  ,  );


--W1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter[2]
W1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] = DFFEAS(W1L128, CLOCK_50, E1_data_out,  , W1_tri_state_bridge_0_avalon_slave_arb_counter_enable,  ,  ,  ,  );


--W1L125 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[1]~212
W1L125 = W1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] # W1_tri_state_bridge_0_avalon_slave_arb_share_counter[2];


--W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter[1]
W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] = DFFEAS(W1L126, CLOCK_50, E1_data_out,  , W1_tri_state_bridge_0_avalon_slave_arb_counter_enable,  ,  ,  ,  );


--W1L1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~782
W1L1 = W1L136 & !W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1];


--W1L127 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[2]~213
W1L127 = W1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] $ (W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] # W1_tri_state_bridge_0_avalon_slave_arb_share_counter[0]);


--W1L2 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~783
W1L2 = W1L136 & W1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] # !W1L136 & (!W1L62);


--W1L126 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[1]~214
W1L126 = W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] & (W1L136 $ !W1L2) # !W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] & !W1L2 & (W1L125 # !W1L136);


--W1L124 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[0]~215
W1L124 = !W1L2 & (W1_tri_state_bridge_0_avalon_slave_arb_share_counter[0] # W1_tri_state_bridge_0_avalon_slave_arb_share_counter[2] # !W1L1);


--W1L142 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable~152
W1L142 = W1L128 # W1L126 # W1L124;


--W1L132 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~37
W1L132 = W1L29 # W1L21;


--W1L134 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_end_xfer~28
W1L134 = W1L133 & (W1L131 # A1L62);


--W1L143 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable~153
W1L143 = W1L132 & (W1L134 & W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable # !W1L134 & (W1L142)) # !W1L132 & W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable;


--W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1]
W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(W1L137, CLOCK_50, E1_data_out,  , W1L130,  ,  ,  ,  );


--W1L57 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1~132
W1L57 = W1L136 & W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] # !W1L136 & (W1L137 # W1_tri_state_bridge_0_avalon_slave_saved_chosen_master_vector[1] & !W1L27);


--W1L58 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1~133
W1L58 = W1_d1_reasons_to_wait # W1L136 # !W1L29 & !W1L21;


--W1L59 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1~134
W1L59 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & (W1L57 # W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 & W1L58);


--H1_R_logic_op[1] is DE2_Board:inst|cpu_0:the_cpu_0|R_logic_op[1]
H1_R_logic_op[1] = AMPP_FUNCTION(CLOCK_50, H1L94, E1_data_out);


--H1_R_logic_op[0] is DE2_Board:inst|cpu_0:the_cpu_0|R_logic_op[0]
H1_R_logic_op[0] = AMPP_FUNCTION(CLOCK_50, H1L93, E1_data_out);


--H1L171 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[22]~8379
H1L171 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[22], H1_E_src1[22], H1_R_logic_op[0]);


--H1_R_ctrl_dst_data_sel_logic_result is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_logic_result
H1_R_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(CLOCK_50, H1L21, E1_data_out);


--H1L735 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[22]~111
H1L735 = AMPP_FUNCTION(H1L171, H1L132, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[22] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[22]
H1_E_shift_rot_result[22] = AMPP_FUNCTION(CLOCK_50, H1L259, H1_E_src1[22], E1_data_out, H1_E_new_inst);


--H1_R_ctrl_dst_data_sel_cmp is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_dst_data_sel_cmp
H1_R_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(CLOCK_50, H1L20, E1_data_out);


--H1_R_ctrl_rdctl_inst is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_rdctl_inst
H1_R_ctrl_rdctl_inst = AMPP_FUNCTION(CLOCK_50, A1L71, E1_data_out);


--H1L127 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result~0
H1L127 = AMPP_FUNCTION(H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1_R_ctrl_shift_rot is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_shift_rot
H1_R_ctrl_shift_rot = AMPP_FUNCTION(CLOCK_50, H1L43, E1_data_out);


--H1_E_new_inst is DE2_Board:inst|cpu_0:the_cpu_0|E_new_inst
H1_E_new_inst = AMPP_FUNCTION(CLOCK_50, H1_R_valid, E1_data_out);


--H1_R_ctrl_ld is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_ld
H1_R_ctrl_ld = AMPP_FUNCTION(CLOCK_50, H1L37, E1_data_out);


--J1_cpu_0_data_master_waitrequest is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest
J1_cpu_0_data_master_waitrequest = DFFEAS(J1L125, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_d_read_nxt is DE2_Board:inst|cpu_0:the_cpu_0|d_read_nxt
H1_d_read_nxt = AMPP_FUNCTION(H1_E_new_inst, H1_R_ctrl_ld, H1_d_read, J1_cpu_0_data_master_waitrequest);


--H1_R_ctrl_st is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_st
H1_R_ctrl_st = AMPP_FUNCTION(CLOCK_50, H1L44, E1_data_out);


--H1_d_write_nxt is DE2_Board:inst|cpu_0:the_cpu_0|d_write_nxt
H1_d_write_nxt = AMPP_FUNCTION(H1_E_new_inst, H1_R_ctrl_st, AB1_d_write, J1_cpu_0_data_master_waitrequest);


--W1L61 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1~33
W1L61 = W1L34 & (W1L129 # W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & W1L58);


--W1L25 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register_in~11
W1L25 = H1_d_read & W1L137 & !W1L16;


--T1_last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1
T1_last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1 = DFFEAS(T1L25, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--T1L54 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~98
T1L54 = T1L17 & T1_last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1;


--T1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register
T1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register = DFFEAS(T1_registered_cpu_0_data_master_read_data_valid_payload_buffer_s1, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L177 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~149
J1L177 = !T1L5 & (J1_cpu_0_data_master_dbs_address[1] & (!H1_d_byteenable[3]) # !J1_cpu_0_data_master_dbs_address[1] & !H1_d_byteenable[1]);


--T1L6 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~183
T1L6 = J1_cpu_0_data_master_no_byte_enables_and_last_term # J1_cpu_0_data_master_waitrequest # J1L177;


--T1L7 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~184
T1L7 = AB1_d_write & (T1L6 # H1_d_read & T1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register) # !AB1_d_write & H1_d_read & T1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register;


--T1L8 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~185
T1L8 = T1L11 & !T1L7 & (!T1L54 # !T1_payload_buffer_s1_slavearbiterlockenable);


--T1_payload_buffer_s1_arb_addend[1] is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_addend[1]
T1_payload_buffer_s1_arb_addend[1] = DFFEAS(T1L42, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--T1L56 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~48
T1L56 = T1L8 & (T1_payload_buffer_s1_arb_addend[1] # !T1L13);


--J1L171 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~491
J1L171 = W1_d1_reasons_to_wait & W1L86 & !W1_cfi_flash_0_s1_wait_counter[3] & !W1_cfi_flash_0_s1_wait_counter[0];


--J1L172 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~492
J1L172 = T1L11 & (J1L177 # W1_cpu_0_data_master_requests_cfi_flash_0_s1 & !W1L18) # !T1L11 & (W1_cpu_0_data_master_requests_cfi_flash_0_s1 & !W1L18);


--J1L173 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~493
J1L173 = W1L137 & (J1L171 # J1L172 & !J1_cpu_0_data_master_no_byte_enables_and_last_term) # !W1L137 & (J1L172 & !J1_cpu_0_data_master_no_byte_enables_and_last_term);


--J1L170 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~1
J1L170 = AB1_d_write & J1_cpu_0_data_master_waitrequest & T1L11;


--J1L174 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~494
J1L174 = AB1_d_write & !J1L170 & (T1L56 # J1L173);


--J1L175 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~495
J1L175 = !J1L170 & (W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # T1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register);


--J1L8 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0]~105
J1L8 = J1_cpu_0_data_master_dbs_address[0] $ (W1_cpu_0_data_master_requests_cfi_flash_0_s1 & (J1L174 # J1L175));


--H1_D_iw[4] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[4]
H1_D_iw[4] = AMPP_FUNCTION(CLOCK_50, H1L435, E1_data_out, H1_F_valid);


--H1_D_iw[3] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[3]
H1_D_iw[3] = AMPP_FUNCTION(CLOCK_50, H1L438, E1_data_out, H1_F_valid);


--H1L184 is DE2_Board:inst|cpu_0:the_cpu_0|E_mem_byte_en~469
H1L184 = AMPP_FUNCTION(H1L819, H1L865, H1_E_alu_sub);


--H1L130 is DE2_Board:inst|cpu_0:the_cpu_0|E_arith_result[1]~165
H1L130 = AMPP_FUNCTION(H1L821, H1L867, H1_E_alu_sub);


--H1L183 is DE2_Board:inst|cpu_0:the_cpu_0|E_mem_byte_en[3]~470
H1L183 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], H1L184, H1L130);


--H1L181 is DE2_Board:inst|cpu_0:the_cpu_0|E_mem_byte_en[1]~471
H1L181 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], H1L184, H1L130);


--J1L1 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|add~127
J1L1 = J1_cpu_0_data_master_dbs_address[1] $ T1L11 $ (W1_cpu_0_data_master_requests_cfi_flash_0_s1 & J1_cpu_0_data_master_dbs_address[0]);


--J1L10 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]~106
J1L10 = J1L174 & J1L1 # !J1L174 & (J1L175 & J1L1 # !J1L175 & (J1_cpu_0_data_master_dbs_address[1]));


--H1L182 is DE2_Board:inst|cpu_0:the_cpu_0|E_mem_byte_en[2]~472
H1L182 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], H1L130, H1L184);


--H1L185 is DE2_Board:inst|cpu_0:the_cpu_0|E_mem_byte_en~473
H1L185 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], H1L184, H1L130);


--J1L178 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~150
J1L178 = T1L11 & J1L177 & (!J1_cpu_0_data_master_dbs_address[0]) # !T1L11 & (!W1L18 & J1_cpu_0_data_master_dbs_address[0]);


--J1L179 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|last_dbs_term_and_run~151
J1L179 = AB1_d_write & J1_cpu_0_data_master_dbs_address[1] & J1L178;


--W1L114 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]~188
W1L114 = W1L16 & (W1L133 & W1L27 # !W1L133 & (!W1L129)) # !W1L16 & (!W1L129);


--W1L115 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]~189
W1L115 = W1L62 & !W1L114 # !W1L62 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--E1_data_in_d1 is DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_in_d1
E1_data_in_d1 = DFFEAS(VCC, CLOCK_50, !C1_inst4,  ,  ,  ,  ,  ,  );


--W1L9 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value~186
W1L9 = W1_cfi_flash_0_s1_wait_counter[3] & (W1_cfi_flash_0_s1_wait_counter[2] # W1_cfi_flash_0_s1_wait_counter[1] # W1_cfi_flash_0_s1_wait_counter[0]);


--W1L8 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[3]~187
W1L8 = W1L9 # W1L131 & W1L133;


--W1L6 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[2]~188
W1L6 = A1L62 & (!W1L133 # !W1L131);


--W1L7 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[2]~189
W1L7 = W1L6 & (W1_cfi_flash_0_s1_wait_counter[2] $ (!W1_cfi_flash_0_s1_wait_counter[1] & !W1_cfi_flash_0_s1_wait_counter[0]));


--W1L4 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[1]~190
W1L4 = W1_cfi_flash_0_s1_wait_counter[1] & W1_cfi_flash_0_s1_wait_counter[0] # !W1_cfi_flash_0_s1_wait_counter[1] & !W1_cfi_flash_0_s1_wait_counter[0] & (W1_cfi_flash_0_s1_wait_counter[3] # W1_cfi_flash_0_s1_wait_counter[2]);


--W1L5 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[1]~191
W1L5 = W1L131 & !W1_cfi_flash_0_s1_in_a_read_cycle & (W1L4 # !W1_in_a_write_cycle) # !W1L131 & W1L4;


--H1L170 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[21]~8380
H1L170 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[21], H1_E_src1[21], H1_R_logic_op[0]);


--H1L586 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[19]~90
H1L586 = AMPP_FUNCTION(H1L907, H1L861, H1_E_alu_sub);


--H1L732 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[21]~112
H1L732 = AMPP_FUNCTION(H1L170, H1L586, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[21] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[21]
H1_E_shift_rot_result[21] = AMPP_FUNCTION(CLOCK_50, H1L258, H1_E_src1[21], E1_data_out, H1_E_new_inst);


--H1L169 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[20]~8381
H1L169 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[20], H1_E_src1[20], H1_R_logic_op[0]);


--H1L583 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[18]~91
H1L583 = AMPP_FUNCTION(H1L905, H1L859, H1_E_alu_sub);


--H1L729 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[20]~113
H1L729 = AMPP_FUNCTION(H1L169, H1L583, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[20] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[20]
H1_E_shift_rot_result[20] = AMPP_FUNCTION(CLOCK_50, H1L257, H1_E_src1[20], E1_data_out, H1_E_new_inst);


--H1L168 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[19]~8382
H1L168 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[19], H1_E_src1[19], H1_R_logic_op[0]);


--H1L580 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[17]~92
H1L580 = AMPP_FUNCTION(H1L903, H1L857, H1_E_alu_sub);


--H1L726 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[19]~114
H1L726 = AMPP_FUNCTION(H1L168, H1L580, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[19] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[19]
H1_E_shift_rot_result[19] = AMPP_FUNCTION(CLOCK_50, H1L256, H1_E_src1[19], E1_data_out, H1_E_new_inst);


--H1L167 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[18]~8383
H1L167 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[18], H1_E_src1[18], H1_R_logic_op[0]);


--H1L577 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[16]~93
H1L577 = AMPP_FUNCTION(H1L901, H1L855, H1_E_alu_sub);


--H1L723 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[18]~115
H1L723 = AMPP_FUNCTION(H1L167, H1L577, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[18] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[18]
H1_E_shift_rot_result[18] = AMPP_FUNCTION(CLOCK_50, H1L255, H1_E_src1[18], E1_data_out, H1_E_new_inst);


--H1L166 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[17]~8384
H1L166 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[17], H1_E_src1[17], H1_R_logic_op[0]);


--H1L574 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[15]~94
H1L574 = AMPP_FUNCTION(H1L899, H1L853, H1_E_alu_sub);


--H1L720 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[17]~116
H1L720 = AMPP_FUNCTION(H1L166, H1L574, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[17] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[17]
H1_E_shift_rot_result[17] = AMPP_FUNCTION(CLOCK_50, H1L254, H1_E_src1[17], E1_data_out, H1_E_new_inst);


--H1L165 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[16]~8385
H1L165 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[16], H1_E_src1[16], H1_R_logic_op[0]);


--H1L571 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[14]~95
H1L571 = AMPP_FUNCTION(H1L897, H1L851, H1_E_alu_sub);


--H1L717 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[16]~117
H1L717 = AMPP_FUNCTION(H1L165, H1L571, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[16] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[16]
H1_E_shift_rot_result[16] = AMPP_FUNCTION(CLOCK_50, H1L253, H1_E_src1[16], E1_data_out, H1_E_new_inst);


--H1L164 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[15]~8386
H1L164 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[15], H1_E_src1[15], H1_R_logic_op[0]);


--H1L568 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[13]~96
H1L568 = AMPP_FUNCTION(H1L895, H1L849, H1_E_alu_sub);


--H1L714 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[15]~118
H1L714 = AMPP_FUNCTION(H1L164, H1L568, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[15] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[15]
H1_E_shift_rot_result[15] = AMPP_FUNCTION(CLOCK_50, H1L252, H1_E_src1[15], E1_data_out, H1_E_new_inst);


--H1L163 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[14]~8387
H1L163 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[14], H1_E_src1[14], H1_R_logic_op[0]);


--H1L565 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[12]~97
H1L565 = AMPP_FUNCTION(H1L893, H1L847, H1_E_alu_sub);


--H1L711 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[14]~119
H1L711 = AMPP_FUNCTION(H1L163, H1L565, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[14] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[14]
H1_E_shift_rot_result[14] = AMPP_FUNCTION(CLOCK_50, H1L251, H1_E_src1[14], E1_data_out, H1_E_new_inst);


--H1L162 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[13]~8388
H1L162 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[13], H1_E_src1[13], H1_R_logic_op[0]);


--H1L562 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[11]~98
H1L562 = AMPP_FUNCTION(H1L891, H1L845, H1_E_alu_sub);


--H1L708 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[13]~120
H1L708 = AMPP_FUNCTION(H1L162, H1L562, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[13] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[13]
H1_E_shift_rot_result[13] = AMPP_FUNCTION(CLOCK_50, H1L250, H1_E_src1[13], E1_data_out, H1_E_new_inst);


--H1L161 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[12]~8389
H1L161 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[12], H1_E_src1[12], H1_R_logic_op[0]);


--H1L559 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[10]~99
H1L559 = AMPP_FUNCTION(H1L889, H1L843, H1_E_alu_sub);


--H1L705 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[12]~121
H1L705 = AMPP_FUNCTION(H1L161, H1L559, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[12] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[12]
H1_E_shift_rot_result[12] = AMPP_FUNCTION(CLOCK_50, H1L249, H1_E_src1[12], E1_data_out, H1_E_new_inst);


--H1L160 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[11]~8390
H1L160 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[11], H1_E_src1[11], H1_R_logic_op[0]);


--H1L556 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[9]~100
H1L556 = AMPP_FUNCTION(H1L887, H1L841, H1_E_alu_sub);


--H1L702 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[11]~122
H1L702 = AMPP_FUNCTION(H1L160, H1L556, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[11] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[11]
H1_E_shift_rot_result[11] = AMPP_FUNCTION(CLOCK_50, H1L248, H1_E_src1[11], E1_data_out, H1_E_new_inst);


--H1L159 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[10]~8391
H1L159 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[10], H1_E_src1[10], H1_R_logic_op[0]);


--H1L553 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[8]~101
H1L553 = AMPP_FUNCTION(H1L885, H1L839, H1_E_alu_sub);


--H1L699 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[10]~123
H1L699 = AMPP_FUNCTION(H1L159, H1L553, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[10] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[10]
H1_E_shift_rot_result[10] = AMPP_FUNCTION(CLOCK_50, H1L247, H1_E_src1[10], E1_data_out, H1_E_new_inst);


--H1L158 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[9]~8392
H1L158 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[9], H1_E_src1[9], H1_R_logic_op[0]);


--H1L550 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[7]~102
H1L550 = AMPP_FUNCTION(H1L883, H1L837, H1_E_alu_sub);


--H1L696 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[9]~124
H1L696 = AMPP_FUNCTION(H1L158, H1L550, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[9] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[9]
H1_E_shift_rot_result[9] = AMPP_FUNCTION(CLOCK_50, H1L246, H1_E_src1[9], E1_data_out, H1_E_new_inst);


--H1L157 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[8]~8393
H1L157 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[8], H1_E_src1[8], H1_R_logic_op[0]);


--H1L547 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[6]~103
H1L547 = AMPP_FUNCTION(H1L881, H1L835, H1_E_alu_sub);


--H1L693 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[8]~125
H1L693 = AMPP_FUNCTION(H1L157, H1L547, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[8] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[8]
H1_E_shift_rot_result[8] = AMPP_FUNCTION(CLOCK_50, H1L245, H1_E_src1[8], E1_data_out, H1_E_new_inst);


--H1L156 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[7]~8394
H1L156 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[7], H1_E_src1[7], H1_R_logic_op[0]);


--H1L544 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[5]~104
H1L544 = AMPP_FUNCTION(H1L879, H1L833, H1_E_alu_sub);


--H1L690 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[7]~126
H1L690 = AMPP_FUNCTION(H1L156, H1L544, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[7] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[7]
H1_E_shift_rot_result[7] = AMPP_FUNCTION(CLOCK_50, H1L244, H1_E_src1[7], E1_data_out, H1_E_new_inst);


--H1L155 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[6]~8395
H1L155 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[6], H1_E_src1[6], H1_R_logic_op[0]);


--H1L541 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[4]~105
H1L541 = AMPP_FUNCTION(H1L877, H1L831, H1_E_alu_sub);


--H1L687 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[6]~127
H1L687 = AMPP_FUNCTION(H1L155, H1L541, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[6] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[6]
H1_E_shift_rot_result[6] = AMPP_FUNCTION(CLOCK_50, H1L243, H1_E_src1[6], E1_data_out, H1_E_new_inst);


--H1L154 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[5]~8396
H1L154 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[5], H1_E_src1[5], H1_R_logic_op[0]);


--H1L131 is DE2_Board:inst|cpu_0:the_cpu_0|E_arith_result[5]~166
H1L131 = AMPP_FUNCTION(H1L829, H1L875, H1_E_alu_sub);


--H1L684 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[5]~128
H1L684 = AMPP_FUNCTION(H1L154, H1L131, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[5] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[5]
H1_E_shift_rot_result[5] = AMPP_FUNCTION(CLOCK_50, H1L242, H1_E_src1[5], E1_data_out, H1_E_new_inst);


--H1L589 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc_nxt[3]~772
H1L589 = AMPP_FUNCTION(H1L783, H1L131, H1L592);


--H1L590 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc_nxt[3]~773
H1L590 = AMPP_FUNCTION(H1_R_ctrl_exception, H1L589, H1_R_ctrl_break);


--H1L153 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[4]~8397
H1L153 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[4], H1_E_src1[4], H1_R_logic_op[0]);


--H1L537 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[2]~106
H1L537 = AMPP_FUNCTION(H1L873, H1L827, H1_E_alu_sub);


--H1L681 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[4]~129
H1L681 = AMPP_FUNCTION(H1L153, H1L537, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[4] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[4]
H1_E_shift_rot_result[4] = AMPP_FUNCTION(CLOCK_50, H1L241, H1_E_src1[4], E1_data_out, H1_E_new_inst);


--H1L152 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[3]~8398
H1L152 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[3], H1_E_src1[3], H1_R_logic_op[0]);


--H1L534 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[1]~107
H1L534 = AMPP_FUNCTION(H1L871, H1L825, H1_E_alu_sub);


--H1L678 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[3]~130
H1L678 = AMPP_FUNCTION(H1L152, H1L534, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[3] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[3]
H1_E_shift_rot_result[3] = AMPP_FUNCTION(CLOCK_50, H1L240, H1_E_src1[3], E1_data_out, H1_E_new_inst);


--H1L151 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[2]~8399
H1L151 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[2], H1_E_src1[2], H1_R_logic_op[0]);


--H1L531 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[0]~108
H1L531 = AMPP_FUNCTION(H1L869, H1L823, H1_E_alu_sub);


--H1L675 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[2]~131
H1L675 = AMPP_FUNCTION(H1L151, H1L531, H1_R_ctrl_dst_data_sel_logic_result);


--H1_E_shift_rot_result[2] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[2]
H1_E_shift_rot_result[2] = AMPP_FUNCTION(CLOCK_50, H1L239, H1_E_src1[2], E1_data_out, H1_E_new_inst);


--K1L1 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|add~97
K1L1 = K1_cpu_0_instruction_master_dbs_address[1] $ T1L17 $ (W1L34 & K1_cpu_0_instruction_master_dbs_address[0]);


--K1L10 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[1]~124
K1L10 = W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & K1L1 # !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & (T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register & K1L1 # !T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register & (K1_cpu_0_instruction_master_dbs_address[1]));


--K1L8 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_dbs_address[0]~125
K1L8 = K1_cpu_0_instruction_master_dbs_address[0] $ (W1L34 & (W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register));


--ZB3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]
ZB3_Q[0] = AMPP_FUNCTION(A1L5, D1L20, D1_CLRN_SIGNAL, D1_IRSR_ENA);


--ZB6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
ZB6_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, D1_CLRN_SIGNAL, D1L16);


--FB1_td_shift[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0]
FB1_td_shift[0] = AMPP_FUNCTION(A1L5, FB1L50, D1_CLRN_SIGNAL, FB1L44);


--D1L10 is sld_hub:sld_hub_inst|hub_tdo~453
D1L10 = AMPP_FUNCTION(ZB6_Q[0], FB1_td_shift[0]);


--ZB7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
ZB7_Q[0] = AMPP_FUNCTION(A1L5, ZB7L3, D1L16);


--AC1_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]
AC1_WORD_SR[0] = AMPP_FUNCTION(A1L5, AC1L26, AC1L24);


--D1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG
D1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L5, D1L8);


--EC1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[0]
EC1_dffe1a[0] = AMPP_FUNCTION(A1L5, EC1_w_anode1w[3], D1_CLRN_SIGNAL, D1L6);


--D1L11 is sld_hub:sld_hub_inst|hub_tdo~454
D1L11 = AMPP_FUNCTION(ZB7_Q[0], AC1_WORD_SR[0], D1_HUB_BYPASS_REG, EC1_dffe1a[0]);


--D1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
D1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, A1L61, DC1_state[0], DC1_state[12]);


--D1L12 is sld_hub:sld_hub_inst|hub_tdo~455
D1L12 = AMPP_FUNCTION(ZB3_Q[0], D1L10, D1L11, D1_jtag_debug_mode_usr1);


--DC1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
DC1_state[3] = AMPP_FUNCTION(A1L5, DC1L19);


--DC1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
DC1_state[4] = AMPP_FUNCTION(A1L5, DC1L20, A1L7);


--D1L13 is sld_hub:sld_hub_inst|hub_tdo~456
D1L13 = AMPP_FUNCTION(D1L12, DC1_state[3], DC1_state[4], D1_hub_tdo);


--DC1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]
DC1_state[8] = AMPP_FUNCTION(A1L5, DC1L24, !A1L7);


--W1_d1_outgoing_tri_state_bridge_0_data[7] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[7]
W1_d1_outgoing_tri_state_bridge_0_data[7] = DFFEAS(J1L26, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_in_a_write_cycle is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle
W1_d1_in_a_write_cycle = DFFEAS(W1_in_a_write_cycle, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[6] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[6]
W1_d1_outgoing_tri_state_bridge_0_data[6] = DFFEAS(J1L24, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[5] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[5]
W1_d1_outgoing_tri_state_bridge_0_data[5] = DFFEAS(J1L22, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[4] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[4]
W1_d1_outgoing_tri_state_bridge_0_data[4] = DFFEAS(J1L20, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[3] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[3]
W1_d1_outgoing_tri_state_bridge_0_data[3] = DFFEAS(J1L18, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[2]
W1_d1_outgoing_tri_state_bridge_0_data[2] = DFFEAS(J1L16, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[1]
W1_d1_outgoing_tri_state_bridge_0_data[1] = DFFEAS(J1L14, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_outgoing_tri_state_bridge_0_data[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[0]
W1_d1_outgoing_tri_state_bridge_0_data[0] = DFFEAS(J1L12, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L130 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_winner~0
W1L130 = W1L62 & !W1L136;


--W1L3 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[0]~192
W1L3 = !W1_cfi_flash_0_s1_wait_counter[0] & A1L62 & (!W1L133 # !W1L131);


--H1_D_iw[0] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[0]
H1_D_iw[0] = AMPP_FUNCTION(CLOCK_50, H1L440, E1_data_out, H1_F_valid);


--H1_D_iw[1] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[1]
H1_D_iw[1] = AMPP_FUNCTION(CLOCK_50, H1L443, E1_data_out, H1_F_valid);


--H1_D_iw[2] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[2]
H1_D_iw[2] = AMPP_FUNCTION(CLOCK_50, H1L445, E1_data_out, H1_F_valid);


--H1_D_iw[5] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[5]
H1_D_iw[5] = AMPP_FUNCTION(CLOCK_50, H1L448, E1_data_out, H1_F_valid);


--A1L64 is rtl~15
A1L64 = !H1_D_iw[0] & H1_D_iw[1] & !H1_D_iw[2] & H1_D_iw[5];


--H1_D_iw[12] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[12]
H1_D_iw[12] = AMPP_FUNCTION(CLOCK_50, H1L450, E1_data_out, H1_F_valid);


--H1L45 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_uncond_cti~134
H1L45 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], A1L64, H1_D_iw[12]);


--H1_D_iw[16] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[16]
H1_D_iw[16] = AMPP_FUNCTION(CLOCK_50, H1L453, E1_data_out, H1_F_valid);


--H1_D_iw[15] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[15]
H1_D_iw[15] = AMPP_FUNCTION(CLOCK_50, H1L456, E1_data_out, H1_F_valid);


--H1_D_iw[14] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[14]
H1_D_iw[14] = AMPP_FUNCTION(CLOCK_50, H1L459, E1_data_out, H1_F_valid);


--H1_D_iw[13] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[13]
H1_D_iw[13] = AMPP_FUNCTION(CLOCK_50, H1L462, E1_data_out, H1_F_valid);


--H1L23 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_exception~36
H1L23 = AMPP_FUNCTION(H1_D_iw[16], H1_D_iw[15], H1_D_iw[14], H1_D_iw[13]);


--H1_D_iw[11] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[11]
H1_D_iw[11] = AMPP_FUNCTION(CLOCK_50, H1L465, E1_data_out, H1_F_valid);


--A1L78 is rtl~2821
A1L78 = H1_D_iw[4] & H1_D_iw[3] & A1L64;


--A1L79 is rtl~2822
A1L79 = H1_D_iw[12] & H1_D_iw[13] & H1_D_iw[11] & A1L78;


--H1L34 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_jmp_direct~69
H1L34 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3]);


--A1L65 is rtl~25
A1L65 = !H1_D_iw[0] & !H1_D_iw[1] & H1_D_iw[2] & H1_D_iw[5];


--H1_D_ctrl_exception is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_exception
H1_D_ctrl_exception = AMPP_FUNCTION(H1L45, H1L23, H1L33);


--H1L15 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_break~25
H1L15 = AMPP_FUNCTION(H1_D_iw[13], A1L78, H1_D_iw[12]);


--H1L16 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_break~26
H1L16 = AMPP_FUNCTION(H1_D_iw[16], H1_D_iw[15], H1L15, H1_D_iw[14]);


--CB1_q_a[22] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[22]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[22] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[22], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[22] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[22]
CB1_q_b[22] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[22], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1_D_iw[21] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[21]
H1_D_iw[21] = AMPP_FUNCTION(CLOCK_50, H1L468, E1_data_out, H1_F_valid);


--H1_R_src2_use_imm is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_use_imm
H1_R_src2_use_imm = AMPP_FUNCTION(CLOCK_50, H1L662, E1_data_out);


--H1L380 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[22]~68
H1L380 = AMPP_FUNCTION(CB1_q_b[22], H1_D_iw[21], H1_R_src2_use_imm);


--H1_R_ctrl_unsigned_lo_imm is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_unsigned_lo_imm
H1_R_ctrl_unsigned_lo_imm = AMPP_FUNCTION(CLOCK_50, H1L48, E1_data_out);


--H1_R_ctrl_force_src2_zero is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_force_src2_zero
H1_R_ctrl_force_src2_zero = AMPP_FUNCTION(CLOCK_50, H1L28, E1_data_out);


--H1L643 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_hi~0
H1L643 = AMPP_FUNCTION(H1_R_ctrl_unsigned_lo_imm, H1_R_ctrl_force_src2_zero);


--H1_R_ctrl_hi_imm is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_hi_imm
H1_R_ctrl_hi_imm = AMPP_FUNCTION(CLOCK_50, H1L31, E1_data_out);


--H1_D_iw[26] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[26]
H1_D_iw[26] = AMPP_FUNCTION(CLOCK_50, H1L470, E1_data_out, H1_F_valid);


--H1_E_valid is DE2_Board:inst|cpu_0:the_cpu_0|E_valid
H1_E_valid = AMPP_FUNCTION(CLOCK_50, H1L429, E1_data_out);


--H1_R_ctrl_jmp_direct is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_jmp_direct
H1_R_ctrl_jmp_direct = AMPP_FUNCTION(CLOCK_50, H1L35, E1_data_out);


--H1L640 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1~3
H1L640 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct);


--H1L333 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[22]~71
H1L333 = AMPP_FUNCTION(H1_D_iw[26], CB1_q_a[22], H1L640);


--H1_R_valid is DE2_Board:inst|cpu_0:the_cpu_0|R_valid
H1_R_valid = AMPP_FUNCTION(CLOCK_50, H1_D_valid, E1_data_out);


--H1_R_ctrl_retaddr is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_retaddr
H1_R_ctrl_retaddr = AMPP_FUNCTION(CLOCK_50, H1L38, E1_data_out);


--H1L639 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1~2
H1L639 = AMPP_FUNCTION(H1_R_ctrl_br, H1_R_valid, H1_R_ctrl_retaddr, H1_E_valid);


--CB1_q_a[21] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[21]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[21] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[21], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[21] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[21]
CB1_q_b[21] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[21], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L377 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[21]~69
H1L377 = AMPP_FUNCTION(CB1_q_b[21], H1_D_iw[21], H1_R_src2_use_imm);


--H1_D_iw[25] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[25]
H1_D_iw[25] = AMPP_FUNCTION(CLOCK_50, H1L472, E1_data_out, H1_F_valid);


--H1L330 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[21]~72
H1L330 = AMPP_FUNCTION(H1_D_iw[25], CB1_q_a[21], H1L640);


--CB1_q_a[20] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[20]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[20] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[20], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[20] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[20]
CB1_q_b[20] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[20], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L374 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[20]~70
H1L374 = AMPP_FUNCTION(CB1_q_b[20], H1_D_iw[21], H1_R_src2_use_imm);


--H1_D_iw[10] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[10]
H1_D_iw[10] = AMPP_FUNCTION(CLOCK_50, H1L474, E1_data_out, H1_F_valid);


--H1_D_iw[24] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[24]
H1_D_iw[24] = AMPP_FUNCTION(CLOCK_50, H1L476, E1_data_out, H1_F_valid);


--H1L327 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[20]~73
H1L327 = AMPP_FUNCTION(H1_D_iw[24], CB1_q_a[20], H1L640);


--CB1_q_a[19] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[19]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[19] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[19], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[19] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[19]
CB1_q_b[19] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[19], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L371 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[19]~71
H1L371 = AMPP_FUNCTION(CB1_q_b[19], H1_D_iw[21], H1_R_src2_use_imm);


--H1_D_iw[9] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[9]
H1_D_iw[9] = AMPP_FUNCTION(CLOCK_50, H1L478, E1_data_out, H1_F_valid);


--H1_D_iw[23] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[23]
H1_D_iw[23] = AMPP_FUNCTION(CLOCK_50, H1L480, E1_data_out, H1_F_valid);


--H1L324 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[19]~74
H1L324 = AMPP_FUNCTION(H1_D_iw[23], CB1_q_a[19], H1L640);


--CB1_q_a[18] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[18]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[18] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[18], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[18] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[18]
CB1_q_b[18] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[18], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L368 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[18]~72
H1L368 = AMPP_FUNCTION(CB1_q_b[18], H1_D_iw[21], H1_R_src2_use_imm);


--H1_D_iw[8] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[8]
H1_D_iw[8] = AMPP_FUNCTION(CLOCK_50, H1L482, E1_data_out, H1_F_valid);


--H1_D_iw[22] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[22]
H1_D_iw[22] = AMPP_FUNCTION(CLOCK_50, H1L484, E1_data_out, H1_F_valid);


--H1L321 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[18]~75
H1L321 = AMPP_FUNCTION(H1_D_iw[22], CB1_q_a[18], H1L640);


--CB1_q_a[17] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[17]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[17] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[17], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[17] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[17]
CB1_q_b[17] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[17], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L365 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[17]~73
H1L365 = AMPP_FUNCTION(CB1_q_b[17], H1_D_iw[21], H1_R_src2_use_imm);


--H1_D_iw[7] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[7]
H1_D_iw[7] = AMPP_FUNCTION(CLOCK_50, H1L486, E1_data_out, H1_F_valid);


--H1L318 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[17]~76
H1L318 = AMPP_FUNCTION(H1_D_iw[21], CB1_q_a[17], H1L640);


--CB1_q_a[16] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[16]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[16] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[16], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[16] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[16]
CB1_q_b[16] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[16], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L362 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[16]~74
H1L362 = AMPP_FUNCTION(CB1_q_b[16], H1_D_iw[21], H1_R_src2_use_imm);


--H1_D_iw[6] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[6]
H1_D_iw[6] = AMPP_FUNCTION(CLOCK_50, H1L488, E1_data_out, H1_F_valid);


--H1_D_iw[20] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[20]
H1_D_iw[20] = AMPP_FUNCTION(CLOCK_50, H1L491, E1_data_out, H1_F_valid);


--H1L315 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[16]~77
H1L315 = AMPP_FUNCTION(H1_D_iw[20], CB1_q_a[16], H1L640);


--CB1_q_a[15] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[15]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[15] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[15], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[15] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[15]
CB1_q_b[15] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[15], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L660 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo~0
H1L660 = AMPP_FUNCTION(H1_R_ctrl_force_src2_zero, H1_R_ctrl_hi_imm);


--H1L659 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[15]~1137
H1L659 = AMPP_FUNCTION(H1_D_iw[21], CB1_q_b[15], H1_R_src2_use_imm, H1L660);


--H1_D_iw[19] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[19]
H1_D_iw[19] = AMPP_FUNCTION(CLOCK_50, H1L494, E1_data_out, H1_F_valid);


--H1L312 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[15]~78
H1L312 = AMPP_FUNCTION(H1_D_iw[19], CB1_q_a[15], H1L640);


--CB1_q_a[14] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[14] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[14], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[14] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[14]
CB1_q_b[14] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[14], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L658 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[14]~1138
H1L658 = AMPP_FUNCTION(H1_D_iw[20], CB1_q_b[14], H1_R_src2_use_imm, H1L660);


--H1_D_iw[18] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[18]
H1_D_iw[18] = AMPP_FUNCTION(CLOCK_50, H1L496, E1_data_out, H1_F_valid);


--H1L309 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[14]~79
H1L309 = AMPP_FUNCTION(H1_D_iw[18], CB1_q_a[14], H1L640);


--CB1_q_a[13] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[13] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[13], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[13] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[13]
CB1_q_b[13] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[13], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L657 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[13]~1139
H1L657 = AMPP_FUNCTION(H1_D_iw[19], CB1_q_b[13], H1_R_src2_use_imm, H1L660);


--H1_D_iw[17] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[17]
H1_D_iw[17] = AMPP_FUNCTION(CLOCK_50, H1L499, E1_data_out, H1_F_valid);


--H1L306 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[13]~80
H1L306 = AMPP_FUNCTION(H1_D_iw[17], CB1_q_a[13], H1L640);


--CB1_q_a[12] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[12] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[12], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[12] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[12]
CB1_q_b[12] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[12], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L656 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[12]~1140
H1L656 = AMPP_FUNCTION(H1_D_iw[18], CB1_q_b[12], H1_R_src2_use_imm, H1L660);


--H1L303 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[12]~81
H1L303 = AMPP_FUNCTION(H1_D_iw[16], CB1_q_a[12], H1L640);


--CB1_q_a[11] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[11] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[11], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[11] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[11]
CB1_q_b[11] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[11], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L655 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[11]~1141
H1L655 = AMPP_FUNCTION(H1_D_iw[17], CB1_q_b[11], H1_R_src2_use_imm, H1L660);


--H1L300 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[11]~82
H1L300 = AMPP_FUNCTION(H1_D_iw[15], CB1_q_a[11], H1L640);


--CB1_q_a[10] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[10] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[10], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[10] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[10]
CB1_q_b[10] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[10], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L654 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[10]~1142
H1L654 = AMPP_FUNCTION(H1_D_iw[16], CB1_q_b[10], H1_R_src2_use_imm, H1L660);


--H1L297 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[10]~83
H1L297 = AMPP_FUNCTION(H1_D_iw[14], CB1_q_a[10], H1L640);


--CB1_q_a[9] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[9]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[9] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[9], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[9] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[9]
CB1_q_b[9] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[9], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L653 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[9]~1143
H1L653 = AMPP_FUNCTION(H1_D_iw[15], CB1_q_b[9], H1_R_src2_use_imm, H1L660);


--H1L294 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[9]~84
H1L294 = AMPP_FUNCTION(H1_D_iw[13], CB1_q_a[9], H1L640);


--CB1_q_a[8] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[8] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[8], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[8] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[8]
CB1_q_b[8] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[8], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte1_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L652 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[8]~1144
H1L652 = AMPP_FUNCTION(H1_D_iw[14], CB1_q_b[8], H1_R_src2_use_imm, H1L660);


--H1L291 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[8]~85
H1L291 = AMPP_FUNCTION(H1_D_iw[12], CB1_q_a[8], H1L640);


--CB1_q_a[7] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[7] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[7], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[7] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[7]
CB1_q_b[7] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[7], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L651 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[7]~1145
H1L651 = AMPP_FUNCTION(H1_D_iw[13], CB1_q_b[7], H1_R_src2_use_imm, H1L660);


--H1L288 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[7]~86
H1L288 = AMPP_FUNCTION(H1_D_iw[11], CB1_q_a[7], H1L640);


--CB1_q_a[6] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[6] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[6], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[6] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[6]
CB1_q_b[6] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[6], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L650 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[6]~1146
H1L650 = AMPP_FUNCTION(H1_D_iw[12], CB1_q_b[6], H1_R_src2_use_imm, H1L660);


--H1L285 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[6]~87
H1L285 = AMPP_FUNCTION(H1_D_iw[10], CB1_q_a[6], H1L640);


--CB1_q_a[5] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[5] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[5], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[5] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[5]
CB1_q_b[5] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[5], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L649 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[5]~1147
H1L649 = AMPP_FUNCTION(H1_D_iw[11], CB1_q_b[5], H1_R_src2_use_imm, H1L660);


--H1L282 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[5]~88
H1L282 = AMPP_FUNCTION(H1_D_iw[9], CB1_q_a[5], H1L640);


--CB1_q_a[4] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[4] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[4], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[4] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[4]
CB1_q_b[4] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[4], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L648 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[4]~1148
H1L648 = AMPP_FUNCTION(H1_D_iw[10], CB1_q_b[4], H1_R_src2_use_imm, H1L660);


--H1L279 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[4]~89
H1L279 = AMPP_FUNCTION(H1_D_iw[8], CB1_q_a[4], H1L640);


--CB1_q_a[3] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[3] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[3], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[3] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[3]
CB1_q_b[3] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[3], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L647 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[3]~1149
H1L647 = AMPP_FUNCTION(H1_D_iw[9], CB1_q_b[3], H1_R_src2_use_imm, H1L660);


--H1L276 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[3]~90
H1L276 = AMPP_FUNCTION(H1_D_iw[7], CB1_q_a[3], H1L640);


--CB1_q_a[2] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[2] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[2], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[2] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[2]
CB1_q_b[2] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[2], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L646 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[2]~1150
H1L646 = AMPP_FUNCTION(H1_D_iw[8], CB1_q_b[2], H1_R_src2_use_imm, H1L660);


--H1L273 is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[2]~91
H1L273 = AMPP_FUNCTION(H1_D_iw[6], CB1_q_a[2], H1L640);


--CB1_q_a[1] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[1] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1L776, H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[1] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[1]
CB1_q_b[1] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1L776, H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L645 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[1]~1151
H1L645 = AMPP_FUNCTION(H1_D_iw[7], CB1_q_b[1], H1_R_src2_use_imm, H1L660);


--CB1_q_a[0] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[0] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1L775, H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[0] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[0]
CB1_q_b[0] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1L775, H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte0_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L644 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_lo[0]~1152
H1L644 = AMPP_FUNCTION(H1_D_iw[6], CB1_q_b[0], H1_R_src2_use_imm, H1L660);


--H1L5 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~404
H1L5 = AMPP_FUNCTION(H1_D_iw[14], H1_D_iw[15], H1_D_iw[11], H1_D_iw[16]);


--H1L6 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~405
H1L6 = AMPP_FUNCTION(H1L45, H1L5, H1_D_iw[13]);


--A1L66 is rtl~27
A1L66 = !H1_D_iw[0] & H1_D_iw[1] & H1_D_iw[2] & !H1_D_iw[5];


--A1L68 is rtl~41
A1L68 = !H1_D_iw[0] & !H1_D_iw[1] & !H1_D_iw[2] & H1_D_iw[5];


--A1L67 is rtl~30
A1L67 = !H1_D_iw[0] & !H1_D_iw[1] & !H1_D_iw[2] & !H1_D_iw[5];


--H1L7 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~406
H1L7 = AMPP_FUNCTION(H1L10, H1L9, H1_D_iw[3], H1_D_iw[4]);


--A1L80 is rtl~2823
A1L80 = A1L78 & !H1_D_iw[12] & !H1_D_iw[13] & !H1_D_iw[16];


--H1L8 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~407
H1L8 = AMPP_FUNCTION(H1_D_iw[11], H1_D_iw[14], H1_D_iw[15], A1L80);


--H1L129 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_sub~0
H1L129 = AMPP_FUNCTION(H1_R_valid, H1L6, H1L7, H1L8);


--H1_R_compare_op[1] is DE2_Board:inst|cpu_0:the_cpu_0|R_compare_op[1]
H1_R_compare_op[1] = AMPP_FUNCTION(CLOCK_50, H1L96, E1_data_out);


--H1_E_src2[31] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[31]
H1_E_src2[31] = AMPP_FUNCTION(CLOCK_50, H1L642, E1_data_out);


--H1_E_invert_arith_src_msb is DE2_Board:inst|cpu_0:the_cpu_0|E_invert_arith_src_msb
H1_E_invert_arith_src_msb = AMPP_FUNCTION(CLOCK_50, H1L147, E1_data_out);


--H1_E_arith_src2[31] is DE2_Board:inst|cpu_0:the_cpu_0|E_arith_src2[31]
H1_E_arith_src2[31] = AMPP_FUNCTION(H1_E_src2[31], H1_E_invert_arith_src_msb);


--H1_E_src1[31] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[31]
H1_E_src1[31] = AMPP_FUNCTION(CLOCK_50, H1L638, E1_data_out);


--H1_E_arith_src1[31] is DE2_Board:inst|cpu_0:the_cpu_0|E_arith_src1[31]
H1_E_arith_src1[31] = AMPP_FUNCTION(H1_E_src1[31], H1_E_invert_arith_src_msb);


--H1_E_src2[30] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[30]
H1_E_src2[30] = AMPP_FUNCTION(CLOCK_50, H1L404, H1_D_iw[20], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[30] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[30]
H1_E_src1[30] = AMPP_FUNCTION(CLOCK_50, H1L637, E1_data_out);


--H1_E_src2[29] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[29]
H1_E_src2[29] = AMPP_FUNCTION(CLOCK_50, H1L401, H1_D_iw[19], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[29] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[29]
H1_E_src1[29] = AMPP_FUNCTION(CLOCK_50, H1L636, E1_data_out);


--H1_E_src2[28] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[28]
H1_E_src2[28] = AMPP_FUNCTION(CLOCK_50, H1L398, H1_D_iw[18], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[28] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[28]
H1_E_src1[28] = AMPP_FUNCTION(CLOCK_50, H1L635, E1_data_out);


--H1_E_src2[27] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[27]
H1_E_src2[27] = AMPP_FUNCTION(CLOCK_50, H1L395, H1_D_iw[17], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[27] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[27]
H1_E_src1[27] = AMPP_FUNCTION(CLOCK_50, H1L634, E1_data_out);


--H1_E_src2[26] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[26]
H1_E_src2[26] = AMPP_FUNCTION(CLOCK_50, H1L392, H1_D_iw[16], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[26] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[26]
H1_E_src1[26] = AMPP_FUNCTION(CLOCK_50, H1L633, E1_data_out);


--H1_E_src2[25] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[25]
H1_E_src2[25] = AMPP_FUNCTION(CLOCK_50, H1L389, H1_D_iw[15], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[25] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[25]
H1_E_src1[25] = AMPP_FUNCTION(CLOCK_50, H1L632, E1_data_out);


--H1_E_src2[24] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[24]
H1_E_src2[24] = AMPP_FUNCTION(CLOCK_50, H1L386, H1_D_iw[14], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[24] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[24]
H1_E_src1[24] = AMPP_FUNCTION(CLOCK_50, H1L631, E1_data_out);


--H1_E_src2[23] is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[23]
H1_E_src2[23] = AMPP_FUNCTION(CLOCK_50, H1L383, H1_D_iw[13], E1_data_out, H1L643, H1_R_ctrl_hi_imm);


--H1_E_src1[23] is DE2_Board:inst|cpu_0:the_cpu_0|E_src1[23]
H1_E_src1[23] = AMPP_FUNCTION(CLOCK_50, H1L630, E1_data_out);


--H1L911 is DE2_Board:inst|cpu_0:the_cpu_0|add~1559
H1L911 = AMPP_FUNCTION(H1_E_src2[23], H1_E_src1[23], GND, H1L864);

--H1L912 is DE2_Board:inst|cpu_0:the_cpu_0|add~1560
H1L912 = AMPP_FUNCTION(H1_E_src2[23], H1_E_src1[23], H1L864);


--H1L913 is DE2_Board:inst|cpu_0:the_cpu_0|add~1561
H1L913 = AMPP_FUNCTION(H1_E_src2[24], H1_E_src1[24], GND, H1L912);

--H1L914 is DE2_Board:inst|cpu_0:the_cpu_0|add~1562
H1L914 = AMPP_FUNCTION(H1_E_src2[24], H1_E_src1[24], H1L912);


--H1L915 is DE2_Board:inst|cpu_0:the_cpu_0|add~1563
H1L915 = AMPP_FUNCTION(H1_E_src2[25], H1_E_src1[25], GND, H1L914);

--H1L916 is DE2_Board:inst|cpu_0:the_cpu_0|add~1564
H1L916 = AMPP_FUNCTION(H1_E_src2[25], H1_E_src1[25], H1L914);


--H1L917 is DE2_Board:inst|cpu_0:the_cpu_0|add~1565
H1L917 = AMPP_FUNCTION(H1_E_src2[26], H1_E_src1[26], GND, H1L916);

--H1L918 is DE2_Board:inst|cpu_0:the_cpu_0|add~1566
H1L918 = AMPP_FUNCTION(H1_E_src2[26], H1_E_src1[26], H1L916);


--H1L919 is DE2_Board:inst|cpu_0:the_cpu_0|add~1567
H1L919 = AMPP_FUNCTION(H1_E_src2[27], H1_E_src1[27], GND, H1L918);

--H1L920 is DE2_Board:inst|cpu_0:the_cpu_0|add~1568
H1L920 = AMPP_FUNCTION(H1_E_src2[27], H1_E_src1[27], H1L918);


--H1L921 is DE2_Board:inst|cpu_0:the_cpu_0|add~1569
H1L921 = AMPP_FUNCTION(H1_E_src2[28], H1_E_src1[28], GND, H1L920);

--H1L922 is DE2_Board:inst|cpu_0:the_cpu_0|add~1570
H1L922 = AMPP_FUNCTION(H1_E_src2[28], H1_E_src1[28], H1L920);


--H1L923 is DE2_Board:inst|cpu_0:the_cpu_0|add~1571
H1L923 = AMPP_FUNCTION(H1_E_src2[29], H1_E_src1[29], GND, H1L922);

--H1L924 is DE2_Board:inst|cpu_0:the_cpu_0|add~1572
H1L924 = AMPP_FUNCTION(H1_E_src2[29], H1_E_src1[29], H1L922);


--H1L925 is DE2_Board:inst|cpu_0:the_cpu_0|add~1573
H1L925 = AMPP_FUNCTION(H1_E_src2[30], H1_E_src1[30], GND, H1L924);

--H1L926 is DE2_Board:inst|cpu_0:the_cpu_0|add~1574
H1L926 = AMPP_FUNCTION(H1_E_src2[30], H1_E_src1[30], H1L924);


--H1L927 is DE2_Board:inst|cpu_0:the_cpu_0|add~1575
H1L927 = AMPP_FUNCTION(H1_E_arith_src2[31], H1_E_arith_src1[31], GND, H1L926);

--H1L928 is DE2_Board:inst|cpu_0:the_cpu_0|add~1576
H1L928 = AMPP_FUNCTION(H1_E_arith_src2[31], H1_E_arith_src1[31], H1L926);


--H1L929 is DE2_Board:inst|cpu_0:the_cpu_0|add~1577
H1L929 = AMPP_FUNCTION(H1L928);


--H1L931 is DE2_Board:inst|cpu_0:the_cpu_0|add~1579
H1L931 = AMPP_FUNCTION(H1_E_src2[23], H1_E_src1[23], GND, H1L910);

--H1L932 is DE2_Board:inst|cpu_0:the_cpu_0|add~1580
H1L932 = AMPP_FUNCTION(H1_E_src2[23], H1_E_src1[23], H1L910);


--H1L933 is DE2_Board:inst|cpu_0:the_cpu_0|add~1581
H1L933 = AMPP_FUNCTION(H1_E_src2[24], H1_E_src1[24], GND, H1L932);

--H1L934 is DE2_Board:inst|cpu_0:the_cpu_0|add~1582
H1L934 = AMPP_FUNCTION(H1_E_src2[24], H1_E_src1[24], H1L932);


--H1L935 is DE2_Board:inst|cpu_0:the_cpu_0|add~1583
H1L935 = AMPP_FUNCTION(H1_E_src2[25], H1_E_src1[25], GND, H1L934);

--H1L936 is DE2_Board:inst|cpu_0:the_cpu_0|add~1584
H1L936 = AMPP_FUNCTION(H1_E_src2[25], H1_E_src1[25], H1L934);


--H1L937 is DE2_Board:inst|cpu_0:the_cpu_0|add~1585
H1L937 = AMPP_FUNCTION(H1_E_src2[26], H1_E_src1[26], GND, H1L936);

--H1L938 is DE2_Board:inst|cpu_0:the_cpu_0|add~1586
H1L938 = AMPP_FUNCTION(H1_E_src2[26], H1_E_src1[26], H1L936);


--H1L939 is DE2_Board:inst|cpu_0:the_cpu_0|add~1587
H1L939 = AMPP_FUNCTION(H1_E_src2[27], H1_E_src1[27], GND, H1L938);

--H1L940 is DE2_Board:inst|cpu_0:the_cpu_0|add~1588
H1L940 = AMPP_FUNCTION(H1_E_src2[27], H1_E_src1[27], H1L938);


--H1L941 is DE2_Board:inst|cpu_0:the_cpu_0|add~1589
H1L941 = AMPP_FUNCTION(H1_E_src2[28], H1_E_src1[28], GND, H1L940);

--H1L942 is DE2_Board:inst|cpu_0:the_cpu_0|add~1590
H1L942 = AMPP_FUNCTION(H1_E_src2[28], H1_E_src1[28], H1L940);


--H1L943 is DE2_Board:inst|cpu_0:the_cpu_0|add~1591
H1L943 = AMPP_FUNCTION(H1_E_src2[29], H1_E_src1[29], GND, H1L942);

--H1L944 is DE2_Board:inst|cpu_0:the_cpu_0|add~1592
H1L944 = AMPP_FUNCTION(H1_E_src2[29], H1_E_src1[29], H1L942);


--H1L945 is DE2_Board:inst|cpu_0:the_cpu_0|add~1593
H1L945 = AMPP_FUNCTION(H1_E_src2[30], H1_E_src1[30], GND, H1L944);

--H1L946 is DE2_Board:inst|cpu_0:the_cpu_0|add~1594
H1L946 = AMPP_FUNCTION(H1_E_src2[30], H1_E_src1[30], H1L944);


--H1L947 is DE2_Board:inst|cpu_0:the_cpu_0|add~1595
H1L947 = AMPP_FUNCTION(H1_E_arith_src2[31], H1_E_arith_src1[31], GND, H1L946);

--H1L948 is DE2_Board:inst|cpu_0:the_cpu_0|add~1596
H1L948 = AMPP_FUNCTION(H1_E_arith_src2[31], H1_E_arith_src1[31], H1L946);


--H1L949 is DE2_Board:inst|cpu_0:the_cpu_0|add~1597
H1L949 = AMPP_FUNCTION(H1L948);


--H1L133 is DE2_Board:inst|cpu_0:the_cpu_0|E_arith_result[32]~167
H1L133 = AMPP_FUNCTION(H1L929, H1L949, H1_E_alu_sub);


--A1L81 is rtl~2824
A1L81 = !H1L171 & !H1L170 & !H1L169 & !H1L168;


--A1L82 is rtl~2825
A1L82 = !H1L167 & !H1L166 & !H1L165 & !H1L164;


--A1L83 is rtl~2826
A1L83 = !H1L163 & !H1L162 & !H1L161 & !H1L160;


--A1L84 is rtl~2827
A1L84 = !H1L159 & !H1L158 & !H1L157 & !H1L156;


--A1L85 is rtl~2828
A1L85 = A1L81 & A1L82 & A1L83 & A1L84;


--A1L86 is rtl~2829
A1L86 = !H1L155 & !H1L154 & !H1L153 & !H1L152;


--H1L172 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[23]~8400
H1L172 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[23], H1_E_src1[23], H1_R_logic_op[0]);


--H1L150 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[1]~8401
H1L150 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[1], H1_E_src1[1], H1_R_logic_op[0]);


--A1L87 is rtl~2830
A1L87 = !H1L172 & !H1L150;


--H1L148 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[0]~8402
H1L148 = AMPP_FUNCTION(H1_E_src2[0], H1_E_src1[0], H1_R_logic_op[0]);


--H1L149 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[0]~8403
H1L149 = AMPP_FUNCTION(H1L865, H1_R_logic_op[1], H1_R_logic_op[0], H1L148);


--A1L88 is rtl~2831
A1L88 = A1L86 & A1L87 & !H1L151 & !H1L149;


--H1L176 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[27]~8404
H1L176 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[27], H1_E_src1[27], H1_R_logic_op[0]);


--H1L173 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[24]~8405
H1L173 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[24], H1_E_src1[24], H1_R_logic_op[0]);


--H1L175 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[26]~8406
H1L175 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[26], H1_E_src1[26], H1_R_logic_op[0]);


--H1L174 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[25]~8407
H1L174 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[25], H1_E_src1[25], H1_R_logic_op[0]);


--A1L89 is rtl~2832
A1L89 = !H1L176 & !H1L173 & !H1L175 & !H1L174;


--H1L177 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[28]~8408
H1L177 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[28], H1_E_src1[28], H1_R_logic_op[0]);


--H1L180 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[31]~8409
H1L180 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[31], H1_E_src1[31], H1_R_logic_op[0]);


--H1L178 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[29]~8410
H1L178 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[29], H1_E_src1[29], H1_R_logic_op[0]);


--H1L179 is DE2_Board:inst|cpu_0:the_cpu_0|E_logic_result[30]~8411
H1L179 = AMPP_FUNCTION(H1_R_logic_op[1], H1_E_src2[30], H1_E_src1[30], H1_R_logic_op[0]);


--A1L90 is rtl~2833
A1L90 = !H1L177 & !H1L180 & !H1L178 & !H1L179;


--A1L69 is rtl~46
A1L69 = A1L85 & A1L88 & A1L89 & A1L90;


--H1_R_compare_op[0] is DE2_Board:inst|cpu_0:the_cpu_0|R_compare_op[0]
H1_R_compare_op[0] = AMPP_FUNCTION(CLOCK_50, H1L95, E1_data_out);


--H1L138 is DE2_Board:inst|cpu_0:the_cpu_0|E_cmp_result~348
H1L138 = AMPP_FUNCTION(H1_R_compare_op[1], H1L133, A1L69, H1_R_compare_op[0]);


--H1L17 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_br~25
H1L17 = AMPP_FUNCTION(H1_D_iw[1], H1_D_iw[2], H1_D_iw[0]);


--H1L35 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_jmp_direct~70
H1L35 = AMPP_FUNCTION(H1L34, H1_D_iw[1], H1_D_iw[2], H1_D_iw[5]);


--A1L91 is rtl~2834
A1L91 = H1_D_iw[11] & !H1_D_iw[16];


--H1_E_shift_rot_cnt[0] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[0]
H1_E_shift_rot_cnt[0] = AMPP_FUNCTION(CLOCK_50, H1L189, H1_E_src2[0], E1_data_out, H1_E_new_inst);


--H1_E_shift_rot_cnt[1] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[1]
H1_E_shift_rot_cnt[1] = AMPP_FUNCTION(CLOCK_50, H1L192, H1_E_src2[1], E1_data_out, H1_E_new_inst);


--H1_E_shift_rot_cnt[2] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[2]
H1_E_shift_rot_cnt[2] = AMPP_FUNCTION(CLOCK_50, H1L195, H1_E_src2[2], E1_data_out, H1_E_new_inst);


--H1L423 is DE2_Board:inst|cpu_0:the_cpu_0|E_stall~437
H1L423 = AMPP_FUNCTION(H1_E_new_inst, H1_E_shift_rot_cnt[0], H1_E_shift_rot_cnt[1], H1_E_shift_rot_cnt[2]);


--H1_E_shift_rot_cnt[3] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[3]
H1_E_shift_rot_cnt[3] = AMPP_FUNCTION(CLOCK_50, H1L198, H1_E_src2[3], E1_data_out, H1_E_new_inst);


--H1_E_shift_rot_cnt[4] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[4]
H1_E_shift_rot_cnt[4] = AMPP_FUNCTION(CLOCK_50, H1L201, H1_E_src2[4], E1_data_out, H1_E_new_inst);


--H1L424 is DE2_Board:inst|cpu_0:the_cpu_0|E_stall~438
H1L424 = AMPP_FUNCTION(H1L423, H1_E_shift_rot_cnt[3], H1_E_shift_rot_cnt[4]);


--H1L425 is DE2_Board:inst|cpu_0:the_cpu_0|E_stall~439
H1L425 = AMPP_FUNCTION(H1_d_write_nxt, H1_R_ctrl_shift_rot, H1_E_valid, H1L424);


--H1_av_ld_waiting_for_data is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_waiting_for_data
H1_av_ld_waiting_for_data = AMPP_FUNCTION(CLOCK_50, H1L1105, E1_data_out);


--H1L958 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_aligning_data_nxt~168
H1L958 = AMPP_FUNCTION(H1_d_read, J1_cpu_0_data_master_waitrequest);


--H1L1105 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_waiting_for_data_nxt~57
H1L1105 = AMPP_FUNCTION(H1_E_new_inst, H1_R_ctrl_ld, H1_av_ld_waiting_for_data, H1L958);


--H1_av_ld_align_cycle[0] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_align_cycle[0]
H1_av_ld_align_cycle[0] = AMPP_FUNCTION(CLOCK_50, H1L955, E1_data_out);


--H1_av_ld_align_cycle[1] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_align_cycle[1]
H1_av_ld_align_cycle[1] = AMPP_FUNCTION(CLOCK_50, H1L956, E1_data_out);


--H1L959 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_aligning_data_nxt~169
H1L959 = AMPP_FUNCTION(H1_D_iw[3], H1_D_iw[4], H1_av_ld_align_cycle[0], H1_av_ld_align_cycle[1]);


--H1_av_ld_aligning_data is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_aligning_data
H1_av_ld_aligning_data = AMPP_FUNCTION(CLOCK_50, H1L960, E1_data_out);


--H1L960 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_aligning_data_nxt~170
H1L960 = AMPP_FUNCTION(H1L959, H1_av_ld_aligning_data, H1L958, H1_D_iw[4]);


--H1L426 is DE2_Board:inst|cpu_0:the_cpu_0|E_stall~440
H1L426 = AMPP_FUNCTION(H1_E_valid, H1L1105, H1L960, H1_D_iw[4]);


--H1L427 is DE2_Board:inst|cpu_0:the_cpu_0|E_stall~441
H1L427 = AMPP_FUNCTION(H1L425, H1_R_ctrl_ld, H1_E_new_inst, H1L426);


--H1L773 is DE2_Board:inst|cpu_0:the_cpu_0|W_valid~0
H1L773 = AMPP_FUNCTION(H1_E_valid, H1L427);


--P1L2 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_qualified_request_firmware_ROM_s1~95
P1L2 = !J1_cpu_0_data_master_waitrequest # !AB1_d_write;


--P1L9 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_requests_firmware_ROM_s1~287
P1L9 = A1L77 & P1L8 & !H1_W_alu_result[15] & !H1_W_alu_result[14];


--P1L10 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_requests_firmware_ROM_s1~288
P1L10 = !H1_W_alu_result[17] & !H1_W_alu_result[13] & !H1_W_alu_result[12];


--M1L4 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_requests_data_RAM_s1~259
M1L4 = !H1_W_alu_result[11] & !H1_W_alu_result[10];


--M1_cpu_0_data_master_requests_data_RAM_s1 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_requests_data_RAM_s1
M1_cpu_0_data_master_requests_data_RAM_s1 = H1_W_alu_result[16] & P1L9 & P1L10 & M1L4;


--M1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register
M1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register = DFFEAS(M1_registered_cpu_0_data_master_read_data_valid_data_RAM_s1, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--M1L1 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_data_master_qualified_request_data_RAM_s1~100
M1L1 = P1L2 & M1_cpu_0_data_master_requests_data_RAM_s1 & (!M1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register # !H1_d_read);


--M1_data_RAM_s1_arb_addend[1] is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_arb_addend[1]
M1_data_RAM_s1_arb_addend[1] = DFFEAS(M1L21, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--M1L7 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_in~12
M1L7 = M1L6 & (!M1_data_RAM_s1_arb_addend[1] # !M1L1);


--T1L18 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register_in~67
T1L18 = T1L13 & (!T1_payload_buffer_s1_arb_addend[1] # !T1L8);


--T1_payload_buffer_s1_arb_share_counter[2] is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter[2]
T1_payload_buffer_s1_arb_share_counter[2] = DFFEAS(T1L50, CLOCK_50, E1_data_out,  , T1L1,  ,  ,  ,  );


--T1_payload_buffer_s1_arb_share_counter[0] is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter[0]
T1_payload_buffer_s1_arb_share_counter[0] = DFFEAS(T1L47, CLOCK_50, E1_data_out,  , T1L1,  ,  ,  ,  );


--T1_payload_buffer_s1_arb_share_counter[1] is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter[1]
T1_payload_buffer_s1_arb_share_counter[1] = DFFEAS(T1L48, CLOCK_50, E1_data_out,  , T1L1,  ,  ,  ,  );


--T1L55 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~99
T1L55 = T1_payload_buffer_s1_slavearbiterlockenable & (T1L54 # T1_last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1 & T1L11);


--T1L49 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter_next_value[2]~137
T1L49 = T1_payload_buffer_s1_arb_share_counter[2] # T1_payload_buffer_s1_arb_share_counter[0] # T1_payload_buffer_s1_arb_share_counter[1] # !T1L55;


--T1L1 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|add~525
T1L1 = T1L13 # T1L8;


--T1L2 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|add~526
T1L2 = !T1L55 # !T1_payload_buffer_s1_arb_share_counter[2];


--T1L61 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_slavearbiterlockenable~93
T1L61 = T1L49 & (T1L3 # !T1L2 # !T1L4);


--T1L62 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_slavearbiterlockenable~94
T1L62 = T1L13 & T1L61 # !T1L13 & (T1L8 & T1L61 # !T1L8 & (T1_payload_buffer_s1_slavearbiterlockenable));


--T1_payload_buffer_s1_saved_chosen_master_vector[1] is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_saved_chosen_master_vector[1]
T1_payload_buffer_s1_saved_chosen_master_vector[1] = DFFEAS(T1L56, CLOCK_50, E1_data_out,  , T1L51,  ,  ,  ,  );


--T1L51 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_winner~0
T1L51 = !T1L55 & (T1L13 # T1L8);


--T1L20 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1~130
T1L20 = T1L51 & T1L56 # !T1L51 & (T1_payload_buffer_s1_saved_chosen_master_vector[1]);


--T1L21 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1~131
T1L21 = T1L55 # !T1L13 & !T1L8;


--T1L22 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1~132
T1L22 = T1L11 & (T1L20 # T1_last_cycle_cpu_0_data_master_granted_slave_payload_buffer_s1 & T1L21);


--P1_cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register
P1_cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register = DFFEAS(P1_registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--P1L3 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_qualified_request_firmware_ROM_s1~96
P1L3 = H1_d_read & !P1_cpu_0_data_master_read_data_valid_firmware_ROM_s1_shift_register & (!J1_cpu_0_data_master_waitrequest # !AB1_d_write) # !H1_d_read & (!J1_cpu_0_data_master_waitrequest # !AB1_d_write);


--P1L4 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_qualified_request_firmware_ROM_s1~97
P1L4 = P1L9 & P1L10 & P1L3 & !H1_W_alu_result[16];


--P1_firmware_ROM_s1_arb_addend[1] is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_arb_addend[1]
P1_firmware_ROM_s1_arb_addend[1] = DFFEAS(P1L27, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--P1L13 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_instruction_master_read_data_valid_firmware_ROM_s1_shift_register_in~14
P1L13 = P1L12 & (!P1_firmware_ROM_s1_arb_addend[1] # !P1L4);


--W1_tri_state_bridge_0_avalon_slave_arb_counter_enable is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_counter_enable
W1_tri_state_bridge_0_avalon_slave_arb_counter_enable = W1L62 & (!W1_cfi_flash_0_s1_in_a_read_cycle & W1_in_a_write_cycle # !W1L16);


--H1L1 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~318
H1L1 = AMPP_FUNCTION(A1L68, H1L9, H1L11, H1_D_iw[4]);


--H1L96 is DE2_Board:inst|cpu_0:the_cpu_0|D_logic_op_raw[1]~97
H1L96 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[15], H1_D_iw[3], A1L64);


--H1L2 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~319
H1L2 = AMPP_FUNCTION(H1_D_iw[12], H1_D_iw[13], H1_D_iw[11]);


--H1L3 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~320
H1L3 = AMPP_FUNCTION(H1_D_iw[14], H1_D_iw[16], H1_D_iw[15]);


--H1L4 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_force_xor~321
H1L4 = AMPP_FUNCTION(A1L64, H1L2, H1L3, H1L12);


--H1L94 is DE2_Board:inst|cpu_0:the_cpu_0|D_logic_op[1]~94
H1L94 = AMPP_FUNCTION(H1L1, H1L96, H1_D_iw[3], H1L4);


--H1L95 is DE2_Board:inst|cpu_0:the_cpu_0|D_logic_op_raw[0]~98
H1L95 = AMPP_FUNCTION(H1_D_iw[3], H1_D_iw[14], H1_D_iw[4], A1L64);


--H1L93 is DE2_Board:inst|cpu_0:the_cpu_0|D_logic_op[0]~95
H1L93 = AMPP_FUNCTION(H1L1, H1L95, H1_D_iw[3], H1L4);


--H1L42 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_shift_rot~53
H1L42 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], H1_D_iw[12], A1L64);


--A1L92 is rtl~2835
A1L92 = H1_D_iw[13] & H1L42 & !H1_D_iw[11] & !H1_D_iw[16];


--A1L72 is rtl~68
A1L72 = !H1_D_iw[0] & !H1_D_iw[1] & H1_D_iw[2] & !H1_D_iw[5];


--H1L21 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_logic_result~67
H1L21 = AMPP_FUNCTION(A1L92, A1L65, A1L72, H1L34);


--H1_E_shift_rot_result[23] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[23]
H1_E_shift_rot_result[23] = AMPP_FUNCTION(CLOCK_50, H1L260, H1_E_src1[23], E1_data_out, H1_E_new_inst);


--H1_R_ctrl_shift_rot_right is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_shift_rot_right
H1_R_ctrl_shift_rot_right = AMPP_FUNCTION(CLOCK_50, H1L39, E1_data_out);


--H1L259 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[22]~444
H1L259 = AMPP_FUNCTION(H1_E_shift_rot_result[23], H1_E_shift_rot_result[21], H1_R_ctrl_shift_rot_right);


--H1L18 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_cmp~265
H1L18 = AMPP_FUNCTION(A1L67, A1L68, H1_D_iw[3], H1_D_iw[4]);


--H1L19 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_cmp~266
H1L19 = AMPP_FUNCTION(A1L67, H1_D_iw[3], A1L64, H1L2);


--H1L20 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_dst_data_sel_cmp~267
H1L20 = AMPP_FUNCTION(H1L18, H1_D_iw[4], H1L19, H1L11);


--A1L93 is rtl~2836
A1L93 = H1_D_iw[13] & H1L42 & !H1_D_iw[15];


--A1L71 is rtl~65
A1L71 = H1_D_iw[16] & A1L93 & !H1_D_iw[11] & !H1_D_iw[14];


--H1L43 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_shift_rot~54
H1L43 = AMPP_FUNCTION(H1L42, H1_D_iw[13]);


--H1L37 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_ld~21
H1L37 = AMPP_FUNCTION(H1_D_iw[2], H1_D_iw[1], H1_D_iw[0], H1_D_iw[4]);


--J1L115 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~370
J1L115 = !W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (W1L29 # W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--J1L116 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~371
J1L116 = H1_d_read & J1_cpu_0_data_master_dbs_address[1] # !H1_d_read & (J1L115);


--J1L117 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~372
J1L117 = J1L116 & W1L21 # !J1L116 & H1_d_read & (W1L21 # T1L8);


--J1L118 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~373
J1L118 = J1L117 # T1L13 & !T1_payload_buffer_s1_arb_addend[1] & T1L8;


--P1L1 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|add~324
P1L1 = P1L12 & P1L4 & !P1_firmware_ROM_s1_arb_addend[1];


--J1L119 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~374
J1L119 = P1L1 # M1L6 & M1L1 & !M1_data_RAM_s1_arb_addend[1];


--J1L120 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~375
J1L120 = T1L11 & !T1L8 & (!J1L177 # !AB1_d_write);


--A1L94 is rtl~2837
A1L94 = A1L77 & !H1_W_alu_result[15] & !H1_W_alu_result[14];


--A1L95 is rtl~2838
A1L95 = !H1_W_alu_result[13] & !H1_W_alu_result[12] & !H1_W_alu_result[11] & !H1_W_alu_result[10];


--A1L96 is rtl~2839
A1L96 = !H1_W_alu_result[9] & !H1_W_alu_result[8] & !H1_W_alu_result[7] & !H1_W_alu_result[6];


--A1L97 is rtl~2840
A1L97 = A1L94 & A1L95 & A1L96 & !H1_W_alu_result[5];


--A1L98 is rtl~2841
A1L98 = H1_W_alu_result[17] & !H1_W_alu_result[18] & !H1_W_alu_result[4] & !H1_W_alu_result[3];


--Q1_av_waitrequest is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|av_waitrequest
Q1_av_waitrequest = DFFEAS(Q1L65, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--A1L99 is rtl~2842
A1L99 = H1_W_alu_result[16] & A1L97 & A1L98 & !Q1_av_waitrequest;


--J1L197 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_1~267
J1L197 = J1_cpu_0_data_master_dbs_address[0] & J1_cpu_0_data_master_dbs_address[1];


--J1L198 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_1~268
J1L198 = W1L86 & W1_cfi_flash_0_s1_wait_counter[0] & J1L197 & !W1_cfi_flash_0_s1_wait_counter[3];


--J1L121 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~376
J1L121 = A1L99 # AB1_d_write & W1L21 & !J1L198;


--P1_cpu_0_data_master_requests_firmware_ROM_s1 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_requests_firmware_ROM_s1
P1_cpu_0_data_master_requests_firmware_ROM_s1 = A1L94 & P1L8 & P1L10 & !H1_W_alu_result[16];


--P1L7 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|cpu_0_data_master_requests_firmware_ROM_s1~0
P1L7 = H1_d_read # AB1_d_write;


--J1L122 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~377
J1L122 = J1_cpu_0_data_master_waitrequest # P1_cpu_0_data_master_requests_firmware_ROM_s1 & !P1L4 # !P1L7;


--J1L123 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~378
J1L123 = J1L121 # J1L122 # M1_cpu_0_data_master_requests_data_RAM_s1 & !M1L1;


--J1L199 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_1~269
J1L199 = W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] # AB1_d_write & !H1_d_byteenable[3];


--J1L200 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_1~270
J1L200 = W1L21 # J1L197 & J1L199 # !W1_cpu_0_data_master_requests_cfi_flash_0_s1;


--J1L124 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~379
J1L124 = J1L119 # J1L120 # J1L123 # !J1L200;


--J1L176 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~496
J1L176 = AB1_d_write & H1_W_alu_result[17] & P1L9 & !H1_W_alu_result[16];


--J1L125 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest~380
J1L125 = !J1L118 & !J1L124 & (J1_cpu_0_data_master_dbs_address[1] # !J1L176);


--H1L44 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_st~32
H1L44 = AMPP_FUNCTION(H1_D_iw[0], H1_D_iw[1]);


--T1_payload_buffer_s1_saved_chosen_master_vector[0] is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_saved_chosen_master_vector[0]
T1_payload_buffer_s1_saved_chosen_master_vector[0] = DFFEAS(T1L18, CLOCK_50, E1_data_out,  , T1L51,  ,  ,  ,  );


--T1L24 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1~123
T1L24 = T1L51 & (!T1L18) # !T1L51 & !T1_payload_buffer_s1_saved_chosen_master_vector[0];


--T1L25 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1~124
T1L25 = T1L17 & (T1_last_cycle_cpu_0_instruction_master_granted_slave_payload_buffer_s1 & T1L21 # !T1L24);


--T1_registered_cpu_0_data_master_read_data_valid_payload_buffer_s1 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|registered_cpu_0_data_master_read_data_valid_payload_buffer_s1
T1_registered_cpu_0_data_master_read_data_valid_payload_buffer_s1 = H1_d_read & T1L8 & (T1_payload_buffer_s1_arb_addend[1] # !T1L13);


--H1_W_status_reg_pie is DE2_Board:inst|cpu_0:the_cpu_0|W_status_reg_pie
H1_W_status_reg_pie = AMPP_FUNCTION(CLOCK_50, H1L771, E1_data_out, H1_E_valid);


--H1_W_ipending_reg[1] is DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[1]
H1_W_ipending_reg[1] = AMPP_FUNCTION(CLOCK_50, H1L765, E1_data_out);


--H1_W_ipending_reg[0] is DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg[0]
H1_W_ipending_reg[0] = AMPP_FUNCTION(CLOCK_50, H1L766, E1_data_out);


--H1L1171 is DE2_Board:inst|cpu_0:the_cpu_0|intr_req~106
H1L1171 = AMPP_FUNCTION(H1_W_status_reg_pie, H1_W_ipending_reg[1], H1_W_ipending_reg[0]);


--DB1_q_a[4] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[4]_PORT_A_data_in = H1_d_writedata[4];
DB1_q_a[4]_PORT_A_data_in_reg = DFFE(DB1_q_a[4]_PORT_A_data_in, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[4]_PORT_A_address_reg = DFFE(DB1_q_a[4]_PORT_A_address, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[4]_PORT_B_address_reg = DFFE(DB1_q_a[4]_PORT_B_address, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4]_PORT_A_write_enable = L1L1;
DB1_q_a[4]_PORT_A_write_enable_reg = DFFE(DB1_q_a[4]_PORT_A_write_enable, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4]_PORT_A_byte_mask = M1L22;
DB1_q_a[4]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[4]_PORT_A_byte_mask, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4]_clock_0 = CLOCK_50;
DB1_q_a[4]_PORT_A_data_out = MEMORY(DB1_q_a[4]_PORT_A_data_in_reg, , DB1_q_a[4]_PORT_A_address_reg, DB1_q_a[4]_PORT_B_address_reg, DB1_q_a[4]_PORT_A_write_enable_reg, , DB1_q_a[4]_PORT_A_byte_mask_reg, , DB1_q_a[4]_clock_0, , , , , );
DB1_q_a[4] = DB1_q_a[4]_PORT_A_data_out[0];


--EB1_q_a[4] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[4]_PORT_A_data_in = H1_d_writedata[4];
EB1_q_a[4]_PORT_A_data_in_reg = DFFE(EB1_q_a[4]_PORT_A_data_in, EB1_q_a[4]_clock_0, , , );
EB1_q_a[4]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[4]_PORT_A_address_reg = DFFE(EB1_q_a[4]_PORT_A_address, EB1_q_a[4]_clock_0, , , );
EB1_q_a[4]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[4]_PORT_B_address_reg = DFFE(EB1_q_a[4]_PORT_B_address, EB1_q_a[4]_clock_0, , , );
EB1_q_a[4]_PORT_A_write_enable = GND;
EB1_q_a[4]_PORT_A_write_enable_reg = DFFE(EB1_q_a[4]_PORT_A_write_enable, EB1_q_a[4]_clock_0, , , );
EB1_q_a[4]_PORT_A_byte_mask = P1L28;
EB1_q_a[4]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[4]_PORT_A_byte_mask, EB1_q_a[4]_clock_0, , , );
EB1_q_a[4]_clock_0 = CLOCK_50;
EB1_q_a[4]_PORT_A_data_out = MEMORY(EB1_q_a[4]_PORT_A_data_in_reg, , EB1_q_a[4]_PORT_A_address_reg, EB1_q_a[4]_PORT_B_address_reg, EB1_q_a[4]_PORT_A_write_enable_reg, , EB1_q_a[4]_PORT_A_byte_mask_reg, , EB1_q_a[4]_clock_0, , , , , );
EB1_q_a[4] = EB1_q_a[4]_PORT_A_data_out[0];


--H1L433 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3099
H1L433 = AMPP_FUNCTION(DB1_q_a[4], EB1_q_a[4], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[4] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[4]
K1_dbs_16_reg_segment_0[4] = DFFEAS(VB1L5, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_0[4] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[4]
K1_dbs_8_reg_segment_0[4] = DFFEAS(W1_incoming_tri_state_bridge_0_data[4], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--H1L434 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3100
H1L434 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[4], K1_dbs_8_reg_segment_0[4], W1L34, T1L17);


--H1L435 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3101
H1L435 = AMPP_FUNCTION(H1L1171, H1L433, H1L434);


--H1_F_valid is DE2_Board:inst|cpu_0:the_cpu_0|F_valid
H1_F_valid = AMPP_FUNCTION(K1L11, K1L13, H1_i_read);


--DB1_q_a[3] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[3]_PORT_A_data_in = H1_d_writedata[3];
DB1_q_a[3]_PORT_A_data_in_reg = DFFE(DB1_q_a[3]_PORT_A_data_in, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[3]_PORT_A_address_reg = DFFE(DB1_q_a[3]_PORT_A_address, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[3]_PORT_B_address_reg = DFFE(DB1_q_a[3]_PORT_B_address, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_A_write_enable = L1L1;
DB1_q_a[3]_PORT_A_write_enable_reg = DFFE(DB1_q_a[3]_PORT_A_write_enable, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_PORT_A_byte_mask = M1L22;
DB1_q_a[3]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[3]_PORT_A_byte_mask, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_clock_0 = CLOCK_50;
DB1_q_a[3]_PORT_A_data_out = MEMORY(DB1_q_a[3]_PORT_A_data_in_reg, , DB1_q_a[3]_PORT_A_address_reg, DB1_q_a[3]_PORT_B_address_reg, DB1_q_a[3]_PORT_A_write_enable_reg, , DB1_q_a[3]_PORT_A_byte_mask_reg, , DB1_q_a[3]_clock_0, , , , , );
DB1_q_a[3] = DB1_q_a[3]_PORT_A_data_out[0];


--EB1_q_a[3] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[3]_PORT_A_data_in = H1_d_writedata[3];
EB1_q_a[3]_PORT_A_data_in_reg = DFFE(EB1_q_a[3]_PORT_A_data_in, EB1_q_a[3]_clock_0, , , );
EB1_q_a[3]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[3]_PORT_A_address_reg = DFFE(EB1_q_a[3]_PORT_A_address, EB1_q_a[3]_clock_0, , , );
EB1_q_a[3]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[3]_PORT_B_address_reg = DFFE(EB1_q_a[3]_PORT_B_address, EB1_q_a[3]_clock_0, , , );
EB1_q_a[3]_PORT_A_write_enable = GND;
EB1_q_a[3]_PORT_A_write_enable_reg = DFFE(EB1_q_a[3]_PORT_A_write_enable, EB1_q_a[3]_clock_0, , , );
EB1_q_a[3]_PORT_A_byte_mask = P1L28;
EB1_q_a[3]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[3]_PORT_A_byte_mask, EB1_q_a[3]_clock_0, , , );
EB1_q_a[3]_clock_0 = CLOCK_50;
EB1_q_a[3]_PORT_A_data_out = MEMORY(EB1_q_a[3]_PORT_A_data_in_reg, , EB1_q_a[3]_PORT_A_address_reg, EB1_q_a[3]_PORT_B_address_reg, EB1_q_a[3]_PORT_A_write_enable_reg, , EB1_q_a[3]_PORT_A_byte_mask_reg, , EB1_q_a[3]_clock_0, , , , , );
EB1_q_a[3] = EB1_q_a[3]_PORT_A_data_out[0];


--H1L436 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3102
H1L436 = AMPP_FUNCTION(DB1_q_a[3], EB1_q_a[3], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[3] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[3]
K1_dbs_16_reg_segment_0[3] = DFFEAS(VB1L4, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_0[3] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[3]
K1_dbs_8_reg_segment_0[3] = DFFEAS(W1_incoming_tri_state_bridge_0_data[3], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--H1L437 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3103
H1L437 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[3], K1_dbs_8_reg_segment_0[3], W1L34, T1L17);


--H1L438 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3104
H1L438 = AMPP_FUNCTION(H1L1171, H1L436, H1L437);


--H1L258 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[21]~445
H1L258 = AMPP_FUNCTION(H1_E_shift_rot_result[22], H1_E_shift_rot_result[20], H1_R_ctrl_shift_rot_right);


--H1L257 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[20]~446
H1L257 = AMPP_FUNCTION(H1_E_shift_rot_result[21], H1_E_shift_rot_result[19], H1_R_ctrl_shift_rot_right);


--H1L256 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[19]~447
H1L256 = AMPP_FUNCTION(H1_E_shift_rot_result[20], H1_E_shift_rot_result[18], H1_R_ctrl_shift_rot_right);


--H1L255 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[18]~448
H1L255 = AMPP_FUNCTION(H1_E_shift_rot_result[19], H1_E_shift_rot_result[17], H1_R_ctrl_shift_rot_right);


--H1L254 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[17]~449
H1L254 = AMPP_FUNCTION(H1_E_shift_rot_result[18], H1_E_shift_rot_result[16], H1_R_ctrl_shift_rot_right);


--H1L253 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[16]~450
H1L253 = AMPP_FUNCTION(H1_E_shift_rot_result[17], H1_E_shift_rot_result[15], H1_R_ctrl_shift_rot_right);


--H1L252 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[15]~451
H1L252 = AMPP_FUNCTION(H1_E_shift_rot_result[16], H1_E_shift_rot_result[14], H1_R_ctrl_shift_rot_right);


--H1L251 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[14]~452
H1L251 = AMPP_FUNCTION(H1_E_shift_rot_result[15], H1_E_shift_rot_result[13], H1_R_ctrl_shift_rot_right);


--H1L250 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[13]~453
H1L250 = AMPP_FUNCTION(H1_E_shift_rot_result[14], H1_E_shift_rot_result[12], H1_R_ctrl_shift_rot_right);


--H1L249 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[12]~454
H1L249 = AMPP_FUNCTION(H1_E_shift_rot_result[13], H1_E_shift_rot_result[11], H1_R_ctrl_shift_rot_right);


--H1L248 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[11]~455
H1L248 = AMPP_FUNCTION(H1_E_shift_rot_result[12], H1_E_shift_rot_result[10], H1_R_ctrl_shift_rot_right);


--H1L247 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[10]~456
H1L247 = AMPP_FUNCTION(H1_E_shift_rot_result[11], H1_E_shift_rot_result[9], H1_R_ctrl_shift_rot_right);


--H1L246 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[9]~457
H1L246 = AMPP_FUNCTION(H1_E_shift_rot_result[10], H1_E_shift_rot_result[8], H1_R_ctrl_shift_rot_right);


--H1L245 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[8]~458
H1L245 = AMPP_FUNCTION(H1_E_shift_rot_result[9], H1_E_shift_rot_result[7], H1_R_ctrl_shift_rot_right);


--H1L244 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[7]~459
H1L244 = AMPP_FUNCTION(H1_E_shift_rot_result[8], H1_E_shift_rot_result[6], H1_R_ctrl_shift_rot_right);


--H1L243 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[6]~460
H1L243 = AMPP_FUNCTION(H1_E_shift_rot_result[7], H1_E_shift_rot_result[5], H1_R_ctrl_shift_rot_right);


--H1L242 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[5]~461
H1L242 = AMPP_FUNCTION(H1_E_shift_rot_result[6], H1_E_shift_rot_result[4], H1_R_ctrl_shift_rot_right);


--H1L241 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[4]~462
H1L241 = AMPP_FUNCTION(H1_E_shift_rot_result[5], H1_E_shift_rot_result[3], H1_R_ctrl_shift_rot_right);


--H1L240 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[3]~463
H1L240 = AMPP_FUNCTION(H1_E_shift_rot_result[4], H1_E_shift_rot_result[2], H1_R_ctrl_shift_rot_right);


--H1_E_shift_rot_result[1] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[1]
H1_E_shift_rot_result[1] = AMPP_FUNCTION(CLOCK_50, H1L238, H1_E_src1[1], E1_data_out, H1_E_new_inst);


--H1L239 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[2]~464
H1L239 = AMPP_FUNCTION(H1_E_shift_rot_result[3], H1_E_shift_rot_result[1], H1_R_ctrl_shift_rot_right);


--ZB3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]
ZB3_Q[1] = AMPP_FUNCTION(A1L5, D1L21, D1_CLRN_SIGNAL, ZB3L6);


--ZB4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]
ZB4_Q[0] = AMPP_FUNCTION(A1L5, ZB4L4, D1_CLRN_SIGNAL);


--ZB3_Q[3] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]
ZB3_Q[3] = AMPP_FUNCTION(A1L5, D1L23, D1_CLRN_SIGNAL, ZB3L6);


--ZB3_Q[4] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4]
ZB3_Q[4] = AMPP_FUNCTION(A1L5, D1L8, D1_CLRN_SIGNAL, D1_IRSR_ENA);


--EC1_dffe1a[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[3]
EC1_dffe1a[3] = AMPP_FUNCTION(A1L5, EC1_w_anode38w[3], D1_CLRN_SIGNAL, D1L6);


--D1L15 is sld_hub:sld_hub_inst|IR_MUX_SEL~12
D1L15 = AMPP_FUNCTION(ZB3_Q[3], ZB3_Q[4], EC1_dffe1a[3]);


--D1L19 is sld_hub:sld_hub_inst|IRSR_D[0]~272
D1L19 = AMPP_FUNCTION(ZB4_Q[0], ZB3_Q[0], D1L15);


--D1L20 is sld_hub:sld_hub_inst|IRSR_D[0]~273
D1L20 = AMPP_FUNCTION(ZB3_Q[1], D1L19, DC1_state[4]);


--D1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL
D1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, D1L4);


--D1_IRSR_ENA is sld_hub:sld_hub_inst|IRSR_ENA
D1_IRSR_ENA = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, DC1_state[3], DC1_state[4]);


--D1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
D1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, D1L32);


--D1L16 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21
D1L16 = AMPP_FUNCTION(A1L7, DC1_state[4], D1_jtag_debug_mode_usr1, D1_OK_TO_UPDATE_IR_Q);


--FB1_state is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state
FB1_state = AMPP_FUNCTION(A1L5, FB1L57, D1_CLRN_SIGNAL);


--FB1L45 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~654
FB1L45 = AMPP_FUNCTION(altera_internal_jtag, FB1_state);


--FB1_count[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[1]
FB1_count[1] = AMPP_FUNCTION(A1L5, FB1L14, D1_CLRN_SIGNAL, FB1L44);


--FB1_user_saw_rvalid is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid
FB1_user_saw_rvalid = AMPP_FUNCTION(A1L5, FB1L90, D1_CLRN_SIGNAL);


--FB1_td_shift[9] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9]
FB1_td_shift[9] = AMPP_FUNCTION(A1L5, FB1L76, D1_CLRN_SIGNAL, !DC1_state[4], FB1L44);


--FB1L46 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~655
FB1L46 = AMPP_FUNCTION(FB1_count[1], FB1_state, FB1_user_saw_rvalid, FB1_td_shift[9]);


--Q1_t_dav is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|t_dav
Q1_t_dav = DFFEAS(MB2_b_full, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--FB1_td_shift[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1]
FB1_td_shift[1] = AMPP_FUNCTION(A1L5, FB1L77, D1_CLRN_SIGNAL, FB1L44);


--FB1_rvalid is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid
FB1_rvalid = AMPP_FUNCTION(CLOCK_50, FB1_rvalid0, E1_data_out);


--FB1_count[9] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9]
FB1_count[9] = AMPP_FUNCTION(A1L5, FB1L51, D1_CLRN_SIGNAL, FB1L44);


--FB1L47 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~656
FB1L47 = AMPP_FUNCTION(FB1_td_shift[1], FB1_rvalid, FB1_count[9]);


--FB1L48 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~657
FB1L48 = AMPP_FUNCTION(ZB4_Q[0], FB1L46, Q1_t_dav, FB1L47);


--FB1L49 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~658
FB1L49 = AMPP_FUNCTION(DC1_state[3], DC1_state[4], ZB4_Q[0]);


--FB1L50 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~659
FB1L50 = AMPP_FUNCTION(FB1L45, FB1L48, ZB4_Q[0], FB1L49);


--D1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
D1_jtag_debug_mode = AMPP_FUNCTION(A1L5, D1L30, DC1_state[0]);


--ZB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
ZB2_Q[0] = AMPP_FUNCTION(A1L5, ZB2L3, D1_CLRN_SIGNAL);


--FB1L1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~57
FB1L1 = AMPP_FUNCTION(ZB6_Q[0], D1_jtag_debug_mode, D1_jtag_debug_mode_usr1, ZB2_Q[0]);


--FB1L44 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~12
FB1L44 = AMPP_FUNCTION(FB1L1, DC1_state[3], DC1_state[4]);


--AC1_WORD_SR[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]
AC1_WORD_SR[1] = AMPP_FUNCTION(A1L5, AC1L28, AC1L24);


--AC1L26 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~750
AC1L26 = AMPP_FUNCTION(DC1_state[4], AC1_WORD_SR[1], D1_jtag_debug_mode_usr1, DC1_state[8]);


--D1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0
D1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, A1L63, DC1_state[0], DC1_state[12]);


--AC1_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal
AC1_clear_signal = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, DC1_state[8]);


--AC1L24 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2]~751
AC1L24 = AMPP_FUNCTION(DC1_state[3], DC1_state[4], D1_jtag_debug_mode_usr0, AC1_clear_signal);


--D1L8 is sld_hub:sld_hub_inst|HUB_BYPASS_REG~11
D1L8 = AMPP_FUNCTION(altera_internal_jtag, DC1_state[4]);


--D1L28 is sld_hub:sld_hub_inst|jtag_debug_mode~2
D1L28 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, D1_jtag_debug_mode_usr0);


--ZB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
ZB3_Q[2] = AMPP_FUNCTION(A1L5, D1L22, D1_CLRN_SIGNAL, ZB3L6);


--EC1_w_anode1w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode1w[3]
EC1_w_anode1w[3] = AMPP_FUNCTION(D1L28, ZB3_Q[1], ZB3_Q[3], ZB3_Q[2]);


--D1L5 is sld_hub:sld_hub_inst|comb~51
D1L5 = AMPP_FUNCTION(DC1_state[3], DC1_state[4], D1_jtag_debug_mode_usr1, D1_jtag_debug_mode_usr0);


--D1L6 is sld_hub:sld_hub_inst|comb~52
D1L6 = AMPP_FUNCTION(A1L7, D1L5, altera_internal_jtag);


--CC1_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1]
CC1_dffs[1] = AMPP_FUNCTION(A1L5, CC1_dffs[2], DC1_state[0], DC1_state[11]);


--CC1_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
CC1_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, DC1_state[0], DC1_state[11]);


--CC1_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]
CC1_dffs[8] = AMPP_FUNCTION(A1L5, CC1_dffs[9], DC1_state[0], DC1_state[11]);


--CC1_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7]
CC1_dffs[7] = AMPP_FUNCTION(A1L5, CC1_dffs[8], DC1_state[0], DC1_state[11]);


--CC1_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6]
CC1_dffs[6] = AMPP_FUNCTION(A1L5, CC1_dffs[7], DC1_state[0], DC1_state[11]);


--A1L100 is rtl~2843
A1L100 = !CC1_dffs[9] & !CC1_dffs[8] & !CC1_dffs[7] & !CC1_dffs[6];


--CC1_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]
CC1_dffs[3] = AMPP_FUNCTION(A1L5, CC1_dffs[4], DC1_state[0], DC1_state[11]);


--CC1_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2]
CC1_dffs[2] = AMPP_FUNCTION(A1L5, CC1_dffs[3], DC1_state[0], DC1_state[11]);


--CC1_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5]
CC1_dffs[5] = AMPP_FUNCTION(A1L5, CC1_dffs[6], DC1_state[0], DC1_state[11]);


--CC1_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]
CC1_dffs[4] = AMPP_FUNCTION(A1L5, CC1_dffs[5], DC1_state[0], DC1_state[11]);


--A1L101 is rtl~2844
A1L101 = CC1_dffs[3] & CC1_dffs[2] & !CC1_dffs[5] & !CC1_dffs[4];


--CC1_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0]
CC1_dffs[0] = AMPP_FUNCTION(A1L5, CC1_dffs[1], DC1_state[0], DC1_state[11]);


--A1L61 is rtl~3
A1L61 = CC1_dffs[1] & A1L100 & A1L101 & !CC1_dffs[0];


--DC1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]
DC1_state[0] = AMPP_FUNCTION(A1L5, DC1L31);


--DC1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12]
DC1_state[12] = AMPP_FUNCTION(A1L5, DC1L32);


--DC1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]
DC1_state[2] = AMPP_FUNCTION(A1L5, DC1L33);


--DC1L19 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~10
DC1L19 = AMPP_FUNCTION(DC1_state[2], A1L7);


--DC1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]
DC1_state[7] = AMPP_FUNCTION(A1L5, DC1L23);


--DC1L20 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~11
DC1L20 = AMPP_FUNCTION(DC1_state[3], DC1_state[4], DC1_state[7]);


--DC1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
DC1_state[5] = AMPP_FUNCTION(A1L5, DC1L21);


--DC1L24 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~18
DC1L24 = AMPP_FUNCTION(DC1_state[7], DC1_state[5]);


--H1_d_writedata[15] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[15]
H1_d_writedata[15] = AMPP_FUNCTION(CLOCK_50, H1L414, E1_data_out);


--H1_d_writedata[23] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[23]
H1_d_writedata[23] = AMPP_FUNCTION(CLOCK_50, H1L422, E1_data_out);


--H1_d_writedata[7] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[7]
H1_d_writedata[7] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[7], E1_data_out);


--J1L25 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[7]~88
J1L25 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[23] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[7]));


--H1_d_writedata[31] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[31]
H1_d_writedata[31] = AMPP_FUNCTION(CLOCK_50, H1L1167, CB1_q_b[31], E1_data_out, H1_D_iw[4]);


--J1L26 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[7]~89
J1L26 = J1_cpu_0_data_master_dbs_address[0] & (J1L25 & (H1_d_writedata[31]) # !J1L25 & H1_d_writedata[15]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L25);


--H1_d_writedata[14] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[14]
H1_d_writedata[14] = AMPP_FUNCTION(CLOCK_50, H1L413, E1_data_out);


--H1_d_writedata[22] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[22]
H1_d_writedata[22] = AMPP_FUNCTION(CLOCK_50, H1L421, E1_data_out);


--H1_d_writedata[6] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[6]
H1_d_writedata[6] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[6], E1_data_out);


--J1L23 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[6]~90
J1L23 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[22] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[6]));


--H1_d_writedata[30] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[30]
H1_d_writedata[30] = AMPP_FUNCTION(CLOCK_50, H1L1164, CB1_q_b[30], E1_data_out, H1_D_iw[4]);


--J1L24 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[6]~91
J1L24 = J1_cpu_0_data_master_dbs_address[0] & (J1L23 & (H1_d_writedata[30]) # !J1L23 & H1_d_writedata[14]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L23);


--H1_d_writedata[13] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[13]
H1_d_writedata[13] = AMPP_FUNCTION(CLOCK_50, H1L412, E1_data_out);


--H1_d_writedata[21] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[21]
H1_d_writedata[21] = AMPP_FUNCTION(CLOCK_50, H1L420, E1_data_out);


--H1_d_writedata[5] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[5]
H1_d_writedata[5] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[5], E1_data_out);


--J1L21 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[5]~92
J1L21 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[21] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[5]));


--H1_d_writedata[29] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[29]
H1_d_writedata[29] = AMPP_FUNCTION(CLOCK_50, H1L1161, CB1_q_b[29], E1_data_out, H1_D_iw[4]);


--J1L22 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[5]~93
J1L22 = J1_cpu_0_data_master_dbs_address[0] & (J1L21 & (H1_d_writedata[29]) # !J1L21 & H1_d_writedata[13]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L21);


--H1_d_writedata[12] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[12]
H1_d_writedata[12] = AMPP_FUNCTION(CLOCK_50, H1L411, E1_data_out);


--H1_d_writedata[20] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[20]
H1_d_writedata[20] = AMPP_FUNCTION(CLOCK_50, H1L419, E1_data_out);


--H1_d_writedata[4] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[4]
H1_d_writedata[4] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[4], E1_data_out);


--J1L19 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[4]~94
J1L19 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[20] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[4]));


--H1_d_writedata[28] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[28]
H1_d_writedata[28] = AMPP_FUNCTION(CLOCK_50, H1L1158, CB1_q_b[28], E1_data_out, H1_D_iw[4]);


--J1L20 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[4]~95
J1L20 = J1_cpu_0_data_master_dbs_address[0] & (J1L19 & (H1_d_writedata[28]) # !J1L19 & H1_d_writedata[12]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L19);


--H1_d_writedata[11] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[11]
H1_d_writedata[11] = AMPP_FUNCTION(CLOCK_50, H1L410, E1_data_out);


--H1_d_writedata[19] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[19]
H1_d_writedata[19] = AMPP_FUNCTION(CLOCK_50, H1L418, E1_data_out);


--H1_d_writedata[3] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[3]
H1_d_writedata[3] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[3], E1_data_out);


--J1L17 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[3]~96
J1L17 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[19] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[3]));


--H1_d_writedata[27] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[27]
H1_d_writedata[27] = AMPP_FUNCTION(CLOCK_50, H1L1155, CB1_q_b[27], E1_data_out, H1_D_iw[4]);


--J1L18 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[3]~97
J1L18 = J1_cpu_0_data_master_dbs_address[0] & (J1L17 & (H1_d_writedata[27]) # !J1L17 & H1_d_writedata[11]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L17);


--H1_d_writedata[10] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[10]
H1_d_writedata[10] = AMPP_FUNCTION(CLOCK_50, H1L409, E1_data_out);


--H1_d_writedata[18] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[18]
H1_d_writedata[18] = AMPP_FUNCTION(CLOCK_50, H1L417, E1_data_out);


--H1_d_writedata[2] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[2]
H1_d_writedata[2] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[2], E1_data_out);


--J1L15 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[2]~98
J1L15 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[18] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[2]));


--H1_d_writedata[26] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[26]
H1_d_writedata[26] = AMPP_FUNCTION(CLOCK_50, H1L1152, CB1_q_b[26], E1_data_out, H1_D_iw[4]);


--J1L16 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[2]~99
J1L16 = J1_cpu_0_data_master_dbs_address[0] & (J1L15 & (H1_d_writedata[26]) # !J1L15 & H1_d_writedata[10]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L15);


--H1_d_writedata[9] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[9]
H1_d_writedata[9] = AMPP_FUNCTION(CLOCK_50, H1L408, E1_data_out);


--H1_d_writedata[17] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[17]
H1_d_writedata[17] = AMPP_FUNCTION(CLOCK_50, H1L416, E1_data_out);


--H1_d_writedata[1] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[1]
H1_d_writedata[1] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[1], E1_data_out);


--J1L13 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[1]~100
J1L13 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[17] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[1]));


--H1_d_writedata[25] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[25]
H1_d_writedata[25] = AMPP_FUNCTION(CLOCK_50, H1L1149, CB1_q_b[25], E1_data_out, H1_D_iw[4]);


--J1L14 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[1]~101
J1L14 = J1_cpu_0_data_master_dbs_address[0] & (J1L13 & (H1_d_writedata[25]) # !J1L13 & H1_d_writedata[9]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L13);


--H1_d_writedata[8] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[8]
H1_d_writedata[8] = AMPP_FUNCTION(CLOCK_50, H1L407, E1_data_out);


--H1_d_writedata[16] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[16]
H1_d_writedata[16] = AMPP_FUNCTION(CLOCK_50, H1L415, E1_data_out);


--H1_d_writedata[0] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[0]
H1_d_writedata[0] = AMPP_FUNCTION(CLOCK_50, CB1_q_b[0], E1_data_out);


--J1L11 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[0]~102
J1L11 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1]) # !J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[16] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[0]));


--H1_d_writedata[24] is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[24]
H1_d_writedata[24] = AMPP_FUNCTION(CLOCK_50, H1L1146, CB1_q_b[24], E1_data_out, H1_D_iw[4]);


--J1L12 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_8[0]~103
J1L12 = J1_cpu_0_data_master_dbs_address[0] & (J1L11 & (H1_d_writedata[24]) # !J1L11 & H1_d_writedata[8]) # !J1_cpu_0_data_master_dbs_address[0] & (J1L11);


--DB1_q_a[0] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[0]_PORT_A_data_in = H1_d_writedata[0];
DB1_q_a[0]_PORT_A_data_in_reg = DFFE(DB1_q_a[0]_PORT_A_data_in, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[0]_PORT_B_address_reg = DFFE(DB1_q_a[0]_PORT_B_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_PORT_A_write_enable = L1L1;
DB1_q_a[0]_PORT_A_write_enable_reg = DFFE(DB1_q_a[0]_PORT_A_write_enable, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_PORT_A_byte_mask = M1L22;
DB1_q_a[0]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[0]_PORT_A_byte_mask, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = CLOCK_50;
DB1_q_a[0]_PORT_A_data_out = MEMORY(DB1_q_a[0]_PORT_A_data_in_reg, , DB1_q_a[0]_PORT_A_address_reg, DB1_q_a[0]_PORT_B_address_reg, DB1_q_a[0]_PORT_A_write_enable_reg, , DB1_q_a[0]_PORT_A_byte_mask_reg, , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0] = DB1_q_a[0]_PORT_A_data_out[0];


--EB1_q_a[0] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[0]_PORT_A_data_in = H1_d_writedata[0];
EB1_q_a[0]_PORT_A_data_in_reg = DFFE(EB1_q_a[0]_PORT_A_data_in, EB1_q_a[0]_clock_0, , , );
EB1_q_a[0]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[0]_PORT_A_address_reg = DFFE(EB1_q_a[0]_PORT_A_address, EB1_q_a[0]_clock_0, , , );
EB1_q_a[0]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[0]_PORT_B_address_reg = DFFE(EB1_q_a[0]_PORT_B_address, EB1_q_a[0]_clock_0, , , );
EB1_q_a[0]_PORT_A_write_enable = GND;
EB1_q_a[0]_PORT_A_write_enable_reg = DFFE(EB1_q_a[0]_PORT_A_write_enable, EB1_q_a[0]_clock_0, , , );
EB1_q_a[0]_PORT_A_byte_mask = P1L28;
EB1_q_a[0]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[0]_PORT_A_byte_mask, EB1_q_a[0]_clock_0, , , );
EB1_q_a[0]_clock_0 = CLOCK_50;
EB1_q_a[0]_PORT_A_data_out = MEMORY(EB1_q_a[0]_PORT_A_data_in_reg, , EB1_q_a[0]_PORT_A_address_reg, EB1_q_a[0]_PORT_B_address_reg, EB1_q_a[0]_PORT_A_write_enable_reg, , EB1_q_a[0]_PORT_A_byte_mask_reg, , EB1_q_a[0]_clock_0, , , , , );
EB1_q_a[0] = EB1_q_a[0]_PORT_A_data_out[0];


--H1L439 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3105
H1L439 = AMPP_FUNCTION(DB1_q_a[0], EB1_q_a[0], P1L14, M1L10);


--K1_dbs_8_reg_segment_0[0] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[0]
K1_dbs_8_reg_segment_0[0] = DFFEAS(W1_incoming_tri_state_bridge_0_data[0], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[0] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[0]
K1_dbs_16_reg_segment_0[0] = DFFEAS(VB1L1, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L440 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3106
H1L440 = AMPP_FUNCTION(H1L439, H1L510, K1_dbs_16_reg_segment_0[0], T1L17);


--DB1_q_a[1] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[1]_PORT_A_data_in = H1_d_writedata[1];
DB1_q_a[1]_PORT_A_data_in_reg = DFFE(DB1_q_a[1]_PORT_A_data_in, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[1]_PORT_A_address_reg = DFFE(DB1_q_a[1]_PORT_A_address, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[1]_PORT_B_address_reg = DFFE(DB1_q_a[1]_PORT_B_address, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1]_PORT_A_write_enable = L1L1;
DB1_q_a[1]_PORT_A_write_enable_reg = DFFE(DB1_q_a[1]_PORT_A_write_enable, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1]_PORT_A_byte_mask = M1L22;
DB1_q_a[1]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[1]_PORT_A_byte_mask, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1]_clock_0 = CLOCK_50;
DB1_q_a[1]_PORT_A_data_out = MEMORY(DB1_q_a[1]_PORT_A_data_in_reg, , DB1_q_a[1]_PORT_A_address_reg, DB1_q_a[1]_PORT_B_address_reg, DB1_q_a[1]_PORT_A_write_enable_reg, , DB1_q_a[1]_PORT_A_byte_mask_reg, , DB1_q_a[1]_clock_0, , , , , );
DB1_q_a[1] = DB1_q_a[1]_PORT_A_data_out[0];


--EB1_q_a[1] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[1]_PORT_A_data_in = H1_d_writedata[1];
EB1_q_a[1]_PORT_A_data_in_reg = DFFE(EB1_q_a[1]_PORT_A_data_in, EB1_q_a[1]_clock_0, , , );
EB1_q_a[1]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[1]_PORT_A_address_reg = DFFE(EB1_q_a[1]_PORT_A_address, EB1_q_a[1]_clock_0, , , );
EB1_q_a[1]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[1]_PORT_B_address_reg = DFFE(EB1_q_a[1]_PORT_B_address, EB1_q_a[1]_clock_0, , , );
EB1_q_a[1]_PORT_A_write_enable = GND;
EB1_q_a[1]_PORT_A_write_enable_reg = DFFE(EB1_q_a[1]_PORT_A_write_enable, EB1_q_a[1]_clock_0, , , );
EB1_q_a[1]_PORT_A_byte_mask = P1L28;
EB1_q_a[1]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[1]_PORT_A_byte_mask, EB1_q_a[1]_clock_0, , , );
EB1_q_a[1]_clock_0 = CLOCK_50;
EB1_q_a[1]_PORT_A_data_out = MEMORY(EB1_q_a[1]_PORT_A_data_in_reg, , EB1_q_a[1]_PORT_A_address_reg, EB1_q_a[1]_PORT_B_address_reg, EB1_q_a[1]_PORT_A_write_enable_reg, , EB1_q_a[1]_PORT_A_byte_mask_reg, , EB1_q_a[1]_clock_0, , , , , );
EB1_q_a[1] = EB1_q_a[1]_PORT_A_data_out[0];


--H1L441 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3107
H1L441 = AMPP_FUNCTION(DB1_q_a[1], EB1_q_a[1], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[1] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[1]
K1_dbs_16_reg_segment_0[1] = DFFEAS(VB1L2, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_0[1] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[1]
K1_dbs_8_reg_segment_0[1] = DFFEAS(W1_incoming_tri_state_bridge_0_data[1], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--H1L442 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3108
H1L442 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[1], K1_dbs_8_reg_segment_0[1], W1L34, T1L17);


--H1L443 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3109
H1L443 = AMPP_FUNCTION(H1L1171, H1L441, H1L442);


--DB1_q_a[2] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[2]_PORT_A_data_in = H1_d_writedata[2];
DB1_q_a[2]_PORT_A_data_in_reg = DFFE(DB1_q_a[2]_PORT_A_data_in, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[2]_PORT_A_address_reg = DFFE(DB1_q_a[2]_PORT_A_address, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[2]_PORT_B_address_reg = DFFE(DB1_q_a[2]_PORT_B_address, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_A_write_enable = L1L1;
DB1_q_a[2]_PORT_A_write_enable_reg = DFFE(DB1_q_a[2]_PORT_A_write_enable, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_PORT_A_byte_mask = M1L22;
DB1_q_a[2]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[2]_PORT_A_byte_mask, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_clock_0 = CLOCK_50;
DB1_q_a[2]_PORT_A_data_out = MEMORY(DB1_q_a[2]_PORT_A_data_in_reg, , DB1_q_a[2]_PORT_A_address_reg, DB1_q_a[2]_PORT_B_address_reg, DB1_q_a[2]_PORT_A_write_enable_reg, , DB1_q_a[2]_PORT_A_byte_mask_reg, , DB1_q_a[2]_clock_0, , , , , );
DB1_q_a[2] = DB1_q_a[2]_PORT_A_data_out[0];


--EB1_q_a[2] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[2]_PORT_A_data_in = H1_d_writedata[2];
EB1_q_a[2]_PORT_A_data_in_reg = DFFE(EB1_q_a[2]_PORT_A_data_in, EB1_q_a[2]_clock_0, , , );
EB1_q_a[2]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[2]_PORT_A_address_reg = DFFE(EB1_q_a[2]_PORT_A_address, EB1_q_a[2]_clock_0, , , );
EB1_q_a[2]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[2]_PORT_B_address_reg = DFFE(EB1_q_a[2]_PORT_B_address, EB1_q_a[2]_clock_0, , , );
EB1_q_a[2]_PORT_A_write_enable = GND;
EB1_q_a[2]_PORT_A_write_enable_reg = DFFE(EB1_q_a[2]_PORT_A_write_enable, EB1_q_a[2]_clock_0, , , );
EB1_q_a[2]_PORT_A_byte_mask = P1L28;
EB1_q_a[2]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[2]_PORT_A_byte_mask, EB1_q_a[2]_clock_0, , , );
EB1_q_a[2]_clock_0 = CLOCK_50;
EB1_q_a[2]_PORT_A_data_out = MEMORY(EB1_q_a[2]_PORT_A_data_in_reg, , EB1_q_a[2]_PORT_A_address_reg, EB1_q_a[2]_PORT_B_address_reg, EB1_q_a[2]_PORT_A_write_enable_reg, , EB1_q_a[2]_PORT_A_byte_mask_reg, , EB1_q_a[2]_clock_0, , , , , );
EB1_q_a[2] = EB1_q_a[2]_PORT_A_data_out[0];


--H1L444 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3110
H1L444 = AMPP_FUNCTION(DB1_q_a[2], EB1_q_a[2], P1L14, M1L10);


--K1_dbs_8_reg_segment_0[2] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[2]
K1_dbs_8_reg_segment_0[2] = DFFEAS(W1_incoming_tri_state_bridge_0_data[2], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[2] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[2]
K1_dbs_16_reg_segment_0[2] = DFFEAS(VB1L3, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L445 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3111
H1L445 = AMPP_FUNCTION(H1L444, H1L511, K1_dbs_16_reg_segment_0[2], T1L17);


--DB1_q_a[5] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[5]_PORT_A_data_in = H1_d_writedata[5];
DB1_q_a[5]_PORT_A_data_in_reg = DFFE(DB1_q_a[5]_PORT_A_data_in, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[5]_PORT_A_address_reg = DFFE(DB1_q_a[5]_PORT_A_address, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[5]_PORT_B_address_reg = DFFE(DB1_q_a[5]_PORT_B_address, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5]_PORT_A_write_enable = L1L1;
DB1_q_a[5]_PORT_A_write_enable_reg = DFFE(DB1_q_a[5]_PORT_A_write_enable, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5]_PORT_A_byte_mask = M1L22;
DB1_q_a[5]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[5]_PORT_A_byte_mask, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5]_clock_0 = CLOCK_50;
DB1_q_a[5]_PORT_A_data_out = MEMORY(DB1_q_a[5]_PORT_A_data_in_reg, , DB1_q_a[5]_PORT_A_address_reg, DB1_q_a[5]_PORT_B_address_reg, DB1_q_a[5]_PORT_A_write_enable_reg, , DB1_q_a[5]_PORT_A_byte_mask_reg, , DB1_q_a[5]_clock_0, , , , , );
DB1_q_a[5] = DB1_q_a[5]_PORT_A_data_out[0];


--EB1_q_a[5] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[5]_PORT_A_data_in = H1_d_writedata[5];
EB1_q_a[5]_PORT_A_data_in_reg = DFFE(EB1_q_a[5]_PORT_A_data_in, EB1_q_a[5]_clock_0, , , );
EB1_q_a[5]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[5]_PORT_A_address_reg = DFFE(EB1_q_a[5]_PORT_A_address, EB1_q_a[5]_clock_0, , , );
EB1_q_a[5]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[5]_PORT_B_address_reg = DFFE(EB1_q_a[5]_PORT_B_address, EB1_q_a[5]_clock_0, , , );
EB1_q_a[5]_PORT_A_write_enable = GND;
EB1_q_a[5]_PORT_A_write_enable_reg = DFFE(EB1_q_a[5]_PORT_A_write_enable, EB1_q_a[5]_clock_0, , , );
EB1_q_a[5]_PORT_A_byte_mask = P1L28;
EB1_q_a[5]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[5]_PORT_A_byte_mask, EB1_q_a[5]_clock_0, , , );
EB1_q_a[5]_clock_0 = CLOCK_50;
EB1_q_a[5]_PORT_A_data_out = MEMORY(EB1_q_a[5]_PORT_A_data_in_reg, , EB1_q_a[5]_PORT_A_address_reg, EB1_q_a[5]_PORT_B_address_reg, EB1_q_a[5]_PORT_A_write_enable_reg, , EB1_q_a[5]_PORT_A_byte_mask_reg, , EB1_q_a[5]_clock_0, , , , , );
EB1_q_a[5] = EB1_q_a[5]_PORT_A_data_out[0];


--H1L446 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3112
H1L446 = AMPP_FUNCTION(DB1_q_a[5], EB1_q_a[5], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[5] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[5]
K1_dbs_16_reg_segment_0[5] = DFFEAS(VB1L6, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_0[5] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[5]
K1_dbs_8_reg_segment_0[5] = DFFEAS(W1_incoming_tri_state_bridge_0_data[5], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--H1L447 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3113
H1L447 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[5], K1_dbs_8_reg_segment_0[5], W1L34, T1L17);


--H1L448 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3114
H1L448 = AMPP_FUNCTION(H1L1171, H1L446, H1L447);


--DB1_q_a[12] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[12]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[12]_PORT_A_data_in = H1_d_writedata[12];
DB1_q_a[12]_PORT_A_data_in_reg = DFFE(DB1_q_a[12]_PORT_A_data_in, DB1_q_a[12]_clock_0, , , );
DB1_q_a[12]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[12]_PORT_A_address_reg = DFFE(DB1_q_a[12]_PORT_A_address, DB1_q_a[12]_clock_0, , , );
DB1_q_a[12]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[12]_PORT_B_address_reg = DFFE(DB1_q_a[12]_PORT_B_address, DB1_q_a[12]_clock_0, , , );
DB1_q_a[12]_PORT_A_write_enable = L1L1;
DB1_q_a[12]_PORT_A_write_enable_reg = DFFE(DB1_q_a[12]_PORT_A_write_enable, DB1_q_a[12]_clock_0, , , );
DB1_q_a[12]_PORT_A_byte_mask = M1L23;
DB1_q_a[12]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[12]_PORT_A_byte_mask, DB1_q_a[12]_clock_0, , , );
DB1_q_a[12]_clock_0 = CLOCK_50;
DB1_q_a[12]_PORT_A_data_out = MEMORY(DB1_q_a[12]_PORT_A_data_in_reg, , DB1_q_a[12]_PORT_A_address_reg, DB1_q_a[12]_PORT_B_address_reg, DB1_q_a[12]_PORT_A_write_enable_reg, , DB1_q_a[12]_PORT_A_byte_mask_reg, , DB1_q_a[12]_clock_0, , , , , );
DB1_q_a[12] = DB1_q_a[12]_PORT_A_data_out[0];


--EB1_q_a[12] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[12]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[12]_PORT_A_data_in = H1_d_writedata[12];
EB1_q_a[12]_PORT_A_data_in_reg = DFFE(EB1_q_a[12]_PORT_A_data_in, EB1_q_a[12]_clock_0, , , );
EB1_q_a[12]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[12]_PORT_A_address_reg = DFFE(EB1_q_a[12]_PORT_A_address, EB1_q_a[12]_clock_0, , , );
EB1_q_a[12]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[12]_PORT_B_address_reg = DFFE(EB1_q_a[12]_PORT_B_address, EB1_q_a[12]_clock_0, , , );
EB1_q_a[12]_PORT_A_write_enable = GND;
EB1_q_a[12]_PORT_A_write_enable_reg = DFFE(EB1_q_a[12]_PORT_A_write_enable, EB1_q_a[12]_clock_0, , , );
EB1_q_a[12]_PORT_A_byte_mask = P1L29;
EB1_q_a[12]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[12]_PORT_A_byte_mask, EB1_q_a[12]_clock_0, , , );
EB1_q_a[12]_clock_0 = CLOCK_50;
EB1_q_a[12]_PORT_A_data_out = MEMORY(EB1_q_a[12]_PORT_A_data_in_reg, , EB1_q_a[12]_PORT_A_address_reg, EB1_q_a[12]_PORT_B_address_reg, EB1_q_a[12]_PORT_A_write_enable_reg, , EB1_q_a[12]_PORT_A_byte_mask_reg, , EB1_q_a[12]_clock_0, , , , , );
EB1_q_a[12] = EB1_q_a[12]_PORT_A_data_out[0];


--H1L449 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3115
H1L449 = AMPP_FUNCTION(DB1_q_a[12], EB1_q_a[12], P1L14, M1L10);


--K1_dbs_8_reg_segment_1[4] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[4]
K1_dbs_8_reg_segment_1[4] = DFFEAS(W1_incoming_tri_state_bridge_0_data[4], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[12] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[12]
K1_dbs_16_reg_segment_0[12] = DFFEAS(VB1L13, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L450 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3116
H1L450 = AMPP_FUNCTION(H1L449, H1L512, K1_dbs_16_reg_segment_0[12], T1L17);


--DB1_q_a[16] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[16]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[16]_PORT_A_data_in = H1_d_writedata[16];
DB1_q_a[16]_PORT_A_data_in_reg = DFFE(DB1_q_a[16]_PORT_A_data_in, DB1_q_a[16]_clock_0, , , );
DB1_q_a[16]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[16]_PORT_A_address_reg = DFFE(DB1_q_a[16]_PORT_A_address, DB1_q_a[16]_clock_0, , , );
DB1_q_a[16]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[16]_PORT_B_address_reg = DFFE(DB1_q_a[16]_PORT_B_address, DB1_q_a[16]_clock_0, , , );
DB1_q_a[16]_PORT_A_write_enable = L1L1;
DB1_q_a[16]_PORT_A_write_enable_reg = DFFE(DB1_q_a[16]_PORT_A_write_enable, DB1_q_a[16]_clock_0, , , );
DB1_q_a[16]_PORT_A_byte_mask = M1L24;
DB1_q_a[16]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[16]_PORT_A_byte_mask, DB1_q_a[16]_clock_0, , , );
DB1_q_a[16]_clock_0 = CLOCK_50;
DB1_q_a[16]_PORT_A_data_out = MEMORY(DB1_q_a[16]_PORT_A_data_in_reg, , DB1_q_a[16]_PORT_A_address_reg, DB1_q_a[16]_PORT_B_address_reg, DB1_q_a[16]_PORT_A_write_enable_reg, , DB1_q_a[16]_PORT_A_byte_mask_reg, , DB1_q_a[16]_clock_0, , , , , );
DB1_q_a[16] = DB1_q_a[16]_PORT_A_data_out[0];


--EB1_q_a[16] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[16]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[16]_PORT_A_data_in = H1_d_writedata[16];
EB1_q_a[16]_PORT_A_data_in_reg = DFFE(EB1_q_a[16]_PORT_A_data_in, EB1_q_a[16]_clock_0, , , );
EB1_q_a[16]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[16]_PORT_A_address_reg = DFFE(EB1_q_a[16]_PORT_A_address, EB1_q_a[16]_clock_0, , , );
EB1_q_a[16]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[16]_PORT_B_address_reg = DFFE(EB1_q_a[16]_PORT_B_address, EB1_q_a[16]_clock_0, , , );
EB1_q_a[16]_PORT_A_write_enable = GND;
EB1_q_a[16]_PORT_A_write_enable_reg = DFFE(EB1_q_a[16]_PORT_A_write_enable, EB1_q_a[16]_clock_0, , , );
EB1_q_a[16]_PORT_A_byte_mask = P1L30;
EB1_q_a[16]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[16]_PORT_A_byte_mask, EB1_q_a[16]_clock_0, , , );
EB1_q_a[16]_clock_0 = CLOCK_50;
EB1_q_a[16]_PORT_A_data_out = MEMORY(EB1_q_a[16]_PORT_A_data_in_reg, , EB1_q_a[16]_PORT_A_address_reg, EB1_q_a[16]_PORT_B_address_reg, EB1_q_a[16]_PORT_A_write_enable_reg, , EB1_q_a[16]_PORT_A_byte_mask_reg, , EB1_q_a[16]_clock_0, , , , , );
EB1_q_a[16] = EB1_q_a[16]_PORT_A_data_out[0];


--H1L451 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3117
H1L451 = AMPP_FUNCTION(DB1_q_a[16], EB1_q_a[16], P1L14, M1L10);


--TB1_ram_block1a16 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a16
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a16_PORT_A_data_in = J1L27;
TB1_ram_block1a16_PORT_A_data_in_reg = DFFE(TB1_ram_block1a16_PORT_A_data_in, TB1_ram_block1a16_clock_0, , , TB1_ram_block1a16_clock_enable_0);
TB1_ram_block1a16_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a16_PORT_A_address_reg = DFFE(TB1_ram_block1a16_PORT_A_address, TB1_ram_block1a16_clock_0, , , TB1_ram_block1a16_clock_enable_0);
TB1_ram_block1a16_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a16_PORT_B_address_reg = DFFE(TB1_ram_block1a16_PORT_B_address, TB1_ram_block1a16_clock_0, , , TB1_ram_block1a16_clock_enable_0);
TB1_ram_block1a16_PORT_A_write_enable = UB1L3;
TB1_ram_block1a16_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a16_PORT_A_write_enable, TB1_ram_block1a16_clock_0, , , TB1_ram_block1a16_clock_enable_0);
TB1_ram_block1a16_PORT_A_byte_mask = T1L52;
TB1_ram_block1a16_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a16_PORT_A_byte_mask, TB1_ram_block1a16_clock_0, , , TB1_ram_block1a16_clock_enable_0);
TB1_ram_block1a16_clock_0 = CLOCK_50;
TB1_ram_block1a16_clock_enable_0 = !T1L38;
TB1_ram_block1a16_PORT_A_data_out = MEMORY(TB1_ram_block1a16_PORT_A_data_in_reg, , TB1_ram_block1a16_PORT_A_address_reg, TB1_ram_block1a16_PORT_B_address_reg, TB1_ram_block1a16_PORT_A_write_enable_reg, , TB1_ram_block1a16_PORT_A_byte_mask_reg, , TB1_ram_block1a16_clock_0, , TB1_ram_block1a16_clock_enable_0, , , );
TB1_ram_block1a16 = TB1_ram_block1a16_PORT_A_data_out[0];


--TB1_ram_block1a0 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a0
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a0_PORT_A_data_in = J1L27;
TB1_ram_block1a0_PORT_A_data_in_reg = DFFE(TB1_ram_block1a0_PORT_A_data_in, TB1_ram_block1a0_clock_0, , , TB1_ram_block1a0_clock_enable_0);
TB1_ram_block1a0_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a0_PORT_A_address_reg = DFFE(TB1_ram_block1a0_PORT_A_address, TB1_ram_block1a0_clock_0, , , TB1_ram_block1a0_clock_enable_0);
TB1_ram_block1a0_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a0_PORT_B_address_reg = DFFE(TB1_ram_block1a0_PORT_B_address, TB1_ram_block1a0_clock_0, , , TB1_ram_block1a0_clock_enable_0);
TB1_ram_block1a0_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a0_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a0_PORT_A_write_enable, TB1_ram_block1a0_clock_0, , , TB1_ram_block1a0_clock_enable_0);
TB1_ram_block1a0_PORT_A_byte_mask = T1L52;
TB1_ram_block1a0_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a0_PORT_A_byte_mask, TB1_ram_block1a0_clock_0, , , TB1_ram_block1a0_clock_enable_0);
TB1_ram_block1a0_clock_0 = CLOCK_50;
TB1_ram_block1a0_clock_enable_0 = T1L38;
TB1_ram_block1a0_PORT_A_data_out = MEMORY(TB1_ram_block1a0_PORT_A_data_in_reg, , TB1_ram_block1a0_PORT_A_address_reg, TB1_ram_block1a0_PORT_B_address_reg, TB1_ram_block1a0_PORT_A_write_enable_reg, , TB1_ram_block1a0_PORT_A_byte_mask_reg, , TB1_ram_block1a0_clock_0, , TB1_ram_block1a0_clock_enable_0, , , );
TB1_ram_block1a0 = TB1_ram_block1a0_PORT_A_data_out[0];


--TB1_address_reg_a[0] is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|address_reg_a[0]
TB1_address_reg_a[0] = DFFEAS(T1L39, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--VB1L1 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[0]~432
VB1L1 = TB1_address_reg_a[0] & TB1_ram_block1a16 # !TB1_address_reg_a[0] & (TB1_ram_block1a0);


--K1_dbs_8_reg_segment_2[0] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[0]
K1_dbs_8_reg_segment_2[0] = DFFEAS(W1_incoming_tri_state_bridge_0_data[0], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--H1L452 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3118
H1L452 = AMPP_FUNCTION(VB1L1, K1_dbs_8_reg_segment_2[0], W1L34, T1L17);


--H1L453 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3119
H1L453 = AMPP_FUNCTION(H1L1171, H1L451, H1L452);


--DB1_q_a[15] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[15]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[15]_PORT_A_data_in = H1_d_writedata[15];
DB1_q_a[15]_PORT_A_data_in_reg = DFFE(DB1_q_a[15]_PORT_A_data_in, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[15]_PORT_A_address_reg = DFFE(DB1_q_a[15]_PORT_A_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[15]_PORT_B_address_reg = DFFE(DB1_q_a[15]_PORT_B_address, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_A_write_enable = L1L1;
DB1_q_a[15]_PORT_A_write_enable_reg = DFFE(DB1_q_a[15]_PORT_A_write_enable, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_PORT_A_byte_mask = M1L23;
DB1_q_a[15]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[15]_PORT_A_byte_mask, DB1_q_a[15]_clock_0, , , );
DB1_q_a[15]_clock_0 = CLOCK_50;
DB1_q_a[15]_PORT_A_data_out = MEMORY(DB1_q_a[15]_PORT_A_data_in_reg, , DB1_q_a[15]_PORT_A_address_reg, DB1_q_a[15]_PORT_B_address_reg, DB1_q_a[15]_PORT_A_write_enable_reg, , DB1_q_a[15]_PORT_A_byte_mask_reg, , DB1_q_a[15]_clock_0, , , , , );
DB1_q_a[15] = DB1_q_a[15]_PORT_A_data_out[0];


--EB1_q_a[15] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[15]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[15]_PORT_A_data_in = H1_d_writedata[15];
EB1_q_a[15]_PORT_A_data_in_reg = DFFE(EB1_q_a[15]_PORT_A_data_in, EB1_q_a[15]_clock_0, , , );
EB1_q_a[15]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[15]_PORT_A_address_reg = DFFE(EB1_q_a[15]_PORT_A_address, EB1_q_a[15]_clock_0, , , );
EB1_q_a[15]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[15]_PORT_B_address_reg = DFFE(EB1_q_a[15]_PORT_B_address, EB1_q_a[15]_clock_0, , , );
EB1_q_a[15]_PORT_A_write_enable = GND;
EB1_q_a[15]_PORT_A_write_enable_reg = DFFE(EB1_q_a[15]_PORT_A_write_enable, EB1_q_a[15]_clock_0, , , );
EB1_q_a[15]_PORT_A_byte_mask = P1L29;
EB1_q_a[15]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[15]_PORT_A_byte_mask, EB1_q_a[15]_clock_0, , , );
EB1_q_a[15]_clock_0 = CLOCK_50;
EB1_q_a[15]_PORT_A_data_out = MEMORY(EB1_q_a[15]_PORT_A_data_in_reg, , EB1_q_a[15]_PORT_A_address_reg, EB1_q_a[15]_PORT_B_address_reg, EB1_q_a[15]_PORT_A_write_enable_reg, , EB1_q_a[15]_PORT_A_byte_mask_reg, , EB1_q_a[15]_clock_0, , , , , );
EB1_q_a[15] = EB1_q_a[15]_PORT_A_data_out[0];


--H1L454 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3120
H1L454 = AMPP_FUNCTION(DB1_q_a[15], EB1_q_a[15], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[15] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[15]
K1_dbs_16_reg_segment_0[15] = DFFEAS(VB1L16, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_1[7] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[7]
K1_dbs_8_reg_segment_1[7] = DFFEAS(W1_incoming_tri_state_bridge_0_data[7], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--H1L455 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3121
H1L455 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[15], K1_dbs_8_reg_segment_1[7], W1L34, T1L17);


--H1L456 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3122
H1L456 = AMPP_FUNCTION(H1L1171, H1L454, H1L455);


--DB1_q_a[14] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[14]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[14]_PORT_A_data_in = H1_d_writedata[14];
DB1_q_a[14]_PORT_A_data_in_reg = DFFE(DB1_q_a[14]_PORT_A_data_in, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[14]_PORT_A_address_reg = DFFE(DB1_q_a[14]_PORT_A_address, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[14]_PORT_B_address_reg = DFFE(DB1_q_a[14]_PORT_B_address, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_A_write_enable = L1L1;
DB1_q_a[14]_PORT_A_write_enable_reg = DFFE(DB1_q_a[14]_PORT_A_write_enable, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_PORT_A_byte_mask = M1L23;
DB1_q_a[14]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[14]_PORT_A_byte_mask, DB1_q_a[14]_clock_0, , , );
DB1_q_a[14]_clock_0 = CLOCK_50;
DB1_q_a[14]_PORT_A_data_out = MEMORY(DB1_q_a[14]_PORT_A_data_in_reg, , DB1_q_a[14]_PORT_A_address_reg, DB1_q_a[14]_PORT_B_address_reg, DB1_q_a[14]_PORT_A_write_enable_reg, , DB1_q_a[14]_PORT_A_byte_mask_reg, , DB1_q_a[14]_clock_0, , , , , );
DB1_q_a[14] = DB1_q_a[14]_PORT_A_data_out[0];


--EB1_q_a[14] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[14]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[14]_PORT_A_data_in = H1_d_writedata[14];
EB1_q_a[14]_PORT_A_data_in_reg = DFFE(EB1_q_a[14]_PORT_A_data_in, EB1_q_a[14]_clock_0, , , );
EB1_q_a[14]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[14]_PORT_A_address_reg = DFFE(EB1_q_a[14]_PORT_A_address, EB1_q_a[14]_clock_0, , , );
EB1_q_a[14]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[14]_PORT_B_address_reg = DFFE(EB1_q_a[14]_PORT_B_address, EB1_q_a[14]_clock_0, , , );
EB1_q_a[14]_PORT_A_write_enable = GND;
EB1_q_a[14]_PORT_A_write_enable_reg = DFFE(EB1_q_a[14]_PORT_A_write_enable, EB1_q_a[14]_clock_0, , , );
EB1_q_a[14]_PORT_A_byte_mask = P1L29;
EB1_q_a[14]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[14]_PORT_A_byte_mask, EB1_q_a[14]_clock_0, , , );
EB1_q_a[14]_clock_0 = CLOCK_50;
EB1_q_a[14]_PORT_A_data_out = MEMORY(EB1_q_a[14]_PORT_A_data_in_reg, , EB1_q_a[14]_PORT_A_address_reg, EB1_q_a[14]_PORT_B_address_reg, EB1_q_a[14]_PORT_A_write_enable_reg, , EB1_q_a[14]_PORT_A_byte_mask_reg, , EB1_q_a[14]_clock_0, , , , , );
EB1_q_a[14] = EB1_q_a[14]_PORT_A_data_out[0];


--H1L457 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3123
H1L457 = AMPP_FUNCTION(DB1_q_a[14], EB1_q_a[14], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[14] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[14]
K1_dbs_16_reg_segment_0[14] = DFFEAS(VB1L15, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_1[6] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[6]
K1_dbs_8_reg_segment_1[6] = DFFEAS(W1_incoming_tri_state_bridge_0_data[6], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--H1L458 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3124
H1L458 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[14], K1_dbs_8_reg_segment_1[6], W1L34, T1L17);


--H1L459 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3125
H1L459 = AMPP_FUNCTION(H1L1171, H1L457, H1L458);


--DB1_q_a[13] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[13]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[13]_PORT_A_data_in = H1_d_writedata[13];
DB1_q_a[13]_PORT_A_data_in_reg = DFFE(DB1_q_a[13]_PORT_A_data_in, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[13]_PORT_A_address_reg = DFFE(DB1_q_a[13]_PORT_A_address, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[13]_PORT_B_address_reg = DFFE(DB1_q_a[13]_PORT_B_address, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_A_write_enable = L1L1;
DB1_q_a[13]_PORT_A_write_enable_reg = DFFE(DB1_q_a[13]_PORT_A_write_enable, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_PORT_A_byte_mask = M1L23;
DB1_q_a[13]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[13]_PORT_A_byte_mask, DB1_q_a[13]_clock_0, , , );
DB1_q_a[13]_clock_0 = CLOCK_50;
DB1_q_a[13]_PORT_A_data_out = MEMORY(DB1_q_a[13]_PORT_A_data_in_reg, , DB1_q_a[13]_PORT_A_address_reg, DB1_q_a[13]_PORT_B_address_reg, DB1_q_a[13]_PORT_A_write_enable_reg, , DB1_q_a[13]_PORT_A_byte_mask_reg, , DB1_q_a[13]_clock_0, , , , , );
DB1_q_a[13] = DB1_q_a[13]_PORT_A_data_out[0];


--EB1_q_a[13] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[13]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[13]_PORT_A_data_in = H1_d_writedata[13];
EB1_q_a[13]_PORT_A_data_in_reg = DFFE(EB1_q_a[13]_PORT_A_data_in, EB1_q_a[13]_clock_0, , , );
EB1_q_a[13]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[13]_PORT_A_address_reg = DFFE(EB1_q_a[13]_PORT_A_address, EB1_q_a[13]_clock_0, , , );
EB1_q_a[13]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[13]_PORT_B_address_reg = DFFE(EB1_q_a[13]_PORT_B_address, EB1_q_a[13]_clock_0, , , );
EB1_q_a[13]_PORT_A_write_enable = GND;
EB1_q_a[13]_PORT_A_write_enable_reg = DFFE(EB1_q_a[13]_PORT_A_write_enable, EB1_q_a[13]_clock_0, , , );
EB1_q_a[13]_PORT_A_byte_mask = P1L29;
EB1_q_a[13]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[13]_PORT_A_byte_mask, EB1_q_a[13]_clock_0, , , );
EB1_q_a[13]_clock_0 = CLOCK_50;
EB1_q_a[13]_PORT_A_data_out = MEMORY(EB1_q_a[13]_PORT_A_data_in_reg, , EB1_q_a[13]_PORT_A_address_reg, EB1_q_a[13]_PORT_B_address_reg, EB1_q_a[13]_PORT_A_write_enable_reg, , EB1_q_a[13]_PORT_A_byte_mask_reg, , EB1_q_a[13]_clock_0, , , , , );
EB1_q_a[13] = EB1_q_a[13]_PORT_A_data_out[0];


--H1L460 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3126
H1L460 = AMPP_FUNCTION(DB1_q_a[13], EB1_q_a[13], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[13] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[13]
K1_dbs_16_reg_segment_0[13] = DFFEAS(VB1L14, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_1[5] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[5]
K1_dbs_8_reg_segment_1[5] = DFFEAS(W1_incoming_tri_state_bridge_0_data[5], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--H1L461 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3127
H1L461 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[13], K1_dbs_8_reg_segment_1[5], W1L34, T1L17);


--H1L462 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3128
H1L462 = AMPP_FUNCTION(H1L1171, H1L460, H1L461);


--DB1_q_a[11] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[11]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[11]_PORT_A_data_in = H1_d_writedata[11];
DB1_q_a[11]_PORT_A_data_in_reg = DFFE(DB1_q_a[11]_PORT_A_data_in, DB1_q_a[11]_clock_0, , , );
DB1_q_a[11]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[11]_PORT_A_address_reg = DFFE(DB1_q_a[11]_PORT_A_address, DB1_q_a[11]_clock_0, , , );
DB1_q_a[11]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[11]_PORT_B_address_reg = DFFE(DB1_q_a[11]_PORT_B_address, DB1_q_a[11]_clock_0, , , );
DB1_q_a[11]_PORT_A_write_enable = L1L1;
DB1_q_a[11]_PORT_A_write_enable_reg = DFFE(DB1_q_a[11]_PORT_A_write_enable, DB1_q_a[11]_clock_0, , , );
DB1_q_a[11]_PORT_A_byte_mask = M1L23;
DB1_q_a[11]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[11]_PORT_A_byte_mask, DB1_q_a[11]_clock_0, , , );
DB1_q_a[11]_clock_0 = CLOCK_50;
DB1_q_a[11]_PORT_A_data_out = MEMORY(DB1_q_a[11]_PORT_A_data_in_reg, , DB1_q_a[11]_PORT_A_address_reg, DB1_q_a[11]_PORT_B_address_reg, DB1_q_a[11]_PORT_A_write_enable_reg, , DB1_q_a[11]_PORT_A_byte_mask_reg, , DB1_q_a[11]_clock_0, , , , , );
DB1_q_a[11] = DB1_q_a[11]_PORT_A_data_out[0];


--EB1_q_a[11] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[11]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[11]_PORT_A_data_in = H1_d_writedata[11];
EB1_q_a[11]_PORT_A_data_in_reg = DFFE(EB1_q_a[11]_PORT_A_data_in, EB1_q_a[11]_clock_0, , , );
EB1_q_a[11]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[11]_PORT_A_address_reg = DFFE(EB1_q_a[11]_PORT_A_address, EB1_q_a[11]_clock_0, , , );
EB1_q_a[11]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[11]_PORT_B_address_reg = DFFE(EB1_q_a[11]_PORT_B_address, EB1_q_a[11]_clock_0, , , );
EB1_q_a[11]_PORT_A_write_enable = GND;
EB1_q_a[11]_PORT_A_write_enable_reg = DFFE(EB1_q_a[11]_PORT_A_write_enable, EB1_q_a[11]_clock_0, , , );
EB1_q_a[11]_PORT_A_byte_mask = P1L29;
EB1_q_a[11]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[11]_PORT_A_byte_mask, EB1_q_a[11]_clock_0, , , );
EB1_q_a[11]_clock_0 = CLOCK_50;
EB1_q_a[11]_PORT_A_data_out = MEMORY(EB1_q_a[11]_PORT_A_data_in_reg, , EB1_q_a[11]_PORT_A_address_reg, EB1_q_a[11]_PORT_B_address_reg, EB1_q_a[11]_PORT_A_write_enable_reg, , EB1_q_a[11]_PORT_A_byte_mask_reg, , EB1_q_a[11]_clock_0, , , , , );
EB1_q_a[11] = EB1_q_a[11]_PORT_A_data_out[0];


--H1L463 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3129
H1L463 = AMPP_FUNCTION(DB1_q_a[11], EB1_q_a[11], P1L14, M1L10);


--K1_dbs_16_reg_segment_0[11] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[11]
K1_dbs_16_reg_segment_0[11] = DFFEAS(VB1L12, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--K1_dbs_8_reg_segment_1[3] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[3]
K1_dbs_8_reg_segment_1[3] = DFFEAS(W1_incoming_tri_state_bridge_0_data[3], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--H1L464 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3130
H1L464 = AMPP_FUNCTION(K1_dbs_16_reg_segment_0[11], K1_dbs_8_reg_segment_1[3], W1L34, T1L17);


--H1L465 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3131
H1L465 = AMPP_FUNCTION(H1L1171, H1L463, H1L464);


--H1_R_wr_dst_reg is DE2_Board:inst|cpu_0:the_cpu_0|R_wr_dst_reg
H1_R_wr_dst_reg = AMPP_FUNCTION(CLOCK_50, H1L98, E1_data_out);


--H1_W_rf_wren_a is DE2_Board:inst|cpu_0:the_cpu_0|W_rf_wren_a
H1_W_rf_wren_a = AMPP_FUNCTION(H1_W_valid, H1_R_wr_dst_reg, E1_data_out);


--H1L1106 is DE2_Board:inst|cpu_0:the_cpu_0|comb~5
H1L1106 = AMPP_FUNCTION(H1_R_ctrl_ld, H1_W_valid);


--H1_R_dst_regnum[0] is DE2_Board:inst|cpu_0:the_cpu_0|R_dst_regnum[0]
H1_R_dst_regnum[0] = AMPP_FUNCTION(CLOCK_50, H1L51, E1_data_out);


--H1_D_iw[27] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[27]
H1_D_iw[27] = AMPP_FUNCTION(CLOCK_50, H1L501, E1_data_out, H1_F_valid);


--H1L1107 is DE2_Board:inst|cpu_0:the_cpu_0|comb~328
H1L1107 = AMPP_FUNCTION(H1_R_dst_regnum[0], H1_D_iw[27], H1_W_rf_wren_a);


--H1_R_dst_regnum[1] is DE2_Board:inst|cpu_0:the_cpu_0|R_dst_regnum[1]
H1_R_dst_regnum[1] = AMPP_FUNCTION(CLOCK_50, H1L54, E1_data_out);


--H1_D_iw[28] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[28]
H1_D_iw[28] = AMPP_FUNCTION(CLOCK_50, H1L503, E1_data_out, H1_F_valid);


--H1L1108 is DE2_Board:inst|cpu_0:the_cpu_0|comb~329
H1L1108 = AMPP_FUNCTION(H1_R_dst_regnum[1], H1_D_iw[28], H1_W_rf_wren_a);


--H1_R_dst_regnum[2] is DE2_Board:inst|cpu_0:the_cpu_0|R_dst_regnum[2]
H1_R_dst_regnum[2] = AMPP_FUNCTION(CLOCK_50, H1L56, E1_data_out);


--H1_D_iw[29] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[29]
H1_D_iw[29] = AMPP_FUNCTION(CLOCK_50, H1L505, E1_data_out, H1_F_valid);


--H1L1109 is DE2_Board:inst|cpu_0:the_cpu_0|comb~330
H1L1109 = AMPP_FUNCTION(H1_R_dst_regnum[2], H1_D_iw[29], H1_W_rf_wren_a);


--H1_R_dst_regnum[3] is DE2_Board:inst|cpu_0:the_cpu_0|R_dst_regnum[3]
H1_R_dst_regnum[3] = AMPP_FUNCTION(CLOCK_50, H1L57, E1_data_out);


--H1_D_iw[30] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[30]
H1_D_iw[30] = AMPP_FUNCTION(CLOCK_50, H1L507, E1_data_out, H1_F_valid);


--H1L1110 is DE2_Board:inst|cpu_0:the_cpu_0|comb~331
H1L1110 = AMPP_FUNCTION(H1_R_dst_regnum[3], H1_D_iw[30], H1_W_rf_wren_a);


--H1_R_dst_regnum[4] is DE2_Board:inst|cpu_0:the_cpu_0|R_dst_regnum[4]
H1_R_dst_regnum[4] = AMPP_FUNCTION(CLOCK_50, H1L59, E1_data_out);


--H1_D_iw[31] is DE2_Board:inst|cpu_0:the_cpu_0|D_iw[31]
H1_D_iw[31] = AMPP_FUNCTION(CLOCK_50, H1L509, E1_data_out, H1_F_valid);


--H1L1111 is DE2_Board:inst|cpu_0:the_cpu_0|comb~332
H1L1111 = AMPP_FUNCTION(H1_R_dst_regnum[4], H1_D_iw[31], H1_W_rf_wren_a);


--H1_av_ld_byte2_data[6] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[6]
H1_av_ld_byte2_data[6] = AMPP_FUNCTION(CLOCK_50, H1L1057, H1_av_ld_byte3_data[6], E1_data_out, !H1L1103);


--DB1_q_a[21] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[21]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[21]_PORT_A_data_in = H1_d_writedata[21];
DB1_q_a[21]_PORT_A_data_in_reg = DFFE(DB1_q_a[21]_PORT_A_data_in, DB1_q_a[21]_clock_0, , , );
DB1_q_a[21]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[21]_PORT_A_address_reg = DFFE(DB1_q_a[21]_PORT_A_address, DB1_q_a[21]_clock_0, , , );
DB1_q_a[21]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[21]_PORT_B_address_reg = DFFE(DB1_q_a[21]_PORT_B_address, DB1_q_a[21]_clock_0, , , );
DB1_q_a[21]_PORT_A_write_enable = L1L1;
DB1_q_a[21]_PORT_A_write_enable_reg = DFFE(DB1_q_a[21]_PORT_A_write_enable, DB1_q_a[21]_clock_0, , , );
DB1_q_a[21]_PORT_A_byte_mask = M1L24;
DB1_q_a[21]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[21]_PORT_A_byte_mask, DB1_q_a[21]_clock_0, , , );
DB1_q_a[21]_clock_0 = CLOCK_50;
DB1_q_a[21]_PORT_A_data_out = MEMORY(DB1_q_a[21]_PORT_A_data_in_reg, , DB1_q_a[21]_PORT_A_address_reg, DB1_q_a[21]_PORT_B_address_reg, DB1_q_a[21]_PORT_A_write_enable_reg, , DB1_q_a[21]_PORT_A_byte_mask_reg, , DB1_q_a[21]_clock_0, , , , , );
DB1_q_a[21] = DB1_q_a[21]_PORT_A_data_out[0];


--EB1_q_a[21] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[21]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[21]_PORT_A_data_in = H1_d_writedata[21];
EB1_q_a[21]_PORT_A_data_in_reg = DFFE(EB1_q_a[21]_PORT_A_data_in, EB1_q_a[21]_clock_0, , , );
EB1_q_a[21]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[21]_PORT_A_address_reg = DFFE(EB1_q_a[21]_PORT_A_address, EB1_q_a[21]_clock_0, , , );
EB1_q_a[21]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[21]_PORT_B_address_reg = DFFE(EB1_q_a[21]_PORT_B_address, EB1_q_a[21]_clock_0, , , );
EB1_q_a[21]_PORT_A_write_enable = GND;
EB1_q_a[21]_PORT_A_write_enable_reg = DFFE(EB1_q_a[21]_PORT_A_write_enable, EB1_q_a[21]_clock_0, , , );
EB1_q_a[21]_PORT_A_byte_mask = P1L30;
EB1_q_a[21]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[21]_PORT_A_byte_mask, EB1_q_a[21]_clock_0, , , );
EB1_q_a[21]_clock_0 = CLOCK_50;
EB1_q_a[21]_PORT_A_data_out = MEMORY(EB1_q_a[21]_PORT_A_data_in_reg, , EB1_q_a[21]_PORT_A_address_reg, EB1_q_a[21]_PORT_B_address_reg, EB1_q_a[21]_PORT_A_write_enable_reg, , EB1_q_a[21]_PORT_A_byte_mask_reg, , EB1_q_a[21]_clock_0, , , , , );
EB1_q_a[21] = EB1_q_a[21]_PORT_A_data_out[0];


--H1L466 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3132
H1L466 = AMPP_FUNCTION(DB1_q_a[21], EB1_q_a[21], P1L14, M1L10);


--TB1_ram_block1a21 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a21
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a21_PORT_A_data_in = J1L32;
TB1_ram_block1a21_PORT_A_data_in_reg = DFFE(TB1_ram_block1a21_PORT_A_data_in, TB1_ram_block1a21_clock_0, , , TB1_ram_block1a21_clock_enable_0);
TB1_ram_block1a21_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a21_PORT_A_address_reg = DFFE(TB1_ram_block1a21_PORT_A_address, TB1_ram_block1a21_clock_0, , , TB1_ram_block1a21_clock_enable_0);
TB1_ram_block1a21_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a21_PORT_B_address_reg = DFFE(TB1_ram_block1a21_PORT_B_address, TB1_ram_block1a21_clock_0, , , TB1_ram_block1a21_clock_enable_0);
TB1_ram_block1a21_PORT_A_write_enable = UB1L3;
TB1_ram_block1a21_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a21_PORT_A_write_enable, TB1_ram_block1a21_clock_0, , , TB1_ram_block1a21_clock_enable_0);
TB1_ram_block1a21_PORT_A_byte_mask = T1L52;
TB1_ram_block1a21_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a21_PORT_A_byte_mask, TB1_ram_block1a21_clock_0, , , TB1_ram_block1a21_clock_enable_0);
TB1_ram_block1a21_clock_0 = CLOCK_50;
TB1_ram_block1a21_clock_enable_0 = !T1L38;
TB1_ram_block1a21_PORT_A_data_out = MEMORY(TB1_ram_block1a21_PORT_A_data_in_reg, , TB1_ram_block1a21_PORT_A_address_reg, TB1_ram_block1a21_PORT_B_address_reg, TB1_ram_block1a21_PORT_A_write_enable_reg, , TB1_ram_block1a21_PORT_A_byte_mask_reg, , TB1_ram_block1a21_clock_0, , TB1_ram_block1a21_clock_enable_0, , , );
TB1_ram_block1a21 = TB1_ram_block1a21_PORT_A_data_out[0];


--TB1_ram_block1a5 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a5
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a5_PORT_A_data_in = J1L32;
TB1_ram_block1a5_PORT_A_data_in_reg = DFFE(TB1_ram_block1a5_PORT_A_data_in, TB1_ram_block1a5_clock_0, , , TB1_ram_block1a5_clock_enable_0);
TB1_ram_block1a5_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a5_PORT_A_address_reg = DFFE(TB1_ram_block1a5_PORT_A_address, TB1_ram_block1a5_clock_0, , , TB1_ram_block1a5_clock_enable_0);
TB1_ram_block1a5_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a5_PORT_B_address_reg = DFFE(TB1_ram_block1a5_PORT_B_address, TB1_ram_block1a5_clock_0, , , TB1_ram_block1a5_clock_enable_0);
TB1_ram_block1a5_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a5_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a5_PORT_A_write_enable, TB1_ram_block1a5_clock_0, , , TB1_ram_block1a5_clock_enable_0);
TB1_ram_block1a5_PORT_A_byte_mask = T1L52;
TB1_ram_block1a5_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a5_PORT_A_byte_mask, TB1_ram_block1a5_clock_0, , , TB1_ram_block1a5_clock_enable_0);
TB1_ram_block1a5_clock_0 = CLOCK_50;
TB1_ram_block1a5_clock_enable_0 = T1L38;
TB1_ram_block1a5_PORT_A_data_out = MEMORY(TB1_ram_block1a5_PORT_A_data_in_reg, , TB1_ram_block1a5_PORT_A_address_reg, TB1_ram_block1a5_PORT_B_address_reg, TB1_ram_block1a5_PORT_A_write_enable_reg, , TB1_ram_block1a5_PORT_A_byte_mask_reg, , TB1_ram_block1a5_clock_0, , TB1_ram_block1a5_clock_enable_0, , , );
TB1_ram_block1a5 = TB1_ram_block1a5_PORT_A_data_out[0];


--VB1L6 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[5]~433
VB1L6 = TB1_address_reg_a[0] & TB1_ram_block1a21 # !TB1_address_reg_a[0] & (TB1_ram_block1a5);


--K1_dbs_8_reg_segment_2[5] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[5]
K1_dbs_8_reg_segment_2[5] = DFFEAS(W1_incoming_tri_state_bridge_0_data[5], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--H1L467 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3133
H1L467 = AMPP_FUNCTION(VB1L6, K1_dbs_8_reg_segment_2[5], W1L34, T1L17);


--H1L468 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3134
H1L468 = AMPP_FUNCTION(H1L1171, H1L466, H1L467);


--H1L13 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_b_is_dst~169
H1L13 = AMPP_FUNCTION(H1_D_iw[3], H1_D_iw[2], H1_D_iw[5]);


--H1L14 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_b_is_dst~170
H1L14 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[0], H1_D_iw[1], H1L13);


--H1L663 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_use_imm~98
H1L663 = AMPP_FUNCTION(H1_R_valid, H1L17, H1L14);


--A1L73 is rtl~93
A1L73 = H1_D_iw[0] & !H1_D_iw[1] & !H1_D_iw[2] & !H1_D_iw[5];


--H1L662 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_use_imm~1
H1L662 = AMPP_FUNCTION(H1L663, H1L43, H1_D_iw[11], H1L664);


--H1L47 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_unsigned_lo_imm~129
H1L47 = AMPP_FUNCTION(A1L72, A1L68, H1_D_iw[4], H1_D_iw[3]);


--H1L48 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_unsigned_lo_imm~130
H1L48 = AMPP_FUNCTION(H1L47, H1L42, H1_D_iw[13], H1_D_iw[11]);


--A1L102 is rtl~2845
A1L102 = H1_D_iw[11] & A1L80 & !H1_D_iw[15];


--H1L24 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_force_src2_zero~534
H1L24 = AMPP_FUNCTION(H1_D_iw[16], H1_D_iw[11], H1_D_iw[14], H1_D_iw[15]);


--H1L25 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_force_src2_zero~535
H1L25 = AMPP_FUNCTION(H1L24, H1_D_iw[15], A1L91, H1_D_iw[13]);


--H1L26 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_force_src2_zero~536
H1L26 = AMPP_FUNCTION(A1L102, H1L45, H1L25);


--A1L103 is rtl~2846
A1L103 = H1_D_iw[14] & H1_D_iw[15];


--H1L27 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_force_src2_zero~537
H1L27 = AMPP_FUNCTION(A1L103, A1L91, H1L15, H1L35);


--H1L28 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_force_src2_zero~538
H1L28 = AMPP_FUNCTION(H1L26, H1L33, H1L27);


--H1L30 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_hi_imm~98
H1L30 = AMPP_FUNCTION(H1_D_iw[0], H1_D_iw[1], H1_D_iw[3], H1_D_iw[4]);


--H1L31 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_hi_imm~99
H1L31 = AMPP_FUNCTION(H1_D_iw[2], H1_D_iw[5], H1L30);


--DB1_q_a[26] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[26]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[26]_PORT_A_data_in = H1_d_writedata[26];
DB1_q_a[26]_PORT_A_data_in_reg = DFFE(DB1_q_a[26]_PORT_A_data_in, DB1_q_a[26]_clock_0, , , );
DB1_q_a[26]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[26]_PORT_A_address_reg = DFFE(DB1_q_a[26]_PORT_A_address, DB1_q_a[26]_clock_0, , , );
DB1_q_a[26]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[26]_PORT_B_address_reg = DFFE(DB1_q_a[26]_PORT_B_address, DB1_q_a[26]_clock_0, , , );
DB1_q_a[26]_PORT_A_write_enable = L1L1;
DB1_q_a[26]_PORT_A_write_enable_reg = DFFE(DB1_q_a[26]_PORT_A_write_enable, DB1_q_a[26]_clock_0, , , );
DB1_q_a[26]_PORT_A_byte_mask = M1L25;
DB1_q_a[26]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[26]_PORT_A_byte_mask, DB1_q_a[26]_clock_0, , , );
DB1_q_a[26]_clock_0 = CLOCK_50;
DB1_q_a[26]_PORT_A_data_out = MEMORY(DB1_q_a[26]_PORT_A_data_in_reg, , DB1_q_a[26]_PORT_A_address_reg, DB1_q_a[26]_PORT_B_address_reg, DB1_q_a[26]_PORT_A_write_enable_reg, , DB1_q_a[26]_PORT_A_byte_mask_reg, , DB1_q_a[26]_clock_0, , , , , );
DB1_q_a[26] = DB1_q_a[26]_PORT_A_data_out[0];


--EB1_q_a[26] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[26]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[26]_PORT_A_data_in = H1_d_writedata[26];
EB1_q_a[26]_PORT_A_data_in_reg = DFFE(EB1_q_a[26]_PORT_A_data_in, EB1_q_a[26]_clock_0, , , );
EB1_q_a[26]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[26]_PORT_A_address_reg = DFFE(EB1_q_a[26]_PORT_A_address, EB1_q_a[26]_clock_0, , , );
EB1_q_a[26]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[26]_PORT_B_address_reg = DFFE(EB1_q_a[26]_PORT_B_address, EB1_q_a[26]_clock_0, , , );
EB1_q_a[26]_PORT_A_write_enable = GND;
EB1_q_a[26]_PORT_A_write_enable_reg = DFFE(EB1_q_a[26]_PORT_A_write_enable, EB1_q_a[26]_clock_0, , , );
EB1_q_a[26]_PORT_A_byte_mask = P1L31;
EB1_q_a[26]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[26]_PORT_A_byte_mask, EB1_q_a[26]_clock_0, , , );
EB1_q_a[26]_clock_0 = CLOCK_50;
EB1_q_a[26]_PORT_A_data_out = MEMORY(EB1_q_a[26]_PORT_A_data_in_reg, , EB1_q_a[26]_PORT_A_address_reg, EB1_q_a[26]_PORT_B_address_reg, EB1_q_a[26]_PORT_A_write_enable_reg, , EB1_q_a[26]_PORT_A_byte_mask_reg, , EB1_q_a[26]_clock_0, , , , , );
EB1_q_a[26] = EB1_q_a[26]_PORT_A_data_out[0];


--H1L469 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3135
H1L469 = AMPP_FUNCTION(DB1_q_a[26], EB1_q_a[26], P1L14, M1L10);


--W1_incoming_tri_state_bridge_0_data[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[2]
W1_incoming_tri_state_bridge_0_data[2] = DFFEAS(A1L53, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--TB1_ram_block1a26 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a26
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a26_PORT_A_data_in = J1L37;
TB1_ram_block1a26_PORT_A_data_in_reg = DFFE(TB1_ram_block1a26_PORT_A_data_in, TB1_ram_block1a26_clock_0, , , TB1_ram_block1a26_clock_enable_0);
TB1_ram_block1a26_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a26_PORT_A_address_reg = DFFE(TB1_ram_block1a26_PORT_A_address, TB1_ram_block1a26_clock_0, , , TB1_ram_block1a26_clock_enable_0);
TB1_ram_block1a26_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a26_PORT_B_address_reg = DFFE(TB1_ram_block1a26_PORT_B_address, TB1_ram_block1a26_clock_0, , , TB1_ram_block1a26_clock_enable_0);
TB1_ram_block1a26_PORT_A_write_enable = UB1L3;
TB1_ram_block1a26_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a26_PORT_A_write_enable, TB1_ram_block1a26_clock_0, , , TB1_ram_block1a26_clock_enable_0);
TB1_ram_block1a26_PORT_A_byte_mask = T1L53;
TB1_ram_block1a26_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a26_PORT_A_byte_mask, TB1_ram_block1a26_clock_0, , , TB1_ram_block1a26_clock_enable_0);
TB1_ram_block1a26_clock_0 = CLOCK_50;
TB1_ram_block1a26_clock_enable_0 = !T1L38;
TB1_ram_block1a26_PORT_A_data_out = MEMORY(TB1_ram_block1a26_PORT_A_data_in_reg, , TB1_ram_block1a26_PORT_A_address_reg, TB1_ram_block1a26_PORT_B_address_reg, TB1_ram_block1a26_PORT_A_write_enable_reg, , TB1_ram_block1a26_PORT_A_byte_mask_reg, , TB1_ram_block1a26_clock_0, , TB1_ram_block1a26_clock_enable_0, , , );
TB1_ram_block1a26 = TB1_ram_block1a26_PORT_A_data_out[0];


--TB1_ram_block1a10 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a10
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a10_PORT_A_data_in = J1L37;
TB1_ram_block1a10_PORT_A_data_in_reg = DFFE(TB1_ram_block1a10_PORT_A_data_in, TB1_ram_block1a10_clock_0, , , TB1_ram_block1a10_clock_enable_0);
TB1_ram_block1a10_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a10_PORT_A_address_reg = DFFE(TB1_ram_block1a10_PORT_A_address, TB1_ram_block1a10_clock_0, , , TB1_ram_block1a10_clock_enable_0);
TB1_ram_block1a10_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a10_PORT_B_address_reg = DFFE(TB1_ram_block1a10_PORT_B_address, TB1_ram_block1a10_clock_0, , , TB1_ram_block1a10_clock_enable_0);
TB1_ram_block1a10_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a10_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a10_PORT_A_write_enable, TB1_ram_block1a10_clock_0, , , TB1_ram_block1a10_clock_enable_0);
TB1_ram_block1a10_PORT_A_byte_mask = T1L53;
TB1_ram_block1a10_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a10_PORT_A_byte_mask, TB1_ram_block1a10_clock_0, , , TB1_ram_block1a10_clock_enable_0);
TB1_ram_block1a10_clock_0 = CLOCK_50;
TB1_ram_block1a10_clock_enable_0 = T1L38;
TB1_ram_block1a10_PORT_A_data_out = MEMORY(TB1_ram_block1a10_PORT_A_data_in_reg, , TB1_ram_block1a10_PORT_A_address_reg, TB1_ram_block1a10_PORT_B_address_reg, TB1_ram_block1a10_PORT_A_write_enable_reg, , TB1_ram_block1a10_PORT_A_byte_mask_reg, , TB1_ram_block1a10_clock_0, , TB1_ram_block1a10_clock_enable_0, , , );
TB1_ram_block1a10 = TB1_ram_block1a10_PORT_A_data_out[0];


--VB1L11 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[10]~434
VB1L11 = TB1_address_reg_a[0] & TB1_ram_block1a26 # !TB1_address_reg_a[0] & (TB1_ram_block1a10);


--H1L470 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3136
H1L470 = AMPP_FUNCTION(H1L469, H1L513, VB1L11, T1L17);


--H1L429 is DE2_Board:inst|cpu_0:the_cpu_0|E_valid~0
H1L429 = AMPP_FUNCTION(H1_R_valid, H1L427);


--H1_D_valid is DE2_Board:inst|cpu_0:the_cpu_0|D_valid
H1_D_valid = AMPP_FUNCTION(CLOCK_50, H1_F_valid, E1_data_out);


--H1L29 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_force_src2_zero~539
H1L29 = AMPP_FUNCTION(H1_D_iw[11], H1_D_iw[14], H1_D_iw[15], H1_D_iw[16]);


--H1L38 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_retaddr~39
H1L38 = AMPP_FUNCTION(H1L15, H1L29, H1L33, H1L27);


--H1_av_ld_byte2_data[5] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[5]
H1_av_ld_byte2_data[5] = AMPP_FUNCTION(CLOCK_50, H1L1054, H1_av_ld_byte3_data[5], E1_data_out, !H1L1103);


--DB1_q_a[25] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[25]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[25]_PORT_A_data_in = H1_d_writedata[25];
DB1_q_a[25]_PORT_A_data_in_reg = DFFE(DB1_q_a[25]_PORT_A_data_in, DB1_q_a[25]_clock_0, , , );
DB1_q_a[25]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[25]_PORT_A_address_reg = DFFE(DB1_q_a[25]_PORT_A_address, DB1_q_a[25]_clock_0, , , );
DB1_q_a[25]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[25]_PORT_B_address_reg = DFFE(DB1_q_a[25]_PORT_B_address, DB1_q_a[25]_clock_0, , , );
DB1_q_a[25]_PORT_A_write_enable = L1L1;
DB1_q_a[25]_PORT_A_write_enable_reg = DFFE(DB1_q_a[25]_PORT_A_write_enable, DB1_q_a[25]_clock_0, , , );
DB1_q_a[25]_PORT_A_byte_mask = M1L25;
DB1_q_a[25]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[25]_PORT_A_byte_mask, DB1_q_a[25]_clock_0, , , );
DB1_q_a[25]_clock_0 = CLOCK_50;
DB1_q_a[25]_PORT_A_data_out = MEMORY(DB1_q_a[25]_PORT_A_data_in_reg, , DB1_q_a[25]_PORT_A_address_reg, DB1_q_a[25]_PORT_B_address_reg, DB1_q_a[25]_PORT_A_write_enable_reg, , DB1_q_a[25]_PORT_A_byte_mask_reg, , DB1_q_a[25]_clock_0, , , , , );
DB1_q_a[25] = DB1_q_a[25]_PORT_A_data_out[0];


--EB1_q_a[25] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[25]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[25]_PORT_A_data_in = H1_d_writedata[25];
EB1_q_a[25]_PORT_A_data_in_reg = DFFE(EB1_q_a[25]_PORT_A_data_in, EB1_q_a[25]_clock_0, , , );
EB1_q_a[25]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[25]_PORT_A_address_reg = DFFE(EB1_q_a[25]_PORT_A_address, EB1_q_a[25]_clock_0, , , );
EB1_q_a[25]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[25]_PORT_B_address_reg = DFFE(EB1_q_a[25]_PORT_B_address, EB1_q_a[25]_clock_0, , , );
EB1_q_a[25]_PORT_A_write_enable = GND;
EB1_q_a[25]_PORT_A_write_enable_reg = DFFE(EB1_q_a[25]_PORT_A_write_enable, EB1_q_a[25]_clock_0, , , );
EB1_q_a[25]_PORT_A_byte_mask = P1L31;
EB1_q_a[25]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[25]_PORT_A_byte_mask, EB1_q_a[25]_clock_0, , , );
EB1_q_a[25]_clock_0 = CLOCK_50;
EB1_q_a[25]_PORT_A_data_out = MEMORY(EB1_q_a[25]_PORT_A_data_in_reg, , EB1_q_a[25]_PORT_A_address_reg, EB1_q_a[25]_PORT_B_address_reg, EB1_q_a[25]_PORT_A_write_enable_reg, , EB1_q_a[25]_PORT_A_byte_mask_reg, , EB1_q_a[25]_clock_0, , , , , );
EB1_q_a[25] = EB1_q_a[25]_PORT_A_data_out[0];


--H1L471 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3137
H1L471 = AMPP_FUNCTION(DB1_q_a[25], EB1_q_a[25], P1L14, M1L10);


--W1_incoming_tri_state_bridge_0_data[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[1]
W1_incoming_tri_state_bridge_0_data[1] = DFFEAS(A1L54, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--TB1_ram_block1a25 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a25
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a25_PORT_A_data_in = J1L36;
TB1_ram_block1a25_PORT_A_data_in_reg = DFFE(TB1_ram_block1a25_PORT_A_data_in, TB1_ram_block1a25_clock_0, , , TB1_ram_block1a25_clock_enable_0);
TB1_ram_block1a25_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a25_PORT_A_address_reg = DFFE(TB1_ram_block1a25_PORT_A_address, TB1_ram_block1a25_clock_0, , , TB1_ram_block1a25_clock_enable_0);
TB1_ram_block1a25_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a25_PORT_B_address_reg = DFFE(TB1_ram_block1a25_PORT_B_address, TB1_ram_block1a25_clock_0, , , TB1_ram_block1a25_clock_enable_0);
TB1_ram_block1a25_PORT_A_write_enable = UB1L3;
TB1_ram_block1a25_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a25_PORT_A_write_enable, TB1_ram_block1a25_clock_0, , , TB1_ram_block1a25_clock_enable_0);
TB1_ram_block1a25_PORT_A_byte_mask = T1L53;
TB1_ram_block1a25_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a25_PORT_A_byte_mask, TB1_ram_block1a25_clock_0, , , TB1_ram_block1a25_clock_enable_0);
TB1_ram_block1a25_clock_0 = CLOCK_50;
TB1_ram_block1a25_clock_enable_0 = !T1L38;
TB1_ram_block1a25_PORT_A_data_out = MEMORY(TB1_ram_block1a25_PORT_A_data_in_reg, , TB1_ram_block1a25_PORT_A_address_reg, TB1_ram_block1a25_PORT_B_address_reg, TB1_ram_block1a25_PORT_A_write_enable_reg, , TB1_ram_block1a25_PORT_A_byte_mask_reg, , TB1_ram_block1a25_clock_0, , TB1_ram_block1a25_clock_enable_0, , , );
TB1_ram_block1a25 = TB1_ram_block1a25_PORT_A_data_out[0];


--TB1_ram_block1a9 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a9
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a9_PORT_A_data_in = J1L36;
TB1_ram_block1a9_PORT_A_data_in_reg = DFFE(TB1_ram_block1a9_PORT_A_data_in, TB1_ram_block1a9_clock_0, , , TB1_ram_block1a9_clock_enable_0);
TB1_ram_block1a9_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a9_PORT_A_address_reg = DFFE(TB1_ram_block1a9_PORT_A_address, TB1_ram_block1a9_clock_0, , , TB1_ram_block1a9_clock_enable_0);
TB1_ram_block1a9_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a9_PORT_B_address_reg = DFFE(TB1_ram_block1a9_PORT_B_address, TB1_ram_block1a9_clock_0, , , TB1_ram_block1a9_clock_enable_0);
TB1_ram_block1a9_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a9_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a9_PORT_A_write_enable, TB1_ram_block1a9_clock_0, , , TB1_ram_block1a9_clock_enable_0);
TB1_ram_block1a9_PORT_A_byte_mask = T1L53;
TB1_ram_block1a9_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a9_PORT_A_byte_mask, TB1_ram_block1a9_clock_0, , , TB1_ram_block1a9_clock_enable_0);
TB1_ram_block1a9_clock_0 = CLOCK_50;
TB1_ram_block1a9_clock_enable_0 = T1L38;
TB1_ram_block1a9_PORT_A_data_out = MEMORY(TB1_ram_block1a9_PORT_A_data_in_reg, , TB1_ram_block1a9_PORT_A_address_reg, TB1_ram_block1a9_PORT_B_address_reg, TB1_ram_block1a9_PORT_A_write_enable_reg, , TB1_ram_block1a9_PORT_A_byte_mask_reg, , TB1_ram_block1a9_clock_0, , TB1_ram_block1a9_clock_enable_0, , , );
TB1_ram_block1a9 = TB1_ram_block1a9_PORT_A_data_out[0];


--VB1L10 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[9]~435
VB1L10 = TB1_address_reg_a[0] & TB1_ram_block1a25 # !TB1_address_reg_a[0] & (TB1_ram_block1a9);


--H1L472 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3138
H1L472 = AMPP_FUNCTION(H1L471, H1L514, VB1L10, T1L17);


--H1_av_ld_byte2_data[4] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[4]
H1_av_ld_byte2_data[4] = AMPP_FUNCTION(CLOCK_50, H1L1051, H1_av_ld_byte3_data[4], E1_data_out, !H1L1103);


--DB1_q_a[10] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[10]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[10]_PORT_A_data_in = H1_d_writedata[10];
DB1_q_a[10]_PORT_A_data_in_reg = DFFE(DB1_q_a[10]_PORT_A_data_in, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[10]_PORT_A_address_reg = DFFE(DB1_q_a[10]_PORT_A_address, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[10]_PORT_B_address_reg = DFFE(DB1_q_a[10]_PORT_B_address, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_A_write_enable = L1L1;
DB1_q_a[10]_PORT_A_write_enable_reg = DFFE(DB1_q_a[10]_PORT_A_write_enable, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_PORT_A_byte_mask = M1L23;
DB1_q_a[10]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[10]_PORT_A_byte_mask, DB1_q_a[10]_clock_0, , , );
DB1_q_a[10]_clock_0 = CLOCK_50;
DB1_q_a[10]_PORT_A_data_out = MEMORY(DB1_q_a[10]_PORT_A_data_in_reg, , DB1_q_a[10]_PORT_A_address_reg, DB1_q_a[10]_PORT_B_address_reg, DB1_q_a[10]_PORT_A_write_enable_reg, , DB1_q_a[10]_PORT_A_byte_mask_reg, , DB1_q_a[10]_clock_0, , , , , );
DB1_q_a[10] = DB1_q_a[10]_PORT_A_data_out[0];


--EB1_q_a[10] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[10]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[10]_PORT_A_data_in = H1_d_writedata[10];
EB1_q_a[10]_PORT_A_data_in_reg = DFFE(EB1_q_a[10]_PORT_A_data_in, EB1_q_a[10]_clock_0, , , );
EB1_q_a[10]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[10]_PORT_A_address_reg = DFFE(EB1_q_a[10]_PORT_A_address, EB1_q_a[10]_clock_0, , , );
EB1_q_a[10]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[10]_PORT_B_address_reg = DFFE(EB1_q_a[10]_PORT_B_address, EB1_q_a[10]_clock_0, , , );
EB1_q_a[10]_PORT_A_write_enable = GND;
EB1_q_a[10]_PORT_A_write_enable_reg = DFFE(EB1_q_a[10]_PORT_A_write_enable, EB1_q_a[10]_clock_0, , , );
EB1_q_a[10]_PORT_A_byte_mask = P1L29;
EB1_q_a[10]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[10]_PORT_A_byte_mask, EB1_q_a[10]_clock_0, , , );
EB1_q_a[10]_clock_0 = CLOCK_50;
EB1_q_a[10]_PORT_A_data_out = MEMORY(EB1_q_a[10]_PORT_A_data_in_reg, , EB1_q_a[10]_PORT_A_address_reg, EB1_q_a[10]_PORT_B_address_reg, EB1_q_a[10]_PORT_A_write_enable_reg, , EB1_q_a[10]_PORT_A_byte_mask_reg, , EB1_q_a[10]_clock_0, , , , , );
EB1_q_a[10] = EB1_q_a[10]_PORT_A_data_out[0];


--H1L473 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3139
H1L473 = AMPP_FUNCTION(DB1_q_a[10], EB1_q_a[10], P1L14, M1L10);


--K1_dbs_8_reg_segment_1[2] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[2]
K1_dbs_8_reg_segment_1[2] = DFFEAS(W1_incoming_tri_state_bridge_0_data[2], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[10] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[10]
K1_dbs_16_reg_segment_0[10] = DFFEAS(VB1L11, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L474 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3140
H1L474 = AMPP_FUNCTION(H1L473, H1L515, K1_dbs_16_reg_segment_0[10], T1L17);


--DB1_q_a[24] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[24]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[24]_PORT_A_data_in = H1_d_writedata[24];
DB1_q_a[24]_PORT_A_data_in_reg = DFFE(DB1_q_a[24]_PORT_A_data_in, DB1_q_a[24]_clock_0, , , );
DB1_q_a[24]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[24]_PORT_A_address_reg = DFFE(DB1_q_a[24]_PORT_A_address, DB1_q_a[24]_clock_0, , , );
DB1_q_a[24]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[24]_PORT_B_address_reg = DFFE(DB1_q_a[24]_PORT_B_address, DB1_q_a[24]_clock_0, , , );
DB1_q_a[24]_PORT_A_write_enable = L1L1;
DB1_q_a[24]_PORT_A_write_enable_reg = DFFE(DB1_q_a[24]_PORT_A_write_enable, DB1_q_a[24]_clock_0, , , );
DB1_q_a[24]_PORT_A_byte_mask = M1L25;
DB1_q_a[24]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[24]_PORT_A_byte_mask, DB1_q_a[24]_clock_0, , , );
DB1_q_a[24]_clock_0 = CLOCK_50;
DB1_q_a[24]_PORT_A_data_out = MEMORY(DB1_q_a[24]_PORT_A_data_in_reg, , DB1_q_a[24]_PORT_A_address_reg, DB1_q_a[24]_PORT_B_address_reg, DB1_q_a[24]_PORT_A_write_enable_reg, , DB1_q_a[24]_PORT_A_byte_mask_reg, , DB1_q_a[24]_clock_0, , , , , );
DB1_q_a[24] = DB1_q_a[24]_PORT_A_data_out[0];


--EB1_q_a[24] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[24]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[24]_PORT_A_data_in = H1_d_writedata[24];
EB1_q_a[24]_PORT_A_data_in_reg = DFFE(EB1_q_a[24]_PORT_A_data_in, EB1_q_a[24]_clock_0, , , );
EB1_q_a[24]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[24]_PORT_A_address_reg = DFFE(EB1_q_a[24]_PORT_A_address, EB1_q_a[24]_clock_0, , , );
EB1_q_a[24]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[24]_PORT_B_address_reg = DFFE(EB1_q_a[24]_PORT_B_address, EB1_q_a[24]_clock_0, , , );
EB1_q_a[24]_PORT_A_write_enable = GND;
EB1_q_a[24]_PORT_A_write_enable_reg = DFFE(EB1_q_a[24]_PORT_A_write_enable, EB1_q_a[24]_clock_0, , , );
EB1_q_a[24]_PORT_A_byte_mask = P1L31;
EB1_q_a[24]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[24]_PORT_A_byte_mask, EB1_q_a[24]_clock_0, , , );
EB1_q_a[24]_clock_0 = CLOCK_50;
EB1_q_a[24]_PORT_A_data_out = MEMORY(EB1_q_a[24]_PORT_A_data_in_reg, , EB1_q_a[24]_PORT_A_address_reg, EB1_q_a[24]_PORT_B_address_reg, EB1_q_a[24]_PORT_A_write_enable_reg, , EB1_q_a[24]_PORT_A_byte_mask_reg, , EB1_q_a[24]_clock_0, , , , , );
EB1_q_a[24] = EB1_q_a[24]_PORT_A_data_out[0];


--H1L475 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3141
H1L475 = AMPP_FUNCTION(DB1_q_a[24], EB1_q_a[24], P1L14, M1L10);


--W1_incoming_tri_state_bridge_0_data[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[0]
W1_incoming_tri_state_bridge_0_data[0] = DFFEAS(A1L55, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--TB1_ram_block1a24 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a24
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a24_PORT_A_data_in = J1L35;
TB1_ram_block1a24_PORT_A_data_in_reg = DFFE(TB1_ram_block1a24_PORT_A_data_in, TB1_ram_block1a24_clock_0, , , TB1_ram_block1a24_clock_enable_0);
TB1_ram_block1a24_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a24_PORT_A_address_reg = DFFE(TB1_ram_block1a24_PORT_A_address, TB1_ram_block1a24_clock_0, , , TB1_ram_block1a24_clock_enable_0);
TB1_ram_block1a24_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a24_PORT_B_address_reg = DFFE(TB1_ram_block1a24_PORT_B_address, TB1_ram_block1a24_clock_0, , , TB1_ram_block1a24_clock_enable_0);
TB1_ram_block1a24_PORT_A_write_enable = UB1L3;
TB1_ram_block1a24_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a24_PORT_A_write_enable, TB1_ram_block1a24_clock_0, , , TB1_ram_block1a24_clock_enable_0);
TB1_ram_block1a24_PORT_A_byte_mask = T1L53;
TB1_ram_block1a24_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a24_PORT_A_byte_mask, TB1_ram_block1a24_clock_0, , , TB1_ram_block1a24_clock_enable_0);
TB1_ram_block1a24_clock_0 = CLOCK_50;
TB1_ram_block1a24_clock_enable_0 = !T1L38;
TB1_ram_block1a24_PORT_A_data_out = MEMORY(TB1_ram_block1a24_PORT_A_data_in_reg, , TB1_ram_block1a24_PORT_A_address_reg, TB1_ram_block1a24_PORT_B_address_reg, TB1_ram_block1a24_PORT_A_write_enable_reg, , TB1_ram_block1a24_PORT_A_byte_mask_reg, , TB1_ram_block1a24_clock_0, , TB1_ram_block1a24_clock_enable_0, , , );
TB1_ram_block1a24 = TB1_ram_block1a24_PORT_A_data_out[0];


--TB1_ram_block1a8 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a8
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a8_PORT_A_data_in = J1L35;
TB1_ram_block1a8_PORT_A_data_in_reg = DFFE(TB1_ram_block1a8_PORT_A_data_in, TB1_ram_block1a8_clock_0, , , TB1_ram_block1a8_clock_enable_0);
TB1_ram_block1a8_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a8_PORT_A_address_reg = DFFE(TB1_ram_block1a8_PORT_A_address, TB1_ram_block1a8_clock_0, , , TB1_ram_block1a8_clock_enable_0);
TB1_ram_block1a8_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a8_PORT_B_address_reg = DFFE(TB1_ram_block1a8_PORT_B_address, TB1_ram_block1a8_clock_0, , , TB1_ram_block1a8_clock_enable_0);
TB1_ram_block1a8_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a8_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a8_PORT_A_write_enable, TB1_ram_block1a8_clock_0, , , TB1_ram_block1a8_clock_enable_0);
TB1_ram_block1a8_PORT_A_byte_mask = T1L53;
TB1_ram_block1a8_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a8_PORT_A_byte_mask, TB1_ram_block1a8_clock_0, , , TB1_ram_block1a8_clock_enable_0);
TB1_ram_block1a8_clock_0 = CLOCK_50;
TB1_ram_block1a8_clock_enable_0 = T1L38;
TB1_ram_block1a8_PORT_A_data_out = MEMORY(TB1_ram_block1a8_PORT_A_data_in_reg, , TB1_ram_block1a8_PORT_A_address_reg, TB1_ram_block1a8_PORT_B_address_reg, TB1_ram_block1a8_PORT_A_write_enable_reg, , TB1_ram_block1a8_PORT_A_byte_mask_reg, , TB1_ram_block1a8_clock_0, , TB1_ram_block1a8_clock_enable_0, , , );
TB1_ram_block1a8 = TB1_ram_block1a8_PORT_A_data_out[0];


--VB1L9 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[8]~436
VB1L9 = TB1_address_reg_a[0] & TB1_ram_block1a24 # !TB1_address_reg_a[0] & (TB1_ram_block1a8);


--H1L476 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3142
H1L476 = AMPP_FUNCTION(H1L475, H1L516, VB1L9, T1L17);


--H1_av_ld_byte2_data[3] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[3]
H1_av_ld_byte2_data[3] = AMPP_FUNCTION(CLOCK_50, H1L1048, H1_av_ld_byte3_data[3], E1_data_out, !H1L1103);


--DB1_q_a[9] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[9]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[9]_PORT_A_data_in = H1_d_writedata[9];
DB1_q_a[9]_PORT_A_data_in_reg = DFFE(DB1_q_a[9]_PORT_A_data_in, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[9]_PORT_A_address_reg = DFFE(DB1_q_a[9]_PORT_A_address, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[9]_PORT_B_address_reg = DFFE(DB1_q_a[9]_PORT_B_address, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9]_PORT_A_write_enable = L1L1;
DB1_q_a[9]_PORT_A_write_enable_reg = DFFE(DB1_q_a[9]_PORT_A_write_enable, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9]_PORT_A_byte_mask = M1L23;
DB1_q_a[9]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[9]_PORT_A_byte_mask, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9]_clock_0 = CLOCK_50;
DB1_q_a[9]_PORT_A_data_out = MEMORY(DB1_q_a[9]_PORT_A_data_in_reg, , DB1_q_a[9]_PORT_A_address_reg, DB1_q_a[9]_PORT_B_address_reg, DB1_q_a[9]_PORT_A_write_enable_reg, , DB1_q_a[9]_PORT_A_byte_mask_reg, , DB1_q_a[9]_clock_0, , , , , );
DB1_q_a[9] = DB1_q_a[9]_PORT_A_data_out[0];


--EB1_q_a[9] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[9]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[9]_PORT_A_data_in = H1_d_writedata[9];
EB1_q_a[9]_PORT_A_data_in_reg = DFFE(EB1_q_a[9]_PORT_A_data_in, EB1_q_a[9]_clock_0, , , );
EB1_q_a[9]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[9]_PORT_A_address_reg = DFFE(EB1_q_a[9]_PORT_A_address, EB1_q_a[9]_clock_0, , , );
EB1_q_a[9]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[9]_PORT_B_address_reg = DFFE(EB1_q_a[9]_PORT_B_address, EB1_q_a[9]_clock_0, , , );
EB1_q_a[9]_PORT_A_write_enable = GND;
EB1_q_a[9]_PORT_A_write_enable_reg = DFFE(EB1_q_a[9]_PORT_A_write_enable, EB1_q_a[9]_clock_0, , , );
EB1_q_a[9]_PORT_A_byte_mask = P1L29;
EB1_q_a[9]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[9]_PORT_A_byte_mask, EB1_q_a[9]_clock_0, , , );
EB1_q_a[9]_clock_0 = CLOCK_50;
EB1_q_a[9]_PORT_A_data_out = MEMORY(EB1_q_a[9]_PORT_A_data_in_reg, , EB1_q_a[9]_PORT_A_address_reg, EB1_q_a[9]_PORT_B_address_reg, EB1_q_a[9]_PORT_A_write_enable_reg, , EB1_q_a[9]_PORT_A_byte_mask_reg, , EB1_q_a[9]_clock_0, , , , , );
EB1_q_a[9] = EB1_q_a[9]_PORT_A_data_out[0];


--H1L477 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3143
H1L477 = AMPP_FUNCTION(DB1_q_a[9], EB1_q_a[9], P1L14, M1L10);


--K1_dbs_8_reg_segment_1[1] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[1]
K1_dbs_8_reg_segment_1[1] = DFFEAS(W1_incoming_tri_state_bridge_0_data[1], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[9] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[9]
K1_dbs_16_reg_segment_0[9] = DFFEAS(VB1L10, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L478 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3144
H1L478 = AMPP_FUNCTION(H1L477, H1L517, K1_dbs_16_reg_segment_0[9], T1L17);


--DB1_q_a[23] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[23]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[23]_PORT_A_data_in = H1_d_writedata[23];
DB1_q_a[23]_PORT_A_data_in_reg = DFFE(DB1_q_a[23]_PORT_A_data_in, DB1_q_a[23]_clock_0, , , );
DB1_q_a[23]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[23]_PORT_A_address_reg = DFFE(DB1_q_a[23]_PORT_A_address, DB1_q_a[23]_clock_0, , , );
DB1_q_a[23]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[23]_PORT_B_address_reg = DFFE(DB1_q_a[23]_PORT_B_address, DB1_q_a[23]_clock_0, , , );
DB1_q_a[23]_PORT_A_write_enable = L1L1;
DB1_q_a[23]_PORT_A_write_enable_reg = DFFE(DB1_q_a[23]_PORT_A_write_enable, DB1_q_a[23]_clock_0, , , );
DB1_q_a[23]_PORT_A_byte_mask = M1L24;
DB1_q_a[23]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[23]_PORT_A_byte_mask, DB1_q_a[23]_clock_0, , , );
DB1_q_a[23]_clock_0 = CLOCK_50;
DB1_q_a[23]_PORT_A_data_out = MEMORY(DB1_q_a[23]_PORT_A_data_in_reg, , DB1_q_a[23]_PORT_A_address_reg, DB1_q_a[23]_PORT_B_address_reg, DB1_q_a[23]_PORT_A_write_enable_reg, , DB1_q_a[23]_PORT_A_byte_mask_reg, , DB1_q_a[23]_clock_0, , , , , );
DB1_q_a[23] = DB1_q_a[23]_PORT_A_data_out[0];


--EB1_q_a[23] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[23]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[23]_PORT_A_data_in = H1_d_writedata[23];
EB1_q_a[23]_PORT_A_data_in_reg = DFFE(EB1_q_a[23]_PORT_A_data_in, EB1_q_a[23]_clock_0, , , );
EB1_q_a[23]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[23]_PORT_A_address_reg = DFFE(EB1_q_a[23]_PORT_A_address, EB1_q_a[23]_clock_0, , , );
EB1_q_a[23]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[23]_PORT_B_address_reg = DFFE(EB1_q_a[23]_PORT_B_address, EB1_q_a[23]_clock_0, , , );
EB1_q_a[23]_PORT_A_write_enable = GND;
EB1_q_a[23]_PORT_A_write_enable_reg = DFFE(EB1_q_a[23]_PORT_A_write_enable, EB1_q_a[23]_clock_0, , , );
EB1_q_a[23]_PORT_A_byte_mask = P1L30;
EB1_q_a[23]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[23]_PORT_A_byte_mask, EB1_q_a[23]_clock_0, , , );
EB1_q_a[23]_clock_0 = CLOCK_50;
EB1_q_a[23]_PORT_A_data_out = MEMORY(EB1_q_a[23]_PORT_A_data_in_reg, , EB1_q_a[23]_PORT_A_address_reg, EB1_q_a[23]_PORT_B_address_reg, EB1_q_a[23]_PORT_A_write_enable_reg, , EB1_q_a[23]_PORT_A_byte_mask_reg, , EB1_q_a[23]_clock_0, , , , , );
EB1_q_a[23] = EB1_q_a[23]_PORT_A_data_out[0];


--H1L479 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3145
H1L479 = AMPP_FUNCTION(DB1_q_a[23], EB1_q_a[23], P1L14, M1L10);


--K1_dbs_8_reg_segment_2[7] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[7]
K1_dbs_8_reg_segment_2[7] = DFFEAS(W1_incoming_tri_state_bridge_0_data[7], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--TB1_ram_block1a23 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a23
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a23_PORT_A_data_in = J1L34;
TB1_ram_block1a23_PORT_A_data_in_reg = DFFE(TB1_ram_block1a23_PORT_A_data_in, TB1_ram_block1a23_clock_0, , , TB1_ram_block1a23_clock_enable_0);
TB1_ram_block1a23_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a23_PORT_A_address_reg = DFFE(TB1_ram_block1a23_PORT_A_address, TB1_ram_block1a23_clock_0, , , TB1_ram_block1a23_clock_enable_0);
TB1_ram_block1a23_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a23_PORT_B_address_reg = DFFE(TB1_ram_block1a23_PORT_B_address, TB1_ram_block1a23_clock_0, , , TB1_ram_block1a23_clock_enable_0);
TB1_ram_block1a23_PORT_A_write_enable = UB1L3;
TB1_ram_block1a23_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a23_PORT_A_write_enable, TB1_ram_block1a23_clock_0, , , TB1_ram_block1a23_clock_enable_0);
TB1_ram_block1a23_PORT_A_byte_mask = T1L52;
TB1_ram_block1a23_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a23_PORT_A_byte_mask, TB1_ram_block1a23_clock_0, , , TB1_ram_block1a23_clock_enable_0);
TB1_ram_block1a23_clock_0 = CLOCK_50;
TB1_ram_block1a23_clock_enable_0 = !T1L38;
TB1_ram_block1a23_PORT_A_data_out = MEMORY(TB1_ram_block1a23_PORT_A_data_in_reg, , TB1_ram_block1a23_PORT_A_address_reg, TB1_ram_block1a23_PORT_B_address_reg, TB1_ram_block1a23_PORT_A_write_enable_reg, , TB1_ram_block1a23_PORT_A_byte_mask_reg, , TB1_ram_block1a23_clock_0, , TB1_ram_block1a23_clock_enable_0, , , );
TB1_ram_block1a23 = TB1_ram_block1a23_PORT_A_data_out[0];


--TB1_ram_block1a7 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a7
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a7_PORT_A_data_in = J1L34;
TB1_ram_block1a7_PORT_A_data_in_reg = DFFE(TB1_ram_block1a7_PORT_A_data_in, TB1_ram_block1a7_clock_0, , , TB1_ram_block1a7_clock_enable_0);
TB1_ram_block1a7_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a7_PORT_A_address_reg = DFFE(TB1_ram_block1a7_PORT_A_address, TB1_ram_block1a7_clock_0, , , TB1_ram_block1a7_clock_enable_0);
TB1_ram_block1a7_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a7_PORT_B_address_reg = DFFE(TB1_ram_block1a7_PORT_B_address, TB1_ram_block1a7_clock_0, , , TB1_ram_block1a7_clock_enable_0);
TB1_ram_block1a7_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a7_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a7_PORT_A_write_enable, TB1_ram_block1a7_clock_0, , , TB1_ram_block1a7_clock_enable_0);
TB1_ram_block1a7_PORT_A_byte_mask = T1L52;
TB1_ram_block1a7_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a7_PORT_A_byte_mask, TB1_ram_block1a7_clock_0, , , TB1_ram_block1a7_clock_enable_0);
TB1_ram_block1a7_clock_0 = CLOCK_50;
TB1_ram_block1a7_clock_enable_0 = T1L38;
TB1_ram_block1a7_PORT_A_data_out = MEMORY(TB1_ram_block1a7_PORT_A_data_in_reg, , TB1_ram_block1a7_PORT_A_address_reg, TB1_ram_block1a7_PORT_B_address_reg, TB1_ram_block1a7_PORT_A_write_enable_reg, , TB1_ram_block1a7_PORT_A_byte_mask_reg, , TB1_ram_block1a7_clock_0, , TB1_ram_block1a7_clock_enable_0, , , );
TB1_ram_block1a7 = TB1_ram_block1a7_PORT_A_data_out[0];


--VB1L8 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[7]~437
VB1L8 = TB1_address_reg_a[0] & TB1_ram_block1a23 # !TB1_address_reg_a[0] & (TB1_ram_block1a7);


--H1L480 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3146
H1L480 = AMPP_FUNCTION(H1L479, H1L518, VB1L8, T1L17);


--H1_av_ld_byte2_data[2] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[2]
H1_av_ld_byte2_data[2] = AMPP_FUNCTION(CLOCK_50, H1L1045, H1_av_ld_byte3_data[2], E1_data_out, !H1L1103);


--DB1_q_a[8] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[8]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[8]_PORT_A_data_in = H1_d_writedata[8];
DB1_q_a[8]_PORT_A_data_in_reg = DFFE(DB1_q_a[8]_PORT_A_data_in, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[8]_PORT_A_address_reg = DFFE(DB1_q_a[8]_PORT_A_address, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[8]_PORT_B_address_reg = DFFE(DB1_q_a[8]_PORT_B_address, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8]_PORT_A_write_enable = L1L1;
DB1_q_a[8]_PORT_A_write_enable_reg = DFFE(DB1_q_a[8]_PORT_A_write_enable, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8]_PORT_A_byte_mask = M1L23;
DB1_q_a[8]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[8]_PORT_A_byte_mask, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8]_clock_0 = CLOCK_50;
DB1_q_a[8]_PORT_A_data_out = MEMORY(DB1_q_a[8]_PORT_A_data_in_reg, , DB1_q_a[8]_PORT_A_address_reg, DB1_q_a[8]_PORT_B_address_reg, DB1_q_a[8]_PORT_A_write_enable_reg, , DB1_q_a[8]_PORT_A_byte_mask_reg, , DB1_q_a[8]_clock_0, , , , , );
DB1_q_a[8] = DB1_q_a[8]_PORT_A_data_out[0];


--EB1_q_a[8] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[8]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[8]_PORT_A_data_in = H1_d_writedata[8];
EB1_q_a[8]_PORT_A_data_in_reg = DFFE(EB1_q_a[8]_PORT_A_data_in, EB1_q_a[8]_clock_0, , , );
EB1_q_a[8]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[8]_PORT_A_address_reg = DFFE(EB1_q_a[8]_PORT_A_address, EB1_q_a[8]_clock_0, , , );
EB1_q_a[8]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[8]_PORT_B_address_reg = DFFE(EB1_q_a[8]_PORT_B_address, EB1_q_a[8]_clock_0, , , );
EB1_q_a[8]_PORT_A_write_enable = GND;
EB1_q_a[8]_PORT_A_write_enable_reg = DFFE(EB1_q_a[8]_PORT_A_write_enable, EB1_q_a[8]_clock_0, , , );
EB1_q_a[8]_PORT_A_byte_mask = P1L29;
EB1_q_a[8]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[8]_PORT_A_byte_mask, EB1_q_a[8]_clock_0, , , );
EB1_q_a[8]_clock_0 = CLOCK_50;
EB1_q_a[8]_PORT_A_data_out = MEMORY(EB1_q_a[8]_PORT_A_data_in_reg, , EB1_q_a[8]_PORT_A_address_reg, EB1_q_a[8]_PORT_B_address_reg, EB1_q_a[8]_PORT_A_write_enable_reg, , EB1_q_a[8]_PORT_A_byte_mask_reg, , EB1_q_a[8]_clock_0, , , , , );
EB1_q_a[8] = EB1_q_a[8]_PORT_A_data_out[0];


--H1L481 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3147
H1L481 = AMPP_FUNCTION(DB1_q_a[8], EB1_q_a[8], P1L14, M1L10);


--K1_dbs_8_reg_segment_1[0] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_1[0]
K1_dbs_8_reg_segment_1[0] = DFFEAS(W1_incoming_tri_state_bridge_0_data[0], CLOCK_50, E1_data_out,  , K1L4,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[8] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[8]
K1_dbs_16_reg_segment_0[8] = DFFEAS(VB1L9, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L482 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3148
H1L482 = AMPP_FUNCTION(H1L481, H1L519, K1_dbs_16_reg_segment_0[8], T1L17);


--DB1_q_a[22] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[22]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[22]_PORT_A_data_in = H1_d_writedata[22];
DB1_q_a[22]_PORT_A_data_in_reg = DFFE(DB1_q_a[22]_PORT_A_data_in, DB1_q_a[22]_clock_0, , , );
DB1_q_a[22]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[22]_PORT_A_address_reg = DFFE(DB1_q_a[22]_PORT_A_address, DB1_q_a[22]_clock_0, , , );
DB1_q_a[22]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[22]_PORT_B_address_reg = DFFE(DB1_q_a[22]_PORT_B_address, DB1_q_a[22]_clock_0, , , );
DB1_q_a[22]_PORT_A_write_enable = L1L1;
DB1_q_a[22]_PORT_A_write_enable_reg = DFFE(DB1_q_a[22]_PORT_A_write_enable, DB1_q_a[22]_clock_0, , , );
DB1_q_a[22]_PORT_A_byte_mask = M1L24;
DB1_q_a[22]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[22]_PORT_A_byte_mask, DB1_q_a[22]_clock_0, , , );
DB1_q_a[22]_clock_0 = CLOCK_50;
DB1_q_a[22]_PORT_A_data_out = MEMORY(DB1_q_a[22]_PORT_A_data_in_reg, , DB1_q_a[22]_PORT_A_address_reg, DB1_q_a[22]_PORT_B_address_reg, DB1_q_a[22]_PORT_A_write_enable_reg, , DB1_q_a[22]_PORT_A_byte_mask_reg, , DB1_q_a[22]_clock_0, , , , , );
DB1_q_a[22] = DB1_q_a[22]_PORT_A_data_out[0];


--EB1_q_a[22] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[22]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[22]_PORT_A_data_in = H1_d_writedata[22];
EB1_q_a[22]_PORT_A_data_in_reg = DFFE(EB1_q_a[22]_PORT_A_data_in, EB1_q_a[22]_clock_0, , , );
EB1_q_a[22]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[22]_PORT_A_address_reg = DFFE(EB1_q_a[22]_PORT_A_address, EB1_q_a[22]_clock_0, , , );
EB1_q_a[22]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[22]_PORT_B_address_reg = DFFE(EB1_q_a[22]_PORT_B_address, EB1_q_a[22]_clock_0, , , );
EB1_q_a[22]_PORT_A_write_enable = GND;
EB1_q_a[22]_PORT_A_write_enable_reg = DFFE(EB1_q_a[22]_PORT_A_write_enable, EB1_q_a[22]_clock_0, , , );
EB1_q_a[22]_PORT_A_byte_mask = P1L30;
EB1_q_a[22]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[22]_PORT_A_byte_mask, EB1_q_a[22]_clock_0, , , );
EB1_q_a[22]_clock_0 = CLOCK_50;
EB1_q_a[22]_PORT_A_data_out = MEMORY(EB1_q_a[22]_PORT_A_data_in_reg, , EB1_q_a[22]_PORT_A_address_reg, EB1_q_a[22]_PORT_B_address_reg, EB1_q_a[22]_PORT_A_write_enable_reg, , EB1_q_a[22]_PORT_A_byte_mask_reg, , EB1_q_a[22]_clock_0, , , , , );
EB1_q_a[22] = EB1_q_a[22]_PORT_A_data_out[0];


--H1L483 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3149
H1L483 = AMPP_FUNCTION(DB1_q_a[22], EB1_q_a[22], P1L14, M1L10);


--K1_dbs_8_reg_segment_2[6] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[6]
K1_dbs_8_reg_segment_2[6] = DFFEAS(W1_incoming_tri_state_bridge_0_data[6], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--TB1_ram_block1a22 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a22
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a22_PORT_A_data_in = J1L33;
TB1_ram_block1a22_PORT_A_data_in_reg = DFFE(TB1_ram_block1a22_PORT_A_data_in, TB1_ram_block1a22_clock_0, , , TB1_ram_block1a22_clock_enable_0);
TB1_ram_block1a22_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a22_PORT_A_address_reg = DFFE(TB1_ram_block1a22_PORT_A_address, TB1_ram_block1a22_clock_0, , , TB1_ram_block1a22_clock_enable_0);
TB1_ram_block1a22_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a22_PORT_B_address_reg = DFFE(TB1_ram_block1a22_PORT_B_address, TB1_ram_block1a22_clock_0, , , TB1_ram_block1a22_clock_enable_0);
TB1_ram_block1a22_PORT_A_write_enable = UB1L3;
TB1_ram_block1a22_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a22_PORT_A_write_enable, TB1_ram_block1a22_clock_0, , , TB1_ram_block1a22_clock_enable_0);
TB1_ram_block1a22_PORT_A_byte_mask = T1L52;
TB1_ram_block1a22_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a22_PORT_A_byte_mask, TB1_ram_block1a22_clock_0, , , TB1_ram_block1a22_clock_enable_0);
TB1_ram_block1a22_clock_0 = CLOCK_50;
TB1_ram_block1a22_clock_enable_0 = !T1L38;
TB1_ram_block1a22_PORT_A_data_out = MEMORY(TB1_ram_block1a22_PORT_A_data_in_reg, , TB1_ram_block1a22_PORT_A_address_reg, TB1_ram_block1a22_PORT_B_address_reg, TB1_ram_block1a22_PORT_A_write_enable_reg, , TB1_ram_block1a22_PORT_A_byte_mask_reg, , TB1_ram_block1a22_clock_0, , TB1_ram_block1a22_clock_enable_0, , , );
TB1_ram_block1a22 = TB1_ram_block1a22_PORT_A_data_out[0];


--TB1_ram_block1a6 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a6
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a6_PORT_A_data_in = J1L33;
TB1_ram_block1a6_PORT_A_data_in_reg = DFFE(TB1_ram_block1a6_PORT_A_data_in, TB1_ram_block1a6_clock_0, , , TB1_ram_block1a6_clock_enable_0);
TB1_ram_block1a6_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a6_PORT_A_address_reg = DFFE(TB1_ram_block1a6_PORT_A_address, TB1_ram_block1a6_clock_0, , , TB1_ram_block1a6_clock_enable_0);
TB1_ram_block1a6_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a6_PORT_B_address_reg = DFFE(TB1_ram_block1a6_PORT_B_address, TB1_ram_block1a6_clock_0, , , TB1_ram_block1a6_clock_enable_0);
TB1_ram_block1a6_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a6_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a6_PORT_A_write_enable, TB1_ram_block1a6_clock_0, , , TB1_ram_block1a6_clock_enable_0);
TB1_ram_block1a6_PORT_A_byte_mask = T1L52;
TB1_ram_block1a6_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a6_PORT_A_byte_mask, TB1_ram_block1a6_clock_0, , , TB1_ram_block1a6_clock_enable_0);
TB1_ram_block1a6_clock_0 = CLOCK_50;
TB1_ram_block1a6_clock_enable_0 = T1L38;
TB1_ram_block1a6_PORT_A_data_out = MEMORY(TB1_ram_block1a6_PORT_A_data_in_reg, , TB1_ram_block1a6_PORT_A_address_reg, TB1_ram_block1a6_PORT_B_address_reg, TB1_ram_block1a6_PORT_A_write_enable_reg, , TB1_ram_block1a6_PORT_A_byte_mask_reg, , TB1_ram_block1a6_clock_0, , TB1_ram_block1a6_clock_enable_0, , , );
TB1_ram_block1a6 = TB1_ram_block1a6_PORT_A_data_out[0];


--VB1L7 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[6]~438
VB1L7 = TB1_address_reg_a[0] & TB1_ram_block1a22 # !TB1_address_reg_a[0] & (TB1_ram_block1a6);


--H1L484 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3150
H1L484 = AMPP_FUNCTION(H1L483, H1L520, VB1L7, T1L17);


--H1_av_ld_byte2_data[1] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[1]
H1_av_ld_byte2_data[1] = AMPP_FUNCTION(CLOCK_50, H1L1042, H1_av_ld_byte3_data[1], E1_data_out, !H1L1103);


--DB1_q_a[7] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[7]_PORT_A_data_in = H1_d_writedata[7];
DB1_q_a[7]_PORT_A_data_in_reg = DFFE(DB1_q_a[7]_PORT_A_data_in, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[7]_PORT_A_address_reg = DFFE(DB1_q_a[7]_PORT_A_address, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[7]_PORT_B_address_reg = DFFE(DB1_q_a[7]_PORT_B_address, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_A_write_enable = L1L1;
DB1_q_a[7]_PORT_A_write_enable_reg = DFFE(DB1_q_a[7]_PORT_A_write_enable, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_PORT_A_byte_mask = M1L22;
DB1_q_a[7]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[7]_PORT_A_byte_mask, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_clock_0 = CLOCK_50;
DB1_q_a[7]_PORT_A_data_out = MEMORY(DB1_q_a[7]_PORT_A_data_in_reg, , DB1_q_a[7]_PORT_A_address_reg, DB1_q_a[7]_PORT_B_address_reg, DB1_q_a[7]_PORT_A_write_enable_reg, , DB1_q_a[7]_PORT_A_byte_mask_reg, , DB1_q_a[7]_clock_0, , , , , );
DB1_q_a[7] = DB1_q_a[7]_PORT_A_data_out[0];


--EB1_q_a[7] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[7]_PORT_A_data_in = H1_d_writedata[7];
EB1_q_a[7]_PORT_A_data_in_reg = DFFE(EB1_q_a[7]_PORT_A_data_in, EB1_q_a[7]_clock_0, , , );
EB1_q_a[7]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[7]_PORT_A_address_reg = DFFE(EB1_q_a[7]_PORT_A_address, EB1_q_a[7]_clock_0, , , );
EB1_q_a[7]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[7]_PORT_B_address_reg = DFFE(EB1_q_a[7]_PORT_B_address, EB1_q_a[7]_clock_0, , , );
EB1_q_a[7]_PORT_A_write_enable = GND;
EB1_q_a[7]_PORT_A_write_enable_reg = DFFE(EB1_q_a[7]_PORT_A_write_enable, EB1_q_a[7]_clock_0, , , );
EB1_q_a[7]_PORT_A_byte_mask = P1L28;
EB1_q_a[7]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[7]_PORT_A_byte_mask, EB1_q_a[7]_clock_0, , , );
EB1_q_a[7]_clock_0 = CLOCK_50;
EB1_q_a[7]_PORT_A_data_out = MEMORY(EB1_q_a[7]_PORT_A_data_in_reg, , EB1_q_a[7]_PORT_A_address_reg, EB1_q_a[7]_PORT_B_address_reg, EB1_q_a[7]_PORT_A_write_enable_reg, , EB1_q_a[7]_PORT_A_byte_mask_reg, , EB1_q_a[7]_clock_0, , , , , );
EB1_q_a[7] = EB1_q_a[7]_PORT_A_data_out[0];


--H1L485 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3151
H1L485 = AMPP_FUNCTION(DB1_q_a[7], EB1_q_a[7], P1L14, M1L10);


--K1_dbs_8_reg_segment_0[7] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[7]
K1_dbs_8_reg_segment_0[7] = DFFEAS(W1_incoming_tri_state_bridge_0_data[7], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[7] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[7]
K1_dbs_16_reg_segment_0[7] = DFFEAS(VB1L8, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L486 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3152
H1L486 = AMPP_FUNCTION(H1L485, H1L521, K1_dbs_16_reg_segment_0[7], T1L17);


--H1_av_ld_byte2_data[0] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0]
H1_av_ld_byte2_data[0] = AMPP_FUNCTION(CLOCK_50, H1L1039, H1_av_ld_byte3_data[0], E1_data_out, !H1L1103);


--DB1_q_a[6] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[6]_PORT_A_data_in = H1_d_writedata[6];
DB1_q_a[6]_PORT_A_data_in_reg = DFFE(DB1_q_a[6]_PORT_A_data_in, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[6]_PORT_A_address_reg = DFFE(DB1_q_a[6]_PORT_A_address, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[6]_PORT_B_address_reg = DFFE(DB1_q_a[6]_PORT_B_address, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_A_write_enable = L1L1;
DB1_q_a[6]_PORT_A_write_enable_reg = DFFE(DB1_q_a[6]_PORT_A_write_enable, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_PORT_A_byte_mask = M1L22;
DB1_q_a[6]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[6]_PORT_A_byte_mask, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_clock_0 = CLOCK_50;
DB1_q_a[6]_PORT_A_data_out = MEMORY(DB1_q_a[6]_PORT_A_data_in_reg, , DB1_q_a[6]_PORT_A_address_reg, DB1_q_a[6]_PORT_B_address_reg, DB1_q_a[6]_PORT_A_write_enable_reg, , DB1_q_a[6]_PORT_A_byte_mask_reg, , DB1_q_a[6]_clock_0, , , , , );
DB1_q_a[6] = DB1_q_a[6]_PORT_A_data_out[0];


--EB1_q_a[6] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[6]_PORT_A_data_in = H1_d_writedata[6];
EB1_q_a[6]_PORT_A_data_in_reg = DFFE(EB1_q_a[6]_PORT_A_data_in, EB1_q_a[6]_clock_0, , , );
EB1_q_a[6]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[6]_PORT_A_address_reg = DFFE(EB1_q_a[6]_PORT_A_address, EB1_q_a[6]_clock_0, , , );
EB1_q_a[6]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[6]_PORT_B_address_reg = DFFE(EB1_q_a[6]_PORT_B_address, EB1_q_a[6]_clock_0, , , );
EB1_q_a[6]_PORT_A_write_enable = GND;
EB1_q_a[6]_PORT_A_write_enable_reg = DFFE(EB1_q_a[6]_PORT_A_write_enable, EB1_q_a[6]_clock_0, , , );
EB1_q_a[6]_PORT_A_byte_mask = P1L28;
EB1_q_a[6]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[6]_PORT_A_byte_mask, EB1_q_a[6]_clock_0, , , );
EB1_q_a[6]_clock_0 = CLOCK_50;
EB1_q_a[6]_PORT_A_data_out = MEMORY(EB1_q_a[6]_PORT_A_data_in_reg, , EB1_q_a[6]_PORT_A_address_reg, EB1_q_a[6]_PORT_B_address_reg, EB1_q_a[6]_PORT_A_write_enable_reg, , EB1_q_a[6]_PORT_A_byte_mask_reg, , EB1_q_a[6]_clock_0, , , , , );
EB1_q_a[6] = EB1_q_a[6]_PORT_A_data_out[0];


--H1L487 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3153
H1L487 = AMPP_FUNCTION(DB1_q_a[6], EB1_q_a[6], P1L14, M1L10);


--K1_dbs_8_reg_segment_0[6] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_0[6]
K1_dbs_8_reg_segment_0[6] = DFFEAS(W1_incoming_tri_state_bridge_0_data[6], CLOCK_50, E1_data_out,  , K1L3,  ,  ,  ,  );


--K1_dbs_16_reg_segment_0[6] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_16_reg_segment_0[6]
K1_dbs_16_reg_segment_0[6] = DFFEAS(VB1L7, CLOCK_50, E1_data_out,  , K1L2,  ,  ,  ,  );


--H1L488 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3154
H1L488 = AMPP_FUNCTION(H1L487, H1L522, K1_dbs_16_reg_segment_0[6], T1L17);


--DB1_q_a[20] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[20]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[20]_PORT_A_data_in = H1_d_writedata[20];
DB1_q_a[20]_PORT_A_data_in_reg = DFFE(DB1_q_a[20]_PORT_A_data_in, DB1_q_a[20]_clock_0, , , );
DB1_q_a[20]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[20]_PORT_A_address_reg = DFFE(DB1_q_a[20]_PORT_A_address, DB1_q_a[20]_clock_0, , , );
DB1_q_a[20]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[20]_PORT_B_address_reg = DFFE(DB1_q_a[20]_PORT_B_address, DB1_q_a[20]_clock_0, , , );
DB1_q_a[20]_PORT_A_write_enable = L1L1;
DB1_q_a[20]_PORT_A_write_enable_reg = DFFE(DB1_q_a[20]_PORT_A_write_enable, DB1_q_a[20]_clock_0, , , );
DB1_q_a[20]_PORT_A_byte_mask = M1L24;
DB1_q_a[20]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[20]_PORT_A_byte_mask, DB1_q_a[20]_clock_0, , , );
DB1_q_a[20]_clock_0 = CLOCK_50;
DB1_q_a[20]_PORT_A_data_out = MEMORY(DB1_q_a[20]_PORT_A_data_in_reg, , DB1_q_a[20]_PORT_A_address_reg, DB1_q_a[20]_PORT_B_address_reg, DB1_q_a[20]_PORT_A_write_enable_reg, , DB1_q_a[20]_PORT_A_byte_mask_reg, , DB1_q_a[20]_clock_0, , , , , );
DB1_q_a[20] = DB1_q_a[20]_PORT_A_data_out[0];


--EB1_q_a[20] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[20]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[20]_PORT_A_data_in = H1_d_writedata[20];
EB1_q_a[20]_PORT_A_data_in_reg = DFFE(EB1_q_a[20]_PORT_A_data_in, EB1_q_a[20]_clock_0, , , );
EB1_q_a[20]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[20]_PORT_A_address_reg = DFFE(EB1_q_a[20]_PORT_A_address, EB1_q_a[20]_clock_0, , , );
EB1_q_a[20]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[20]_PORT_B_address_reg = DFFE(EB1_q_a[20]_PORT_B_address, EB1_q_a[20]_clock_0, , , );
EB1_q_a[20]_PORT_A_write_enable = GND;
EB1_q_a[20]_PORT_A_write_enable_reg = DFFE(EB1_q_a[20]_PORT_A_write_enable, EB1_q_a[20]_clock_0, , , );
EB1_q_a[20]_PORT_A_byte_mask = P1L30;
EB1_q_a[20]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[20]_PORT_A_byte_mask, EB1_q_a[20]_clock_0, , , );
EB1_q_a[20]_clock_0 = CLOCK_50;
EB1_q_a[20]_PORT_A_data_out = MEMORY(EB1_q_a[20]_PORT_A_data_in_reg, , EB1_q_a[20]_PORT_A_address_reg, EB1_q_a[20]_PORT_B_address_reg, EB1_q_a[20]_PORT_A_write_enable_reg, , EB1_q_a[20]_PORT_A_byte_mask_reg, , EB1_q_a[20]_clock_0, , , , , );
EB1_q_a[20] = EB1_q_a[20]_PORT_A_data_out[0];


--H1L489 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3155
H1L489 = AMPP_FUNCTION(DB1_q_a[20], EB1_q_a[20], P1L14, M1L10);


--TB1_ram_block1a20 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a20
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a20_PORT_A_data_in = J1L31;
TB1_ram_block1a20_PORT_A_data_in_reg = DFFE(TB1_ram_block1a20_PORT_A_data_in, TB1_ram_block1a20_clock_0, , , TB1_ram_block1a20_clock_enable_0);
TB1_ram_block1a20_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a20_PORT_A_address_reg = DFFE(TB1_ram_block1a20_PORT_A_address, TB1_ram_block1a20_clock_0, , , TB1_ram_block1a20_clock_enable_0);
TB1_ram_block1a20_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a20_PORT_B_address_reg = DFFE(TB1_ram_block1a20_PORT_B_address, TB1_ram_block1a20_clock_0, , , TB1_ram_block1a20_clock_enable_0);
TB1_ram_block1a20_PORT_A_write_enable = UB1L3;
TB1_ram_block1a20_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a20_PORT_A_write_enable, TB1_ram_block1a20_clock_0, , , TB1_ram_block1a20_clock_enable_0);
TB1_ram_block1a20_PORT_A_byte_mask = T1L52;
TB1_ram_block1a20_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a20_PORT_A_byte_mask, TB1_ram_block1a20_clock_0, , , TB1_ram_block1a20_clock_enable_0);
TB1_ram_block1a20_clock_0 = CLOCK_50;
TB1_ram_block1a20_clock_enable_0 = !T1L38;
TB1_ram_block1a20_PORT_A_data_out = MEMORY(TB1_ram_block1a20_PORT_A_data_in_reg, , TB1_ram_block1a20_PORT_A_address_reg, TB1_ram_block1a20_PORT_B_address_reg, TB1_ram_block1a20_PORT_A_write_enable_reg, , TB1_ram_block1a20_PORT_A_byte_mask_reg, , TB1_ram_block1a20_clock_0, , TB1_ram_block1a20_clock_enable_0, , , );
TB1_ram_block1a20 = TB1_ram_block1a20_PORT_A_data_out[0];


--TB1_ram_block1a4 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a4
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a4_PORT_A_data_in = J1L31;
TB1_ram_block1a4_PORT_A_data_in_reg = DFFE(TB1_ram_block1a4_PORT_A_data_in, TB1_ram_block1a4_clock_0, , , TB1_ram_block1a4_clock_enable_0);
TB1_ram_block1a4_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a4_PORT_A_address_reg = DFFE(TB1_ram_block1a4_PORT_A_address, TB1_ram_block1a4_clock_0, , , TB1_ram_block1a4_clock_enable_0);
TB1_ram_block1a4_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a4_PORT_B_address_reg = DFFE(TB1_ram_block1a4_PORT_B_address, TB1_ram_block1a4_clock_0, , , TB1_ram_block1a4_clock_enable_0);
TB1_ram_block1a4_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a4_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a4_PORT_A_write_enable, TB1_ram_block1a4_clock_0, , , TB1_ram_block1a4_clock_enable_0);
TB1_ram_block1a4_PORT_A_byte_mask = T1L52;
TB1_ram_block1a4_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a4_PORT_A_byte_mask, TB1_ram_block1a4_clock_0, , , TB1_ram_block1a4_clock_enable_0);
TB1_ram_block1a4_clock_0 = CLOCK_50;
TB1_ram_block1a4_clock_enable_0 = T1L38;
TB1_ram_block1a4_PORT_A_data_out = MEMORY(TB1_ram_block1a4_PORT_A_data_in_reg, , TB1_ram_block1a4_PORT_A_address_reg, TB1_ram_block1a4_PORT_B_address_reg, TB1_ram_block1a4_PORT_A_write_enable_reg, , TB1_ram_block1a4_PORT_A_byte_mask_reg, , TB1_ram_block1a4_clock_0, , TB1_ram_block1a4_clock_enable_0, , , );
TB1_ram_block1a4 = TB1_ram_block1a4_PORT_A_data_out[0];


--VB1L5 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[4]~439
VB1L5 = TB1_address_reg_a[0] & TB1_ram_block1a20 # !TB1_address_reg_a[0] & (TB1_ram_block1a4);


--K1_dbs_8_reg_segment_2[4] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[4]
K1_dbs_8_reg_segment_2[4] = DFFEAS(W1_incoming_tri_state_bridge_0_data[4], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--H1L490 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3156
H1L490 = AMPP_FUNCTION(VB1L5, K1_dbs_8_reg_segment_2[4], W1L34, T1L17);


--H1L491 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3157
H1L491 = AMPP_FUNCTION(H1L1171, H1L489, H1L490);


--H1_av_ld_byte1_data[7] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[7]
H1_av_ld_byte1_data[7] = AMPP_FUNCTION(CLOCK_50, H1L1034, H1_av_ld_byte2_data[7], E1_data_out, !H1L1103, H1L1036);


--DB1_q_a[19] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[19]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[19]_PORT_A_data_in = H1_d_writedata[19];
DB1_q_a[19]_PORT_A_data_in_reg = DFFE(DB1_q_a[19]_PORT_A_data_in, DB1_q_a[19]_clock_0, , , );
DB1_q_a[19]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[19]_PORT_A_address_reg = DFFE(DB1_q_a[19]_PORT_A_address, DB1_q_a[19]_clock_0, , , );
DB1_q_a[19]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[19]_PORT_B_address_reg = DFFE(DB1_q_a[19]_PORT_B_address, DB1_q_a[19]_clock_0, , , );
DB1_q_a[19]_PORT_A_write_enable = L1L1;
DB1_q_a[19]_PORT_A_write_enable_reg = DFFE(DB1_q_a[19]_PORT_A_write_enable, DB1_q_a[19]_clock_0, , , );
DB1_q_a[19]_PORT_A_byte_mask = M1L24;
DB1_q_a[19]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[19]_PORT_A_byte_mask, DB1_q_a[19]_clock_0, , , );
DB1_q_a[19]_clock_0 = CLOCK_50;
DB1_q_a[19]_PORT_A_data_out = MEMORY(DB1_q_a[19]_PORT_A_data_in_reg, , DB1_q_a[19]_PORT_A_address_reg, DB1_q_a[19]_PORT_B_address_reg, DB1_q_a[19]_PORT_A_write_enable_reg, , DB1_q_a[19]_PORT_A_byte_mask_reg, , DB1_q_a[19]_clock_0, , , , , );
DB1_q_a[19] = DB1_q_a[19]_PORT_A_data_out[0];


--EB1_q_a[19] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[19]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[19]_PORT_A_data_in = H1_d_writedata[19];
EB1_q_a[19]_PORT_A_data_in_reg = DFFE(EB1_q_a[19]_PORT_A_data_in, EB1_q_a[19]_clock_0, , , );
EB1_q_a[19]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[19]_PORT_A_address_reg = DFFE(EB1_q_a[19]_PORT_A_address, EB1_q_a[19]_clock_0, , , );
EB1_q_a[19]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[19]_PORT_B_address_reg = DFFE(EB1_q_a[19]_PORT_B_address, EB1_q_a[19]_clock_0, , , );
EB1_q_a[19]_PORT_A_write_enable = GND;
EB1_q_a[19]_PORT_A_write_enable_reg = DFFE(EB1_q_a[19]_PORT_A_write_enable, EB1_q_a[19]_clock_0, , , );
EB1_q_a[19]_PORT_A_byte_mask = P1L30;
EB1_q_a[19]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[19]_PORT_A_byte_mask, EB1_q_a[19]_clock_0, , , );
EB1_q_a[19]_clock_0 = CLOCK_50;
EB1_q_a[19]_PORT_A_data_out = MEMORY(EB1_q_a[19]_PORT_A_data_in_reg, , EB1_q_a[19]_PORT_A_address_reg, EB1_q_a[19]_PORT_B_address_reg, EB1_q_a[19]_PORT_A_write_enable_reg, , EB1_q_a[19]_PORT_A_byte_mask_reg, , EB1_q_a[19]_clock_0, , , , , );
EB1_q_a[19] = EB1_q_a[19]_PORT_A_data_out[0];


--H1L492 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3158
H1L492 = AMPP_FUNCTION(DB1_q_a[19], EB1_q_a[19], P1L14, M1L10);


--TB1_ram_block1a19 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a19
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a19_PORT_A_data_in = J1L30;
TB1_ram_block1a19_PORT_A_data_in_reg = DFFE(TB1_ram_block1a19_PORT_A_data_in, TB1_ram_block1a19_clock_0, , , TB1_ram_block1a19_clock_enable_0);
TB1_ram_block1a19_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a19_PORT_A_address_reg = DFFE(TB1_ram_block1a19_PORT_A_address, TB1_ram_block1a19_clock_0, , , TB1_ram_block1a19_clock_enable_0);
TB1_ram_block1a19_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a19_PORT_B_address_reg = DFFE(TB1_ram_block1a19_PORT_B_address, TB1_ram_block1a19_clock_0, , , TB1_ram_block1a19_clock_enable_0);
TB1_ram_block1a19_PORT_A_write_enable = UB1L3;
TB1_ram_block1a19_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a19_PORT_A_write_enable, TB1_ram_block1a19_clock_0, , , TB1_ram_block1a19_clock_enable_0);
TB1_ram_block1a19_PORT_A_byte_mask = T1L52;
TB1_ram_block1a19_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a19_PORT_A_byte_mask, TB1_ram_block1a19_clock_0, , , TB1_ram_block1a19_clock_enable_0);
TB1_ram_block1a19_clock_0 = CLOCK_50;
TB1_ram_block1a19_clock_enable_0 = !T1L38;
TB1_ram_block1a19_PORT_A_data_out = MEMORY(TB1_ram_block1a19_PORT_A_data_in_reg, , TB1_ram_block1a19_PORT_A_address_reg, TB1_ram_block1a19_PORT_B_address_reg, TB1_ram_block1a19_PORT_A_write_enable_reg, , TB1_ram_block1a19_PORT_A_byte_mask_reg, , TB1_ram_block1a19_clock_0, , TB1_ram_block1a19_clock_enable_0, , , );
TB1_ram_block1a19 = TB1_ram_block1a19_PORT_A_data_out[0];


--TB1_ram_block1a3 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a3
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a3_PORT_A_data_in = J1L30;
TB1_ram_block1a3_PORT_A_data_in_reg = DFFE(TB1_ram_block1a3_PORT_A_data_in, TB1_ram_block1a3_clock_0, , , TB1_ram_block1a3_clock_enable_0);
TB1_ram_block1a3_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a3_PORT_A_address_reg = DFFE(TB1_ram_block1a3_PORT_A_address, TB1_ram_block1a3_clock_0, , , TB1_ram_block1a3_clock_enable_0);
TB1_ram_block1a3_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a3_PORT_B_address_reg = DFFE(TB1_ram_block1a3_PORT_B_address, TB1_ram_block1a3_clock_0, , , TB1_ram_block1a3_clock_enable_0);
TB1_ram_block1a3_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a3_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a3_PORT_A_write_enable, TB1_ram_block1a3_clock_0, , , TB1_ram_block1a3_clock_enable_0);
TB1_ram_block1a3_PORT_A_byte_mask = T1L52;
TB1_ram_block1a3_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a3_PORT_A_byte_mask, TB1_ram_block1a3_clock_0, , , TB1_ram_block1a3_clock_enable_0);
TB1_ram_block1a3_clock_0 = CLOCK_50;
TB1_ram_block1a3_clock_enable_0 = T1L38;
TB1_ram_block1a3_PORT_A_data_out = MEMORY(TB1_ram_block1a3_PORT_A_data_in_reg, , TB1_ram_block1a3_PORT_A_address_reg, TB1_ram_block1a3_PORT_B_address_reg, TB1_ram_block1a3_PORT_A_write_enable_reg, , TB1_ram_block1a3_PORT_A_byte_mask_reg, , TB1_ram_block1a3_clock_0, , TB1_ram_block1a3_clock_enable_0, , , );
TB1_ram_block1a3 = TB1_ram_block1a3_PORT_A_data_out[0];


--VB1L4 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[3]~440
VB1L4 = TB1_address_reg_a[0] & TB1_ram_block1a19 # !TB1_address_reg_a[0] & (TB1_ram_block1a3);


--K1_dbs_8_reg_segment_2[3] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[3]
K1_dbs_8_reg_segment_2[3] = DFFEAS(W1_incoming_tri_state_bridge_0_data[3], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--H1L493 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3159
H1L493 = AMPP_FUNCTION(VB1L4, K1_dbs_8_reg_segment_2[3], W1L34, T1L17);


--H1L494 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3160
H1L494 = AMPP_FUNCTION(H1L1171, H1L492, H1L493);


--H1_av_ld_byte1_data[6] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[6]
H1_av_ld_byte1_data[6] = AMPP_FUNCTION(CLOCK_50, H1L1031, H1_av_ld_byte2_data[6], E1_data_out, !H1L1103, H1L1036);


--DB1_q_a[18] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[18]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[18]_PORT_A_data_in = H1_d_writedata[18];
DB1_q_a[18]_PORT_A_data_in_reg = DFFE(DB1_q_a[18]_PORT_A_data_in, DB1_q_a[18]_clock_0, , , );
DB1_q_a[18]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[18]_PORT_A_address_reg = DFFE(DB1_q_a[18]_PORT_A_address, DB1_q_a[18]_clock_0, , , );
DB1_q_a[18]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[18]_PORT_B_address_reg = DFFE(DB1_q_a[18]_PORT_B_address, DB1_q_a[18]_clock_0, , , );
DB1_q_a[18]_PORT_A_write_enable = L1L1;
DB1_q_a[18]_PORT_A_write_enable_reg = DFFE(DB1_q_a[18]_PORT_A_write_enable, DB1_q_a[18]_clock_0, , , );
DB1_q_a[18]_PORT_A_byte_mask = M1L24;
DB1_q_a[18]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[18]_PORT_A_byte_mask, DB1_q_a[18]_clock_0, , , );
DB1_q_a[18]_clock_0 = CLOCK_50;
DB1_q_a[18]_PORT_A_data_out = MEMORY(DB1_q_a[18]_PORT_A_data_in_reg, , DB1_q_a[18]_PORT_A_address_reg, DB1_q_a[18]_PORT_B_address_reg, DB1_q_a[18]_PORT_A_write_enable_reg, , DB1_q_a[18]_PORT_A_byte_mask_reg, , DB1_q_a[18]_clock_0, , , , , );
DB1_q_a[18] = DB1_q_a[18]_PORT_A_data_out[0];


--EB1_q_a[18] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[18]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[18]_PORT_A_data_in = H1_d_writedata[18];
EB1_q_a[18]_PORT_A_data_in_reg = DFFE(EB1_q_a[18]_PORT_A_data_in, EB1_q_a[18]_clock_0, , , );
EB1_q_a[18]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[18]_PORT_A_address_reg = DFFE(EB1_q_a[18]_PORT_A_address, EB1_q_a[18]_clock_0, , , );
EB1_q_a[18]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[18]_PORT_B_address_reg = DFFE(EB1_q_a[18]_PORT_B_address, EB1_q_a[18]_clock_0, , , );
EB1_q_a[18]_PORT_A_write_enable = GND;
EB1_q_a[18]_PORT_A_write_enable_reg = DFFE(EB1_q_a[18]_PORT_A_write_enable, EB1_q_a[18]_clock_0, , , );
EB1_q_a[18]_PORT_A_byte_mask = P1L30;
EB1_q_a[18]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[18]_PORT_A_byte_mask, EB1_q_a[18]_clock_0, , , );
EB1_q_a[18]_clock_0 = CLOCK_50;
EB1_q_a[18]_PORT_A_data_out = MEMORY(EB1_q_a[18]_PORT_A_data_in_reg, , EB1_q_a[18]_PORT_A_address_reg, EB1_q_a[18]_PORT_B_address_reg, EB1_q_a[18]_PORT_A_write_enable_reg, , EB1_q_a[18]_PORT_A_byte_mask_reg, , EB1_q_a[18]_clock_0, , , , , );
EB1_q_a[18] = EB1_q_a[18]_PORT_A_data_out[0];


--H1L495 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3161
H1L495 = AMPP_FUNCTION(DB1_q_a[18], EB1_q_a[18], P1L14, M1L10);


--K1_dbs_8_reg_segment_2[2] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[2]
K1_dbs_8_reg_segment_2[2] = DFFEAS(W1_incoming_tri_state_bridge_0_data[2], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--TB1_ram_block1a18 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a18
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a18_PORT_A_data_in = J1L29;
TB1_ram_block1a18_PORT_A_data_in_reg = DFFE(TB1_ram_block1a18_PORT_A_data_in, TB1_ram_block1a18_clock_0, , , TB1_ram_block1a18_clock_enable_0);
TB1_ram_block1a18_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a18_PORT_A_address_reg = DFFE(TB1_ram_block1a18_PORT_A_address, TB1_ram_block1a18_clock_0, , , TB1_ram_block1a18_clock_enable_0);
TB1_ram_block1a18_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a18_PORT_B_address_reg = DFFE(TB1_ram_block1a18_PORT_B_address, TB1_ram_block1a18_clock_0, , , TB1_ram_block1a18_clock_enable_0);
TB1_ram_block1a18_PORT_A_write_enable = UB1L3;
TB1_ram_block1a18_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a18_PORT_A_write_enable, TB1_ram_block1a18_clock_0, , , TB1_ram_block1a18_clock_enable_0);
TB1_ram_block1a18_PORT_A_byte_mask = T1L52;
TB1_ram_block1a18_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a18_PORT_A_byte_mask, TB1_ram_block1a18_clock_0, , , TB1_ram_block1a18_clock_enable_0);
TB1_ram_block1a18_clock_0 = CLOCK_50;
TB1_ram_block1a18_clock_enable_0 = !T1L38;
TB1_ram_block1a18_PORT_A_data_out = MEMORY(TB1_ram_block1a18_PORT_A_data_in_reg, , TB1_ram_block1a18_PORT_A_address_reg, TB1_ram_block1a18_PORT_B_address_reg, TB1_ram_block1a18_PORT_A_write_enable_reg, , TB1_ram_block1a18_PORT_A_byte_mask_reg, , TB1_ram_block1a18_clock_0, , TB1_ram_block1a18_clock_enable_0, , , );
TB1_ram_block1a18 = TB1_ram_block1a18_PORT_A_data_out[0];


--TB1_ram_block1a2 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a2
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a2_PORT_A_data_in = J1L29;
TB1_ram_block1a2_PORT_A_data_in_reg = DFFE(TB1_ram_block1a2_PORT_A_data_in, TB1_ram_block1a2_clock_0, , , TB1_ram_block1a2_clock_enable_0);
TB1_ram_block1a2_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a2_PORT_A_address_reg = DFFE(TB1_ram_block1a2_PORT_A_address, TB1_ram_block1a2_clock_0, , , TB1_ram_block1a2_clock_enable_0);
TB1_ram_block1a2_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a2_PORT_B_address_reg = DFFE(TB1_ram_block1a2_PORT_B_address, TB1_ram_block1a2_clock_0, , , TB1_ram_block1a2_clock_enable_0);
TB1_ram_block1a2_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a2_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a2_PORT_A_write_enable, TB1_ram_block1a2_clock_0, , , TB1_ram_block1a2_clock_enable_0);
TB1_ram_block1a2_PORT_A_byte_mask = T1L52;
TB1_ram_block1a2_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a2_PORT_A_byte_mask, TB1_ram_block1a2_clock_0, , , TB1_ram_block1a2_clock_enable_0);
TB1_ram_block1a2_clock_0 = CLOCK_50;
TB1_ram_block1a2_clock_enable_0 = T1L38;
TB1_ram_block1a2_PORT_A_data_out = MEMORY(TB1_ram_block1a2_PORT_A_data_in_reg, , TB1_ram_block1a2_PORT_A_address_reg, TB1_ram_block1a2_PORT_B_address_reg, TB1_ram_block1a2_PORT_A_write_enable_reg, , TB1_ram_block1a2_PORT_A_byte_mask_reg, , TB1_ram_block1a2_clock_0, , TB1_ram_block1a2_clock_enable_0, , , );
TB1_ram_block1a2 = TB1_ram_block1a2_PORT_A_data_out[0];


--VB1L3 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[2]~441
VB1L3 = TB1_address_reg_a[0] & TB1_ram_block1a18 # !TB1_address_reg_a[0] & (TB1_ram_block1a2);


--H1L496 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3162
H1L496 = AMPP_FUNCTION(H1L495, H1L523, VB1L3, T1L17);


--H1_av_ld_byte1_data[5] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[5]
H1_av_ld_byte1_data[5] = AMPP_FUNCTION(CLOCK_50, H1L1028, H1_av_ld_byte2_data[5], E1_data_out, !H1L1103, H1L1036);


--DB1_q_a[17] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[17]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[17]_PORT_A_data_in = H1_d_writedata[17];
DB1_q_a[17]_PORT_A_data_in_reg = DFFE(DB1_q_a[17]_PORT_A_data_in, DB1_q_a[17]_clock_0, , , );
DB1_q_a[17]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[17]_PORT_A_address_reg = DFFE(DB1_q_a[17]_PORT_A_address, DB1_q_a[17]_clock_0, , , );
DB1_q_a[17]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[17]_PORT_B_address_reg = DFFE(DB1_q_a[17]_PORT_B_address, DB1_q_a[17]_clock_0, , , );
DB1_q_a[17]_PORT_A_write_enable = L1L1;
DB1_q_a[17]_PORT_A_write_enable_reg = DFFE(DB1_q_a[17]_PORT_A_write_enable, DB1_q_a[17]_clock_0, , , );
DB1_q_a[17]_PORT_A_byte_mask = M1L24;
DB1_q_a[17]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[17]_PORT_A_byte_mask, DB1_q_a[17]_clock_0, , , );
DB1_q_a[17]_clock_0 = CLOCK_50;
DB1_q_a[17]_PORT_A_data_out = MEMORY(DB1_q_a[17]_PORT_A_data_in_reg, , DB1_q_a[17]_PORT_A_address_reg, DB1_q_a[17]_PORT_B_address_reg, DB1_q_a[17]_PORT_A_write_enable_reg, , DB1_q_a[17]_PORT_A_byte_mask_reg, , DB1_q_a[17]_clock_0, , , , , );
DB1_q_a[17] = DB1_q_a[17]_PORT_A_data_out[0];


--EB1_q_a[17] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[17]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[17]_PORT_A_data_in = H1_d_writedata[17];
EB1_q_a[17]_PORT_A_data_in_reg = DFFE(EB1_q_a[17]_PORT_A_data_in, EB1_q_a[17]_clock_0, , , );
EB1_q_a[17]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[17]_PORT_A_address_reg = DFFE(EB1_q_a[17]_PORT_A_address, EB1_q_a[17]_clock_0, , , );
EB1_q_a[17]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[17]_PORT_B_address_reg = DFFE(EB1_q_a[17]_PORT_B_address, EB1_q_a[17]_clock_0, , , );
EB1_q_a[17]_PORT_A_write_enable = GND;
EB1_q_a[17]_PORT_A_write_enable_reg = DFFE(EB1_q_a[17]_PORT_A_write_enable, EB1_q_a[17]_clock_0, , , );
EB1_q_a[17]_PORT_A_byte_mask = P1L30;
EB1_q_a[17]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[17]_PORT_A_byte_mask, EB1_q_a[17]_clock_0, , , );
EB1_q_a[17]_clock_0 = CLOCK_50;
EB1_q_a[17]_PORT_A_data_out = MEMORY(EB1_q_a[17]_PORT_A_data_in_reg, , EB1_q_a[17]_PORT_A_address_reg, EB1_q_a[17]_PORT_B_address_reg, EB1_q_a[17]_PORT_A_write_enable_reg, , EB1_q_a[17]_PORT_A_byte_mask_reg, , EB1_q_a[17]_clock_0, , , , , );
EB1_q_a[17] = EB1_q_a[17]_PORT_A_data_out[0];


--H1L497 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3163
H1L497 = AMPP_FUNCTION(DB1_q_a[17], EB1_q_a[17], P1L14, M1L10);


--TB1_ram_block1a17 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a17
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a17_PORT_A_data_in = J1L28;
TB1_ram_block1a17_PORT_A_data_in_reg = DFFE(TB1_ram_block1a17_PORT_A_data_in, TB1_ram_block1a17_clock_0, , , TB1_ram_block1a17_clock_enable_0);
TB1_ram_block1a17_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a17_PORT_A_address_reg = DFFE(TB1_ram_block1a17_PORT_A_address, TB1_ram_block1a17_clock_0, , , TB1_ram_block1a17_clock_enable_0);
TB1_ram_block1a17_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a17_PORT_B_address_reg = DFFE(TB1_ram_block1a17_PORT_B_address, TB1_ram_block1a17_clock_0, , , TB1_ram_block1a17_clock_enable_0);
TB1_ram_block1a17_PORT_A_write_enable = UB1L3;
TB1_ram_block1a17_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a17_PORT_A_write_enable, TB1_ram_block1a17_clock_0, , , TB1_ram_block1a17_clock_enable_0);
TB1_ram_block1a17_PORT_A_byte_mask = T1L52;
TB1_ram_block1a17_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a17_PORT_A_byte_mask, TB1_ram_block1a17_clock_0, , , TB1_ram_block1a17_clock_enable_0);
TB1_ram_block1a17_clock_0 = CLOCK_50;
TB1_ram_block1a17_clock_enable_0 = !T1L38;
TB1_ram_block1a17_PORT_A_data_out = MEMORY(TB1_ram_block1a17_PORT_A_data_in_reg, , TB1_ram_block1a17_PORT_A_address_reg, TB1_ram_block1a17_PORT_B_address_reg, TB1_ram_block1a17_PORT_A_write_enable_reg, , TB1_ram_block1a17_PORT_A_byte_mask_reg, , TB1_ram_block1a17_clock_0, , TB1_ram_block1a17_clock_enable_0, , , );
TB1_ram_block1a17 = TB1_ram_block1a17_PORT_A_data_out[0];


--TB1_ram_block1a1 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a1
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a1_PORT_A_data_in = J1L28;
TB1_ram_block1a1_PORT_A_data_in_reg = DFFE(TB1_ram_block1a1_PORT_A_data_in, TB1_ram_block1a1_clock_0, , , TB1_ram_block1a1_clock_enable_0);
TB1_ram_block1a1_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a1_PORT_A_address_reg = DFFE(TB1_ram_block1a1_PORT_A_address, TB1_ram_block1a1_clock_0, , , TB1_ram_block1a1_clock_enable_0);
TB1_ram_block1a1_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a1_PORT_B_address_reg = DFFE(TB1_ram_block1a1_PORT_B_address, TB1_ram_block1a1_clock_0, , , TB1_ram_block1a1_clock_enable_0);
TB1_ram_block1a1_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a1_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a1_PORT_A_write_enable, TB1_ram_block1a1_clock_0, , , TB1_ram_block1a1_clock_enable_0);
TB1_ram_block1a1_PORT_A_byte_mask = T1L52;
TB1_ram_block1a1_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a1_PORT_A_byte_mask, TB1_ram_block1a1_clock_0, , , TB1_ram_block1a1_clock_enable_0);
TB1_ram_block1a1_clock_0 = CLOCK_50;
TB1_ram_block1a1_clock_enable_0 = T1L38;
TB1_ram_block1a1_PORT_A_data_out = MEMORY(TB1_ram_block1a1_PORT_A_data_in_reg, , TB1_ram_block1a1_PORT_A_address_reg, TB1_ram_block1a1_PORT_B_address_reg, TB1_ram_block1a1_PORT_A_write_enable_reg, , TB1_ram_block1a1_PORT_A_byte_mask_reg, , TB1_ram_block1a1_clock_0, , TB1_ram_block1a1_clock_enable_0, , , );
TB1_ram_block1a1 = TB1_ram_block1a1_PORT_A_data_out[0];


--VB1L2 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[1]~442
VB1L2 = TB1_address_reg_a[0] & TB1_ram_block1a17 # !TB1_address_reg_a[0] & (TB1_ram_block1a1);


--K1_dbs_8_reg_segment_2[1] is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|dbs_8_reg_segment_2[1]
K1_dbs_8_reg_segment_2[1] = DFFEAS(W1_incoming_tri_state_bridge_0_data[1], CLOCK_50, E1_data_out,  , K1L5,  ,  ,  ,  );


--H1L498 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3164
H1L498 = AMPP_FUNCTION(VB1L2, K1_dbs_8_reg_segment_2[1], W1L34, T1L17);


--H1L499 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3165
H1L499 = AMPP_FUNCTION(H1L1171, H1L497, H1L498);


--H1_av_ld_byte1_data[4] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[4]
H1_av_ld_byte1_data[4] = AMPP_FUNCTION(CLOCK_50, H1L1025, H1_av_ld_byte2_data[4], E1_data_out, !H1L1103, H1L1036);


--H1_av_ld_byte1_data[3] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[3]
H1_av_ld_byte1_data[3] = AMPP_FUNCTION(CLOCK_50, H1L1022, H1_av_ld_byte2_data[3], E1_data_out, !H1L1103, H1L1036);


--H1_av_ld_byte1_data[2] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[2]
H1_av_ld_byte1_data[2] = AMPP_FUNCTION(CLOCK_50, H1L1019, H1_av_ld_byte2_data[2], E1_data_out, !H1L1103, H1L1036);


--H1_av_ld_byte1_data[1] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[1]
H1_av_ld_byte1_data[1] = AMPP_FUNCTION(CLOCK_50, H1L1016, H1_av_ld_byte2_data[1], E1_data_out, !H1L1103, H1L1036);


--H1_av_ld_byte1_data[0] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[0]
H1_av_ld_byte1_data[0] = AMPP_FUNCTION(CLOCK_50, H1L1013, H1_av_ld_byte2_data[0], E1_data_out, !H1L1103, H1L1036);


--H1_av_ld_byte0_data[7] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[7]
H1_av_ld_byte0_data[7] = AMPP_FUNCTION(CLOCK_50, H1L1010, E1_data_out, H1L965);


--H1_av_ld_byte0_data[6] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[6]
H1_av_ld_byte0_data[6] = AMPP_FUNCTION(CLOCK_50, H1L1005, E1_data_out, H1L965);


--H1_av_ld_byte0_data[5] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[5]
H1_av_ld_byte0_data[5] = AMPP_FUNCTION(CLOCK_50, H1L1000, E1_data_out, H1L965);


--H1_av_ld_byte0_data[4] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[4]
H1_av_ld_byte0_data[4] = AMPP_FUNCTION(CLOCK_50, H1L995, E1_data_out, H1L965);


--H1_av_ld_byte0_data[3] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[3]
H1_av_ld_byte0_data[3] = AMPP_FUNCTION(CLOCK_50, H1L990, E1_data_out, H1L965);


--H1_av_ld_byte0_data[2] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[2]
H1_av_ld_byte0_data[2] = AMPP_FUNCTION(CLOCK_50, H1L985, E1_data_out, H1L965);


--H1_W_control_rd_data[1] is DE2_Board:inst|cpu_0:the_cpu_0|W_control_rd_data[1]
H1_W_control_rd_data[1] = AMPP_FUNCTION(CLOCK_50, H1L144, E1_data_out);


--H1_W_alu_result[1] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[1]
H1_W_alu_result[1] = AMPP_FUNCTION(CLOCK_50, H1L672, H1_E_shift_rot_result[1], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1L776 is DE2_Board:inst|cpu_0:the_cpu_0|W_wr_data[1]~152
H1L776 = AMPP_FUNCTION(H1_W_control_rd_data[1], H1_W_alu_result[1], H1_R_ctrl_rdctl_inst, H1_R_ctrl_dst_data_sel_cmp);


--H1_av_ld_byte0_data[1] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[1]
H1_av_ld_byte0_data[1] = AMPP_FUNCTION(CLOCK_50, H1L980, E1_data_out, H1L965);


--H1_W_control_rd_data[0] is DE2_Board:inst|cpu_0:the_cpu_0|W_control_rd_data[0]
H1_W_control_rd_data[0] = AMPP_FUNCTION(CLOCK_50, H1L142, E1_data_out);


--H1_W_alu_result[0] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[0]
H1_W_alu_result[0] = AMPP_FUNCTION(CLOCK_50, H1L669, H1_E_shift_rot_result[0], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1L774 is DE2_Board:inst|cpu_0:the_cpu_0|W_wr_data[0]~153
H1L774 = AMPP_FUNCTION(H1_W_control_rd_data[0], H1_W_alu_result[0], H1_R_ctrl_rdctl_inst);


--H1L775 is DE2_Board:inst|cpu_0:the_cpu_0|W_wr_data[0]~154
H1L775 = AMPP_FUNCTION(H1_W_cmp_result, H1L774, H1_R_ctrl_dst_data_sel_cmp);


--H1_av_ld_byte0_data[0] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[0]
H1_av_ld_byte0_data[0] = AMPP_FUNCTION(CLOCK_50, H1L975, E1_data_out, H1L965);


--CB1_q_a[31] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[31]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[31] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[31], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[31] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[31]
CB1_q_b[31] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[31], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L641 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_hi[15]~882
H1L641 = AMPP_FUNCTION(H1_D_iw[21], CB1_q_b[31], H1_R_src2_use_imm, H1_R_ctrl_hi_imm);


--H1L642 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_hi[15]~883
H1L642 = AMPP_FUNCTION(H1L641, H1_R_ctrl_unsigned_lo_imm, H1_R_ctrl_force_src2_zero);


--H1L146 is DE2_Board:inst|cpu_0:the_cpu_0|E_invert_arith_src_msb~255
H1L146 = AMPP_FUNCTION(A1L66, A1L67, H1_D_iw[4], H1_D_iw[3]);


--H1L147 is DE2_Board:inst|cpu_0:the_cpu_0|E_invert_arith_src_msb~256
H1L147 = AMPP_FUNCTION(H1_R_valid, H1L146, H1L8);


--CB1_q_a[30] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[30]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[30] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[30], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[30] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[30]
CB1_q_b[30] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[30], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[6], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L404 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[30]~82
H1L404 = AMPP_FUNCTION(CB1_q_b[30], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[29] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[29]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[29] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[29], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[29] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[29]
CB1_q_b[29] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[29], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[5], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L401 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[29]~81
H1L401 = AMPP_FUNCTION(CB1_q_b[29], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[28] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[28]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[28] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[28], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[28] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[28]
CB1_q_b[28] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[28], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[4], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L398 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[28]~80
H1L398 = AMPP_FUNCTION(CB1_q_b[28], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[27] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[27]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[27] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[27], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[27] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[27]
CB1_q_b[27] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[27], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[3], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L395 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[27]~79
H1L395 = AMPP_FUNCTION(CB1_q_b[27], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[26] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[26]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[26] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[26], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[26] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[26]
CB1_q_b[26] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[26], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[2], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L392 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[26]~78
H1L392 = AMPP_FUNCTION(CB1_q_b[26], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[25] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[25]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[25] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[25], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[25] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[25]
CB1_q_b[25] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[25], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[1], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L389 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[25]~77
H1L389 = AMPP_FUNCTION(CB1_q_b[25], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[24] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[24]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[24] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[24], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[24] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[24]
CB1_q_b[24] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[24], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte3_data[0], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L386 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[24]~76
H1L386 = AMPP_FUNCTION(CB1_q_b[24], H1_D_iw[21], H1_R_src2_use_imm);


--CB1_q_a[23] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_a[23]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
CB1_q_a[23] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[23], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);

--CB1_q_b[23] is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|q_b[23]
CB1_q_b[23] = AMPP_FUNCTION(H1_W_rf_wren_a, H1L1106, CLOCK_50, CLOCK_50, H1_W_alu_result[23], H1L1107, H1L1108, H1L1109, H1L1110, H1L1111, H1_av_ld_byte2_data[7], H1_D_iw[22], H1_D_iw[23], H1_D_iw[24], H1_D_iw[25], H1_D_iw[26]);


--H1L383 is DE2_Board:inst|cpu_0:the_cpu_0|E_src2[23]~75
H1L383 = AMPP_FUNCTION(CB1_q_b[23], H1_D_iw[21], H1_R_src2_use_imm);


--H1L189 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[0]~50
H1L189 = AMPP_FUNCTION(H1_E_shift_rot_cnt[0], GND);

--H1L190 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[0]~51
H1L190 = AMPP_FUNCTION(H1_E_shift_rot_cnt[0]);


--H1L192 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[1]~52
H1L192 = AMPP_FUNCTION(H1_E_shift_rot_cnt[1], GND, H1L190);

--H1L193 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[1]~53
H1L193 = AMPP_FUNCTION(H1_E_shift_rot_cnt[1], H1L190);


--H1L195 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[2]~54
H1L195 = AMPP_FUNCTION(H1_E_shift_rot_cnt[2], GND, H1L193);

--H1L196 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[2]~55
H1L196 = AMPP_FUNCTION(H1_E_shift_rot_cnt[2], H1L193);


--H1L198 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[3]~56
H1L198 = AMPP_FUNCTION(H1_E_shift_rot_cnt[3], GND, H1L196);

--H1L199 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[3]~57
H1L199 = AMPP_FUNCTION(H1_E_shift_rot_cnt[3], H1L196);


--H1L201 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_cnt[4]~58
H1L201 = AMPP_FUNCTION(H1_E_shift_rot_cnt[4], H1L199);


--H1L955 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_align_cycle_nxt[0]~20
H1L955 = AMPP_FUNCTION(H1_av_ld_align_cycle[0], H1_d_read, J1_cpu_0_data_master_waitrequest);


--H1L956 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_align_cycle_nxt[1]~21
H1L956 = AMPP_FUNCTION(H1_av_ld_align_cycle[1], H1_av_ld_align_cycle[0], H1_d_read, J1_cpu_0_data_master_waitrequest);


--M1_registered_cpu_0_data_master_read_data_valid_data_RAM_s1 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|registered_cpu_0_data_master_read_data_valid_data_RAM_s1
M1_registered_cpu_0_data_master_read_data_valid_data_RAM_s1 = H1_d_read & M1L1 & (M1_data_RAM_s1_arb_addend[1] # !M1L6);


--M1L21 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_arb_addend[1]~99
M1L21 = M1_data_RAM_s1_arb_addend[1] & (!M1L1) # !M1_data_RAM_s1_arb_addend[1] & M1L6;


--T1L50 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter_next_value[2]~138
T1L50 = T1L49 & (T1L2 $ (T1L4 # T1L3));


--T1L47 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter_next_value[0]~139
T1L47 = T1L49 & (T1L55 & (!T1_payload_buffer_s1_arb_share_counter[0]) # !T1L55 & T1L1);


--T1L48 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_share_counter_next_value[1]~140
T1L48 = T1L49 & (T1L4 $ !T1L3);


--P1_registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1
P1_registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 = H1_d_read & P1L4 & (P1_firmware_ROM_s1_arb_addend[1] # !P1L12);


--P1L27 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_arb_addend[1]~99
P1L27 = P1_firmware_ROM_s1_arb_addend[1] & (!P1L4) # !P1_firmware_ROM_s1_arb_addend[1] & P1L12;


--H1_E_shift_rot_result[24] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[24]
H1_E_shift_rot_result[24] = AMPP_FUNCTION(CLOCK_50, H1L261, H1_E_src1[24], E1_data_out, H1_E_new_inst);


--H1L260 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[23]~465
H1L260 = AMPP_FUNCTION(H1_E_shift_rot_result[24], H1_E_shift_rot_result[22], H1_R_ctrl_shift_rot_right);


--H1L39 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_rot_right~25
H1L39 = AMPP_FUNCTION(H1_D_iw[14], H1L42, H1_D_iw[13]);


--H1_W_bstatus_reg is DE2_Board:inst|cpu_0:the_cpu_0|W_bstatus_reg
H1_W_bstatus_reg = AMPP_FUNCTION(CLOCK_50, H1L750, E1_data_out, H1_E_valid);


--H1_R_ctrl_wrctl_inst is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_wrctl_inst
H1_R_ctrl_wrctl_inst = AMPP_FUNCTION(CLOCK_50, A1L74, E1_data_out);


--H1L431 is DE2_Board:inst|cpu_0:the_cpu_0|E_wrctl_status~9
H1L431 = AMPP_FUNCTION(H1_R_ctrl_wrctl_inst, H1_D_iw[8], H1_D_iw[7]);


--H1L769 is DE2_Board:inst|cpu_0:the_cpu_0|W_status_reg_pie_inst_nxt~599
H1L769 = AMPP_FUNCTION(H1_W_status_reg_pie, H1_E_src1[0], H1L431, H1_D_iw[6]);


--H1L770 is DE2_Board:inst|cpu_0:the_cpu_0|W_status_reg_pie_inst_nxt~600
H1L770 = AMPP_FUNCTION(H1_D_iw[14], H1_W_bstatus_reg, H1L769, A1L102);


--A1L70 is rtl~50
A1L70 = H1_D_iw[11] & A1L80 & !H1_D_iw[14] & !H1_D_iw[15];


--H1_W_estatus_reg is DE2_Board:inst|cpu_0:the_cpu_0|W_estatus_reg
H1_W_estatus_reg = AMPP_FUNCTION(CLOCK_50, H1L757, E1_data_out, H1_E_valid);


--H1L771 is DE2_Board:inst|cpu_0:the_cpu_0|W_status_reg_pie_inst_nxt~601
H1L771 = AMPP_FUNCTION(H1L591, H1L770, A1L70, H1_W_estatus_reg);


--H1_W_ienable_reg[1] is DE2_Board:inst|cpu_0:the_cpu_0|W_ienable_reg[1]
H1_W_ienable_reg[1] = AMPP_FUNCTION(CLOCK_50, H1_E_src1[1], E1_data_out, H1L761);


--X1_irq_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|irq_reg
X1_irq_reg = DFFEAS(X1L133, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L765 is DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg_nxt~1
H1L765 = AMPP_FUNCTION(H1_W_ienable_reg[1], X1_irq_reg);


--H1_W_ienable_reg[0] is DE2_Board:inst|cpu_0:the_cpu_0|W_ienable_reg[0]
H1_W_ienable_reg[0] = AMPP_FUNCTION(CLOCK_50, H1_E_src1[0], E1_data_out, H1L761);


--Q1_ien_AF is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|ien_AF
Q1_ien_AF = DFFEAS(H1_d_writedata[0], CLOCK_50, E1_data_out,  , Q1L73,  ,  ,  ,  );


--Q1_fifo_AF is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|fifo_AF
Q1_fifo_AF = DFFEAS(Q1L4, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--Q1_pause_irq is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|pause_irq
Q1_pause_irq = DFFEAS(Q1L76, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L189 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[8]~67
J1L189 = Q1_ien_AF & (Q1_fifo_AF # Q1_pause_irq);


--Q1_fifo_AE is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|fifo_AE
Q1_fifo_AE = DFFEAS(Q1L7, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--Q1_ien_AE is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|ien_AE
Q1_ien_AE = DFFEAS(H1_d_writedata[1], CLOCK_50, E1_data_out,  , Q1L73,  ,  ,  ,  );


--H1L766 is DE2_Board:inst|cpu_0:the_cpu_0|W_ipending_reg_nxt~35
H1L766 = AMPP_FUNCTION(H1_W_ienable_reg[0], J1L189, Q1_fifo_AE, Q1_ien_AE);


--L1L1 is DE2_Board:inst|data_RAM:the_data_RAM|wren~4
L1L1 = AB1_d_write & M1L1 & (M1_data_RAM_s1_arb_addend[1] # !M1L6);


--M1L26 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_grant_vector[1]~70
M1L26 = M1L1 & (M1_data_RAM_s1_arb_addend[1] # !M1L6);


--M1L11 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[0]~80
M1L11 = M1L26 & H1_W_alu_result[2] # !M1L26 & (H1_F_pc[0]);


--M1L12 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[1]~81
M1L12 = M1L26 & H1_W_alu_result[3] # !M1L26 & (H1_F_pc[1]);


--M1L13 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[2]~82
M1L13 = M1L26 & H1_W_alu_result[4] # !M1L26 & (H1_F_pc[2]);


--M1L14 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[3]~83
M1L14 = M1L26 & H1_W_alu_result[5] # !M1L26 & (H1_F_pc[3]);


--M1L15 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[4]~84
M1L15 = M1L26 & H1_W_alu_result[6] # !M1L26 & (H1_F_pc[4]);


--M1L16 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[5]~85
M1L16 = M1L26 & H1_W_alu_result[7] # !M1L26 & (H1_F_pc[5]);


--M1L17 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[6]~86
M1L17 = M1L26 & H1_W_alu_result[8] # !M1L26 & (H1_F_pc[6]);


--M1L18 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_address[7]~87
M1L18 = M1L26 & H1_W_alu_result[9] # !M1L26 & (H1_F_pc[7]);


--M1L22 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_byteenable[0]~16
M1L22 = H1_d_byteenable[0] # M1L6 & !M1_data_RAM_s1_arb_addend[1] # !M1L1;


--P1L32 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_grant_vector[1]~63
P1L32 = P1L4 & (P1_firmware_ROM_s1_arb_addend[1] # !P1L12);


--P1L15 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[0]~100
P1L15 = P1L32 & H1_W_alu_result[2] # !P1L32 & (H1_F_pc[0]);


--P1L16 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[1]~101
P1L16 = P1L32 & H1_W_alu_result[3] # !P1L32 & (H1_F_pc[1]);


--P1L17 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[2]~102
P1L17 = P1L32 & H1_W_alu_result[4] # !P1L32 & (H1_F_pc[2]);


--P1L18 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[3]~103
P1L18 = P1L32 & H1_W_alu_result[5] # !P1L32 & (H1_F_pc[3]);


--P1L19 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[4]~104
P1L19 = P1L32 & H1_W_alu_result[6] # !P1L32 & (H1_F_pc[4]);


--P1L20 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[5]~105
P1L20 = P1L32 & H1_W_alu_result[7] # !P1L32 & (H1_F_pc[5]);


--P1L21 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[6]~106
P1L21 = P1L32 & H1_W_alu_result[8] # !P1L32 & (H1_F_pc[6]);


--P1L22 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[7]~107
P1L22 = P1L32 & H1_W_alu_result[9] # !P1L32 & (H1_F_pc[7]);


--P1L23 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[8]~108
P1L23 = P1L32 & H1_W_alu_result[10] # !P1L32 & (H1_F_pc[8]);


--P1L24 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_address[9]~109
P1L24 = P1L32 & H1_W_alu_result[11] # !P1L32 & (H1_F_pc[9]);


--P1L28 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_byteenable[0]~16
P1L28 = H1_d_byteenable[0] # P1L12 & !P1_firmware_ROM_s1_arb_addend[1] # !P1L4;


--K1L2 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always0~23
K1L2 = !K1_cpu_0_instruction_master_dbs_address[1] & (W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register);


--W1_incoming_tri_state_bridge_0_data[4] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[4]
W1_incoming_tri_state_bridge_0_data[4] = DFFEAS(A1L51, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--K1L3 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always2~0
K1L3 = !K1_cpu_0_instruction_master_dbs_address[1] & !K1_cpu_0_instruction_master_dbs_address[0] & (W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register);


--W1_incoming_tri_state_bridge_0_data[3] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[3]
W1_incoming_tri_state_bridge_0_data[3] = DFFEAS(A1L52, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_E_shift_rot_result[0] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[0]
H1_E_shift_rot_result[0] = AMPP_FUNCTION(CLOCK_50, H1L237, H1_E_src1[0], E1_data_out, H1_E_new_inst);


--H1L238 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[1]~466
H1L238 = AMPP_FUNCTION(H1_E_shift_rot_result[2], H1_E_shift_rot_result[0], H1_R_ctrl_shift_rot_right);


--D1L21 is sld_hub:sld_hub_inst|IRSR_D[1]~274
D1L21 = AMPP_FUNCTION(DC1_state[4], ZB3_Q[2]);


--ZB3L6 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]~69
ZB3L6 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, DC1_state[4], DC1_state[3], D1L15);


--ZB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0]
ZB5_Q[0] = AMPP_FUNCTION(A1L5, ZB5L3, D1_CLRN_SIGNAL);


--ZB4L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]~181
ZB4L3 = AMPP_FUNCTION(ZB5_Q[0], ZB3_Q[0], ZB2_Q[0]);


--EC1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[2]
EC1_dffe1a[2] = AMPP_FUNCTION(A1L5, EC1_w_anode28w[3], D1_CLRN_SIGNAL, D1L6);


--D1L17 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~77
D1L17 = AMPP_FUNCTION(ZB7_Q[0], EC1_dffe1a[2], ZB6_Q[0], ZB2_Q[0]);


--D1L18 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~78
D1L18 = AMPP_FUNCTION(D1_OK_TO_UPDATE_IR_Q, DC1_state[5]);


--ZB4L4 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]~182
ZB4L4 = AMPP_FUNCTION(ZB4L3, ZB4_Q[0], D1L17, D1L18);


--D1L23 is sld_hub:sld_hub_inst|IRSR_D[3]~275
D1L23 = AMPP_FUNCTION(DC1_state[4], ZB3_Q[4]);


--EC1_w_anode38w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode38w[3]
EC1_w_anode38w[3] = AMPP_FUNCTION(ZB3_Q[1], ZB3_Q[2], D1L28, ZB3_Q[3]);


--DC1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
DC1_state[1] = AMPP_FUNCTION(A1L5, DC1L18, A1L7);


--ZB1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]
ZB1_Q[0] = AMPP_FUNCTION(A1L5, ZB1L3, D1_jtag_debug_mode_usr1);


--D1L4 is sld_hub:sld_hub_inst|CLRN_SIGNAL~0
D1L4 = AMPP_FUNCTION(DC1_state[1], ZB1_Q[0]);


--D1L32 is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q~56
D1L32 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, D1_OK_TO_UPDATE_IR_Q, DC1_state[4], DC1_state[8]);


--FB1L56 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state~194
FB1L56 = AMPP_FUNCTION(DC1_state[3], ZB4_Q[0], FB1_state);


--FB1L57 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state~195
FB1L57 = AMPP_FUNCTION(FB1L1, D1L8, FB1_state, FB1L56);


--FB1_count[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[0]
FB1_count[0] = AMPP_FUNCTION(A1L5, FB1L15, D1_CLRN_SIGNAL, FB1L44);


--FB1L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~214
FB1L14 = AMPP_FUNCTION(DC1_state[4], FB1_count[0]);


--FB1L89 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid~130
FB1L89 = AMPP_FUNCTION(DC1_state[4], FB1_state, FB1L1, ZB4_Q[0]);


--FB1L90 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid~131
FB1L90 = AMPP_FUNCTION(FB1_td_shift[0], FB1_user_saw_rvalid, FB1_count[0], FB1L89);


--FB1_td_shift[10] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10]
FB1_td_shift[10] = AMPP_FUNCTION(A1L5, D1L8, D1_CLRN_SIGNAL, FB1L44);


--FB1_rdata[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[7]
FB1_rdata[7] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[7], E1_data_out, FB1L28);


--FB1L76 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1390
FB1L76 = AMPP_FUNCTION(FB1_td_shift[10], FB1_rdata[7], FB1_count[9]);


--MB2_b_full is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full
MB2_b_full = DFFEAS(MB2L7, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--FB1L70 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5]~1391
FB1L70 = AMPP_FUNCTION(DC1_state[4], ZB4_Q[0], FB1L46);


--FB1_td_shift[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[2]
FB1_td_shift[2] = AMPP_FUNCTION(A1L5, FB1L78, D1_CLRN_SIGNAL, FB1L44);


--FB1_write_stalled is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled
FB1_write_stalled = AMPP_FUNCTION(A1L5, FB1L103, D1_CLRN_SIGNAL, FB1L93);


--FB1L77 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1392
FB1L77 = AMPP_FUNCTION(FB1L70, FB1_td_shift[2], FB1_write_stalled, FB1_count[9]);


--FB1_rvalid0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid0
FB1_rvalid0 = AMPP_FUNCTION(CLOCK_50, FB1L54, E1_data_out);


--FB1_count[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[8]
FB1_count[8] = AMPP_FUNCTION(A1L5, FB1L16, D1_CLRN_SIGNAL, FB1L44);


--FB1L51 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rtl~660
FB1L51 = AMPP_FUNCTION(DC1_state[4], FB1_count[8], FB1L45, ZB4_Q[0]);


--D1L29 is sld_hub:sld_hub_inst|jtag_debug_mode~171
D1L29 = AMPP_FUNCTION(DC1_state[12], A1L7, DC1_state[2]);


--DC1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]
DC1_state[15] = AMPP_FUNCTION(A1L5, DC1L29, !A1L7);


--D1L30 is sld_hub:sld_hub_inst|jtag_debug_mode~172
D1L30 = AMPP_FUNCTION(D1L28, D1_jtag_debug_mode, D1L29, DC1_state[15]);


--EC1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[1]
EC1_dffe1a[1] = AMPP_FUNCTION(A1L5, EC1_w_anode18w[3], D1_CLRN_SIGNAL, D1L6);


--D1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28
D1L1 = AMPP_FUNCTION(DC1_state[8], D1_OK_TO_UPDATE_IR_Q, EC1_dffe1a[2], EC1_dffe1a[1]);


--ZB2L3 is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~71
ZB2L3 = AMPP_FUNCTION(EC1_dffe1a[1], ZB2_Q[0], ZB7_Q[0], D1L1);


--AC1_WORD_SR[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2]
AC1_WORD_SR[2] = AMPP_FUNCTION(A1L5, AC1L32, AC1L24);


--AC1_word_counter[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]
AC1_word_counter[1] = AMPP_FUNCTION(A1L5, AC1L9, AC1L6, AC1L7);


--AC1_word_counter[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]
AC1_word_counter[2] = AMPP_FUNCTION(A1L5, AC1L12, AC1L6, AC1L7);


--AC1L27 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~752
AC1L27 = AMPP_FUNCTION(AC1_word_counter[1], AC1_word_counter[2]);


--AC1L28 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~753
AC1L28 = AMPP_FUNCTION(AC1_WORD_SR[2], AC1L27, DC1_state[4], AC1_clear_signal);


--A1L63 is rtl~12
A1L63 = A1L100 & A1L101 & !CC1_dffs[1] & !CC1_dffs[0];


--D1L22 is sld_hub:sld_hub_inst|IRSR_D[2]~276
D1L22 = AMPP_FUNCTION(DC1_state[4], ZB3_Q[3]);


--DC1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11]
DC1_state[11] = AMPP_FUNCTION(A1L5, DC1L26, A1L7);


--DC1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]
DC1_state[9] = AMPP_FUNCTION(A1L5, D1L33);


--DC1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2]
DC1_tms_cnt[2] = AMPP_FUNCTION(A1L5, DC1L40, !A1L7);


--DC1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]
DC1_tms_cnt[0] = AMPP_FUNCTION(A1L5, DC1L38);


--DC1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1]
DC1_tms_cnt[1] = AMPP_FUNCTION(A1L5, DC1L39, !A1L7);


--DC1L30 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~431
DC1L30 = AMPP_FUNCTION(DC1_tms_cnt[2], DC1_tms_cnt[0], DC1_tms_cnt[1]);


--DC1L31 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~432
DC1L31 = AMPP_FUNCTION(A1L7, DC1_state[9], DC1L30, DC1_state[0]);


--DC1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]
DC1_state[10] = AMPP_FUNCTION(A1L5, DC1L25);


--DC1L32 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~433
DC1L32 = AMPP_FUNCTION(A1L7, DC1_state[11], DC1_state[10]);


--DC1L33 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~434
DC1L33 = AMPP_FUNCTION(A1L7, DC1_state[8], DC1_state[1], DC1_state[15]);


--DC1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6]
DC1_state[6] = AMPP_FUNCTION(A1L5, DC1L22, A1L7);


--DC1L23 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~17
DC1L23 = AMPP_FUNCTION(A1L7, DC1_state[6]);


--DC1L21 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~14
DC1L21 = AMPP_FUNCTION(A1L7, DC1_state[3], DC1_state[4]);


--H1L414 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[15]~800
H1L414 = AMPP_FUNCTION(CB1_q_b[15], CB1_q_b[7], H1_D_iw[4], H1_D_iw[3]);


--H1L422 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[23]~801
H1L422 = AMPP_FUNCTION(CB1_q_b[23], CB1_q_b[7], H1_D_iw[4]);


--H1L1167 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[31]~68
H1L1167 = AMPP_FUNCTION(CB1_q_b[7], CB1_q_b[15], H1_D_iw[3]);


--H1L413 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[14]~802
H1L413 = AMPP_FUNCTION(CB1_q_b[14], CB1_q_b[6], H1_D_iw[4], H1_D_iw[3]);


--H1L421 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[22]~803
H1L421 = AMPP_FUNCTION(CB1_q_b[22], CB1_q_b[6], H1_D_iw[4]);


--H1L1164 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[30]~69
H1L1164 = AMPP_FUNCTION(CB1_q_b[6], CB1_q_b[14], H1_D_iw[3]);


--H1L412 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[13]~804
H1L412 = AMPP_FUNCTION(CB1_q_b[13], CB1_q_b[5], H1_D_iw[4], H1_D_iw[3]);


--H1L420 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[21]~805
H1L420 = AMPP_FUNCTION(CB1_q_b[21], CB1_q_b[5], H1_D_iw[4]);


--H1L1161 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[29]~70
H1L1161 = AMPP_FUNCTION(CB1_q_b[5], CB1_q_b[13], H1_D_iw[3]);


--H1L411 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[12]~806
H1L411 = AMPP_FUNCTION(CB1_q_b[12], CB1_q_b[4], H1_D_iw[4], H1_D_iw[3]);


--H1L419 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[20]~807
H1L419 = AMPP_FUNCTION(CB1_q_b[20], CB1_q_b[4], H1_D_iw[4]);


--H1L1158 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[28]~71
H1L1158 = AMPP_FUNCTION(CB1_q_b[4], CB1_q_b[12], H1_D_iw[3]);


--H1L410 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[11]~808
H1L410 = AMPP_FUNCTION(CB1_q_b[11], CB1_q_b[3], H1_D_iw[4], H1_D_iw[3]);


--H1L418 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[19]~809
H1L418 = AMPP_FUNCTION(CB1_q_b[19], CB1_q_b[3], H1_D_iw[4]);


--H1L1155 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[27]~72
H1L1155 = AMPP_FUNCTION(CB1_q_b[3], CB1_q_b[11], H1_D_iw[3]);


--H1L409 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[10]~810
H1L409 = AMPP_FUNCTION(CB1_q_b[10], CB1_q_b[2], H1_D_iw[4], H1_D_iw[3]);


--H1L417 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[18]~811
H1L417 = AMPP_FUNCTION(CB1_q_b[18], CB1_q_b[2], H1_D_iw[4]);


--H1L1152 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[26]~73
H1L1152 = AMPP_FUNCTION(CB1_q_b[2], CB1_q_b[10], H1_D_iw[3]);


--H1L408 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[9]~812
H1L408 = AMPP_FUNCTION(CB1_q_b[9], CB1_q_b[1], H1_D_iw[4], H1_D_iw[3]);


--H1L416 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[17]~813
H1L416 = AMPP_FUNCTION(CB1_q_b[17], CB1_q_b[1], H1_D_iw[4]);


--H1L1149 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[25]~74
H1L1149 = AMPP_FUNCTION(CB1_q_b[1], CB1_q_b[9], H1_D_iw[3]);


--H1L407 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[8]~814
H1L407 = AMPP_FUNCTION(CB1_q_b[8], CB1_q_b[0], H1_D_iw[4], H1_D_iw[3]);


--H1L415 is DE2_Board:inst|cpu_0:the_cpu_0|E_st_data[16]~815
H1L415 = AMPP_FUNCTION(CB1_q_b[16], CB1_q_b[0], H1_D_iw[4]);


--H1L1146 is DE2_Board:inst|cpu_0:the_cpu_0|d_writedata[24]~75
H1L1146 = AMPP_FUNCTION(CB1_q_b[0], CB1_q_b[8], H1_D_iw[3]);


--W1_incoming_tri_state_bridge_0_data[5] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[5]
W1_incoming_tri_state_bridge_0_data[5] = DFFEAS(A1L50, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--M1L23 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_byteenable[1]~17
M1L23 = H1_d_byteenable[1] # M1L6 & !M1_data_RAM_s1_arb_addend[1] # !M1L1;


--P1L29 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_byteenable[1]~17
P1L29 = H1_d_byteenable[1] # P1L12 & !P1_firmware_ROM_s1_arb_addend[1] # !P1L4;


--K1L4 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always3~0
K1L4 = K1_cpu_0_instruction_master_dbs_address[0] & !K1_cpu_0_instruction_master_dbs_address[1] & (W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register);


--TB1_ram_block1a28 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a28
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a28_PORT_A_data_in = J1L39;
TB1_ram_block1a28_PORT_A_data_in_reg = DFFE(TB1_ram_block1a28_PORT_A_data_in, TB1_ram_block1a28_clock_0, , , TB1_ram_block1a28_clock_enable_0);
TB1_ram_block1a28_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a28_PORT_A_address_reg = DFFE(TB1_ram_block1a28_PORT_A_address, TB1_ram_block1a28_clock_0, , , TB1_ram_block1a28_clock_enable_0);
TB1_ram_block1a28_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a28_PORT_B_address_reg = DFFE(TB1_ram_block1a28_PORT_B_address, TB1_ram_block1a28_clock_0, , , TB1_ram_block1a28_clock_enable_0);
TB1_ram_block1a28_PORT_A_write_enable = UB1L3;
TB1_ram_block1a28_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a28_PORT_A_write_enable, TB1_ram_block1a28_clock_0, , , TB1_ram_block1a28_clock_enable_0);
TB1_ram_block1a28_PORT_A_byte_mask = T1L53;
TB1_ram_block1a28_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a28_PORT_A_byte_mask, TB1_ram_block1a28_clock_0, , , TB1_ram_block1a28_clock_enable_0);
TB1_ram_block1a28_clock_0 = CLOCK_50;
TB1_ram_block1a28_clock_enable_0 = !T1L38;
TB1_ram_block1a28_PORT_A_data_out = MEMORY(TB1_ram_block1a28_PORT_A_data_in_reg, , TB1_ram_block1a28_PORT_A_address_reg, TB1_ram_block1a28_PORT_B_address_reg, TB1_ram_block1a28_PORT_A_write_enable_reg, , TB1_ram_block1a28_PORT_A_byte_mask_reg, , TB1_ram_block1a28_clock_0, , TB1_ram_block1a28_clock_enable_0, , , );
TB1_ram_block1a28 = TB1_ram_block1a28_PORT_A_data_out[0];


--TB1_ram_block1a12 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a12
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a12_PORT_A_data_in = J1L39;
TB1_ram_block1a12_PORT_A_data_in_reg = DFFE(TB1_ram_block1a12_PORT_A_data_in, TB1_ram_block1a12_clock_0, , , TB1_ram_block1a12_clock_enable_0);
TB1_ram_block1a12_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a12_PORT_A_address_reg = DFFE(TB1_ram_block1a12_PORT_A_address, TB1_ram_block1a12_clock_0, , , TB1_ram_block1a12_clock_enable_0);
TB1_ram_block1a12_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a12_PORT_B_address_reg = DFFE(TB1_ram_block1a12_PORT_B_address, TB1_ram_block1a12_clock_0, , , TB1_ram_block1a12_clock_enable_0);
TB1_ram_block1a12_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a12_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a12_PORT_A_write_enable, TB1_ram_block1a12_clock_0, , , TB1_ram_block1a12_clock_enable_0);
TB1_ram_block1a12_PORT_A_byte_mask = T1L53;
TB1_ram_block1a12_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a12_PORT_A_byte_mask, TB1_ram_block1a12_clock_0, , , TB1_ram_block1a12_clock_enable_0);
TB1_ram_block1a12_clock_0 = CLOCK_50;
TB1_ram_block1a12_clock_enable_0 = T1L38;
TB1_ram_block1a12_PORT_A_data_out = MEMORY(TB1_ram_block1a12_PORT_A_data_in_reg, , TB1_ram_block1a12_PORT_A_address_reg, TB1_ram_block1a12_PORT_B_address_reg, TB1_ram_block1a12_PORT_A_write_enable_reg, , TB1_ram_block1a12_PORT_A_byte_mask_reg, , TB1_ram_block1a12_clock_0, , TB1_ram_block1a12_clock_enable_0, , , );
TB1_ram_block1a12 = TB1_ram_block1a12_PORT_A_data_out[0];


--VB1L13 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[12]~443
VB1L13 = TB1_address_reg_a[0] & TB1_ram_block1a28 # !TB1_address_reg_a[0] & (TB1_ram_block1a12);


--M1L24 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_byteenable[2]~18
M1L24 = H1_d_byteenable[2] # M1L6 & !M1_data_RAM_s1_arb_addend[1] # !M1L1;


--P1L30 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_byteenable[2]~18
P1L30 = H1_d_byteenable[2] # P1L12 & !P1_firmware_ROM_s1_arb_addend[1] # !P1L4;


--UB1L3 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|decode_1oa:decode3|eq_node[1]~16
UB1L3 = AB1_d_write & H1_W_alu_result[13] & T1L56;


--T1L38 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[12]~137
T1L38 = T1L56 & !H1_W_alu_result[13] # !T1L56 & (!H1_F_pc[11]);


--J1L27 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[0]~160
J1L27 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[16] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[0]);


--T1L26 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[0]~138
T1L26 = T1L56 & J1_cpu_0_data_master_dbs_address[1] # !T1L56 & (K1_cpu_0_instruction_master_dbs_address[1]);


--T1L27 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[1]~139
T1L27 = T1L56 & H1_W_alu_result[2] # !T1L56 & (H1_F_pc[0]);


--T1L28 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[2]~140
T1L28 = T1L56 & H1_W_alu_result[3] # !T1L56 & (H1_F_pc[1]);


--T1L29 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[3]~141
T1L29 = T1L56 & H1_W_alu_result[4] # !T1L56 & (H1_F_pc[2]);


--T1L30 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[4]~142
T1L30 = T1L56 & H1_W_alu_result[5] # !T1L56 & (H1_F_pc[3]);


--T1L31 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[5]~143
T1L31 = T1L56 & H1_W_alu_result[6] # !T1L56 & (H1_F_pc[4]);


--T1L32 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[6]~144
T1L32 = T1L56 & H1_W_alu_result[7] # !T1L56 & (H1_F_pc[5]);


--T1L33 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[7]~145
T1L33 = T1L56 & H1_W_alu_result[8] # !T1L56 & (H1_F_pc[6]);


--T1L34 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[8]~146
T1L34 = T1L56 & H1_W_alu_result[9] # !T1L56 & (H1_F_pc[7]);


--T1L35 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[9]~147
T1L35 = T1L56 & H1_W_alu_result[10] # !T1L56 & (H1_F_pc[8]);


--T1L36 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[10]~148
T1L36 = T1L56 & H1_W_alu_result[11] # !T1L56 & (H1_F_pc[9]);


--T1L37 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[11]~149
T1L37 = T1L56 & H1_W_alu_result[12] # !T1L56 & (H1_F_pc[10]);


--T1L52 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_byteenable[0]~8
T1L52 = T1L5 # T1L13 & !T1_payload_buffer_s1_arb_addend[1] # !T1L8;


--UB1_eq_node[0] is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|decode_1oa:decode3|eq_node[0]
UB1_eq_node[0] = !H1_W_alu_result[13] & AB1_d_write & T1L56;


--K1L5 is DE2_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|always4~33
K1L5 = K1_cpu_0_instruction_master_dbs_address[1] & !K1_cpu_0_instruction_master_dbs_address[0] & (W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # T1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register);


--TB1_ram_block1a31 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a31
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a31_PORT_A_data_in = J1L42;
TB1_ram_block1a31_PORT_A_data_in_reg = DFFE(TB1_ram_block1a31_PORT_A_data_in, TB1_ram_block1a31_clock_0, , , TB1_ram_block1a31_clock_enable_0);
TB1_ram_block1a31_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a31_PORT_A_address_reg = DFFE(TB1_ram_block1a31_PORT_A_address, TB1_ram_block1a31_clock_0, , , TB1_ram_block1a31_clock_enable_0);
TB1_ram_block1a31_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a31_PORT_B_address_reg = DFFE(TB1_ram_block1a31_PORT_B_address, TB1_ram_block1a31_clock_0, , , TB1_ram_block1a31_clock_enable_0);
TB1_ram_block1a31_PORT_A_write_enable = UB1L3;
TB1_ram_block1a31_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a31_PORT_A_write_enable, TB1_ram_block1a31_clock_0, , , TB1_ram_block1a31_clock_enable_0);
TB1_ram_block1a31_PORT_A_byte_mask = T1L53;
TB1_ram_block1a31_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a31_PORT_A_byte_mask, TB1_ram_block1a31_clock_0, , , TB1_ram_block1a31_clock_enable_0);
TB1_ram_block1a31_clock_0 = CLOCK_50;
TB1_ram_block1a31_clock_enable_0 = !T1L38;
TB1_ram_block1a31_PORT_A_data_out = MEMORY(TB1_ram_block1a31_PORT_A_data_in_reg, , TB1_ram_block1a31_PORT_A_address_reg, TB1_ram_block1a31_PORT_B_address_reg, TB1_ram_block1a31_PORT_A_write_enable_reg, , TB1_ram_block1a31_PORT_A_byte_mask_reg, , TB1_ram_block1a31_clock_0, , TB1_ram_block1a31_clock_enable_0, , , );
TB1_ram_block1a31 = TB1_ram_block1a31_PORT_A_data_out[0];


--TB1_ram_block1a15 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a15
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a15_PORT_A_data_in = J1L42;
TB1_ram_block1a15_PORT_A_data_in_reg = DFFE(TB1_ram_block1a15_PORT_A_data_in, TB1_ram_block1a15_clock_0, , , TB1_ram_block1a15_clock_enable_0);
TB1_ram_block1a15_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a15_PORT_A_address_reg = DFFE(TB1_ram_block1a15_PORT_A_address, TB1_ram_block1a15_clock_0, , , TB1_ram_block1a15_clock_enable_0);
TB1_ram_block1a15_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a15_PORT_B_address_reg = DFFE(TB1_ram_block1a15_PORT_B_address, TB1_ram_block1a15_clock_0, , , TB1_ram_block1a15_clock_enable_0);
TB1_ram_block1a15_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a15_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a15_PORT_A_write_enable, TB1_ram_block1a15_clock_0, , , TB1_ram_block1a15_clock_enable_0);
TB1_ram_block1a15_PORT_A_byte_mask = T1L53;
TB1_ram_block1a15_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a15_PORT_A_byte_mask, TB1_ram_block1a15_clock_0, , , TB1_ram_block1a15_clock_enable_0);
TB1_ram_block1a15_clock_0 = CLOCK_50;
TB1_ram_block1a15_clock_enable_0 = T1L38;
TB1_ram_block1a15_PORT_A_data_out = MEMORY(TB1_ram_block1a15_PORT_A_data_in_reg, , TB1_ram_block1a15_PORT_A_address_reg, TB1_ram_block1a15_PORT_B_address_reg, TB1_ram_block1a15_PORT_A_write_enable_reg, , TB1_ram_block1a15_PORT_A_byte_mask_reg, , TB1_ram_block1a15_clock_0, , TB1_ram_block1a15_clock_enable_0, , , );
TB1_ram_block1a15 = TB1_ram_block1a15_PORT_A_data_out[0];


--VB1L16 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[15]~444
VB1L16 = TB1_address_reg_a[0] & TB1_ram_block1a31 # !TB1_address_reg_a[0] & (TB1_ram_block1a15);


--W1_incoming_tri_state_bridge_0_data[7] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[7]
W1_incoming_tri_state_bridge_0_data[7] = DFFEAS(A1L48, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--TB1_ram_block1a30 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a30
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a30_PORT_A_data_in = J1L41;
TB1_ram_block1a30_PORT_A_data_in_reg = DFFE(TB1_ram_block1a30_PORT_A_data_in, TB1_ram_block1a30_clock_0, , , TB1_ram_block1a30_clock_enable_0);
TB1_ram_block1a30_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a30_PORT_A_address_reg = DFFE(TB1_ram_block1a30_PORT_A_address, TB1_ram_block1a30_clock_0, , , TB1_ram_block1a30_clock_enable_0);
TB1_ram_block1a30_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a30_PORT_B_address_reg = DFFE(TB1_ram_block1a30_PORT_B_address, TB1_ram_block1a30_clock_0, , , TB1_ram_block1a30_clock_enable_0);
TB1_ram_block1a30_PORT_A_write_enable = UB1L3;
TB1_ram_block1a30_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a30_PORT_A_write_enable, TB1_ram_block1a30_clock_0, , , TB1_ram_block1a30_clock_enable_0);
TB1_ram_block1a30_PORT_A_byte_mask = T1L53;
TB1_ram_block1a30_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a30_PORT_A_byte_mask, TB1_ram_block1a30_clock_0, , , TB1_ram_block1a30_clock_enable_0);
TB1_ram_block1a30_clock_0 = CLOCK_50;
TB1_ram_block1a30_clock_enable_0 = !T1L38;
TB1_ram_block1a30_PORT_A_data_out = MEMORY(TB1_ram_block1a30_PORT_A_data_in_reg, , TB1_ram_block1a30_PORT_A_address_reg, TB1_ram_block1a30_PORT_B_address_reg, TB1_ram_block1a30_PORT_A_write_enable_reg, , TB1_ram_block1a30_PORT_A_byte_mask_reg, , TB1_ram_block1a30_clock_0, , TB1_ram_block1a30_clock_enable_0, , , );
TB1_ram_block1a30 = TB1_ram_block1a30_PORT_A_data_out[0];


--TB1_ram_block1a14 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a14
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a14_PORT_A_data_in = J1L41;
TB1_ram_block1a14_PORT_A_data_in_reg = DFFE(TB1_ram_block1a14_PORT_A_data_in, TB1_ram_block1a14_clock_0, , , TB1_ram_block1a14_clock_enable_0);
TB1_ram_block1a14_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a14_PORT_A_address_reg = DFFE(TB1_ram_block1a14_PORT_A_address, TB1_ram_block1a14_clock_0, , , TB1_ram_block1a14_clock_enable_0);
TB1_ram_block1a14_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a14_PORT_B_address_reg = DFFE(TB1_ram_block1a14_PORT_B_address, TB1_ram_block1a14_clock_0, , , TB1_ram_block1a14_clock_enable_0);
TB1_ram_block1a14_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a14_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a14_PORT_A_write_enable, TB1_ram_block1a14_clock_0, , , TB1_ram_block1a14_clock_enable_0);
TB1_ram_block1a14_PORT_A_byte_mask = T1L53;
TB1_ram_block1a14_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a14_PORT_A_byte_mask, TB1_ram_block1a14_clock_0, , , TB1_ram_block1a14_clock_enable_0);
TB1_ram_block1a14_clock_0 = CLOCK_50;
TB1_ram_block1a14_clock_enable_0 = T1L38;
TB1_ram_block1a14_PORT_A_data_out = MEMORY(TB1_ram_block1a14_PORT_A_data_in_reg, , TB1_ram_block1a14_PORT_A_address_reg, TB1_ram_block1a14_PORT_B_address_reg, TB1_ram_block1a14_PORT_A_write_enable_reg, , TB1_ram_block1a14_PORT_A_byte_mask_reg, , TB1_ram_block1a14_clock_0, , TB1_ram_block1a14_clock_enable_0, , , );
TB1_ram_block1a14 = TB1_ram_block1a14_PORT_A_data_out[0];


--VB1L15 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[14]~445
VB1L15 = TB1_address_reg_a[0] & TB1_ram_block1a30 # !TB1_address_reg_a[0] & (TB1_ram_block1a14);


--W1_incoming_tri_state_bridge_0_data[6] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6]
W1_incoming_tri_state_bridge_0_data[6] = DFFEAS(A1L49, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--TB1_ram_block1a29 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a29
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a29_PORT_A_data_in = J1L40;
TB1_ram_block1a29_PORT_A_data_in_reg = DFFE(TB1_ram_block1a29_PORT_A_data_in, TB1_ram_block1a29_clock_0, , , TB1_ram_block1a29_clock_enable_0);
TB1_ram_block1a29_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a29_PORT_A_address_reg = DFFE(TB1_ram_block1a29_PORT_A_address, TB1_ram_block1a29_clock_0, , , TB1_ram_block1a29_clock_enable_0);
TB1_ram_block1a29_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a29_PORT_B_address_reg = DFFE(TB1_ram_block1a29_PORT_B_address, TB1_ram_block1a29_clock_0, , , TB1_ram_block1a29_clock_enable_0);
TB1_ram_block1a29_PORT_A_write_enable = UB1L3;
TB1_ram_block1a29_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a29_PORT_A_write_enable, TB1_ram_block1a29_clock_0, , , TB1_ram_block1a29_clock_enable_0);
TB1_ram_block1a29_PORT_A_byte_mask = T1L53;
TB1_ram_block1a29_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a29_PORT_A_byte_mask, TB1_ram_block1a29_clock_0, , , TB1_ram_block1a29_clock_enable_0);
TB1_ram_block1a29_clock_0 = CLOCK_50;
TB1_ram_block1a29_clock_enable_0 = !T1L38;
TB1_ram_block1a29_PORT_A_data_out = MEMORY(TB1_ram_block1a29_PORT_A_data_in_reg, , TB1_ram_block1a29_PORT_A_address_reg, TB1_ram_block1a29_PORT_B_address_reg, TB1_ram_block1a29_PORT_A_write_enable_reg, , TB1_ram_block1a29_PORT_A_byte_mask_reg, , TB1_ram_block1a29_clock_0, , TB1_ram_block1a29_clock_enable_0, , , );
TB1_ram_block1a29 = TB1_ram_block1a29_PORT_A_data_out[0];


--TB1_ram_block1a13 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a13
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a13_PORT_A_data_in = J1L40;
TB1_ram_block1a13_PORT_A_data_in_reg = DFFE(TB1_ram_block1a13_PORT_A_data_in, TB1_ram_block1a13_clock_0, , , TB1_ram_block1a13_clock_enable_0);
TB1_ram_block1a13_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a13_PORT_A_address_reg = DFFE(TB1_ram_block1a13_PORT_A_address, TB1_ram_block1a13_clock_0, , , TB1_ram_block1a13_clock_enable_0);
TB1_ram_block1a13_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a13_PORT_B_address_reg = DFFE(TB1_ram_block1a13_PORT_B_address, TB1_ram_block1a13_clock_0, , , TB1_ram_block1a13_clock_enable_0);
TB1_ram_block1a13_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a13_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a13_PORT_A_write_enable, TB1_ram_block1a13_clock_0, , , TB1_ram_block1a13_clock_enable_0);
TB1_ram_block1a13_PORT_A_byte_mask = T1L53;
TB1_ram_block1a13_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a13_PORT_A_byte_mask, TB1_ram_block1a13_clock_0, , , TB1_ram_block1a13_clock_enable_0);
TB1_ram_block1a13_clock_0 = CLOCK_50;
TB1_ram_block1a13_clock_enable_0 = T1L38;
TB1_ram_block1a13_PORT_A_data_out = MEMORY(TB1_ram_block1a13_PORT_A_data_in_reg, , TB1_ram_block1a13_PORT_A_address_reg, TB1_ram_block1a13_PORT_B_address_reg, TB1_ram_block1a13_PORT_A_write_enable_reg, , TB1_ram_block1a13_PORT_A_byte_mask_reg, , TB1_ram_block1a13_clock_0, , TB1_ram_block1a13_clock_enable_0, , , );
TB1_ram_block1a13 = TB1_ram_block1a13_PORT_A_data_out[0];


--VB1L14 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[13]~446
VB1L14 = TB1_address_reg_a[0] & TB1_ram_block1a29 # !TB1_address_reg_a[0] & (TB1_ram_block1a13);


--TB1_ram_block1a27 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a27
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a27_PORT_A_data_in = J1L38;
TB1_ram_block1a27_PORT_A_data_in_reg = DFFE(TB1_ram_block1a27_PORT_A_data_in, TB1_ram_block1a27_clock_0, , , TB1_ram_block1a27_clock_enable_0);
TB1_ram_block1a27_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a27_PORT_A_address_reg = DFFE(TB1_ram_block1a27_PORT_A_address, TB1_ram_block1a27_clock_0, , , TB1_ram_block1a27_clock_enable_0);
TB1_ram_block1a27_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a27_PORT_B_address_reg = DFFE(TB1_ram_block1a27_PORT_B_address, TB1_ram_block1a27_clock_0, , , TB1_ram_block1a27_clock_enable_0);
TB1_ram_block1a27_PORT_A_write_enable = UB1L3;
TB1_ram_block1a27_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a27_PORT_A_write_enable, TB1_ram_block1a27_clock_0, , , TB1_ram_block1a27_clock_enable_0);
TB1_ram_block1a27_PORT_A_byte_mask = T1L53;
TB1_ram_block1a27_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a27_PORT_A_byte_mask, TB1_ram_block1a27_clock_0, , , TB1_ram_block1a27_clock_enable_0);
TB1_ram_block1a27_clock_0 = CLOCK_50;
TB1_ram_block1a27_clock_enable_0 = !T1L38;
TB1_ram_block1a27_PORT_A_data_out = MEMORY(TB1_ram_block1a27_PORT_A_data_in_reg, , TB1_ram_block1a27_PORT_A_address_reg, TB1_ram_block1a27_PORT_B_address_reg, TB1_ram_block1a27_PORT_A_write_enable_reg, , TB1_ram_block1a27_PORT_A_byte_mask_reg, , TB1_ram_block1a27_clock_0, , TB1_ram_block1a27_clock_enable_0, , , );
TB1_ram_block1a27 = TB1_ram_block1a27_PORT_A_data_out[0];


--TB1_ram_block1a11 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ram_block1a11
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 16
--Port A Input: Registered, Port A Output: Un-registered
TB1_ram_block1a11_PORT_A_data_in = J1L38;
TB1_ram_block1a11_PORT_A_data_in_reg = DFFE(TB1_ram_block1a11_PORT_A_data_in, TB1_ram_block1a11_clock_0, , , TB1_ram_block1a11_clock_enable_0);
TB1_ram_block1a11_PORT_A_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a11_PORT_A_address_reg = DFFE(TB1_ram_block1a11_PORT_A_address, TB1_ram_block1a11_clock_0, , , TB1_ram_block1a11_clock_enable_0);
TB1_ram_block1a11_PORT_B_address = BUS(T1L26, T1L27, T1L28, T1L29, T1L30, T1L31, T1L32, T1L33, T1L34, T1L35, T1L36, T1L37);
TB1_ram_block1a11_PORT_B_address_reg = DFFE(TB1_ram_block1a11_PORT_B_address, TB1_ram_block1a11_clock_0, , , TB1_ram_block1a11_clock_enable_0);
TB1_ram_block1a11_PORT_A_write_enable = UB1_eq_node[0];
TB1_ram_block1a11_PORT_A_write_enable_reg = DFFE(TB1_ram_block1a11_PORT_A_write_enable, TB1_ram_block1a11_clock_0, , , TB1_ram_block1a11_clock_enable_0);
TB1_ram_block1a11_PORT_A_byte_mask = T1L53;
TB1_ram_block1a11_PORT_A_byte_mask_reg = DFFE(TB1_ram_block1a11_PORT_A_byte_mask, TB1_ram_block1a11_clock_0, , , TB1_ram_block1a11_clock_enable_0);
TB1_ram_block1a11_clock_0 = CLOCK_50;
TB1_ram_block1a11_clock_enable_0 = T1L38;
TB1_ram_block1a11_PORT_A_data_out = MEMORY(TB1_ram_block1a11_PORT_A_data_in_reg, , TB1_ram_block1a11_PORT_A_address_reg, TB1_ram_block1a11_PORT_B_address_reg, TB1_ram_block1a11_PORT_A_write_enable_reg, , TB1_ram_block1a11_PORT_A_byte_mask_reg, , TB1_ram_block1a11_clock_0, , TB1_ram_block1a11_clock_enable_0, , , );
TB1_ram_block1a11 = TB1_ram_block1a11_PORT_A_data_out[0];


--VB1L12 is DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2|result_node[11]~447
VB1L12 = TB1_address_reg_a[0] & TB1_ram_block1a27 # !TB1_address_reg_a[0] & (TB1_ram_block1a11);


--H1L32 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_implicit_dst_eretaddr~144
H1L32 = AMPP_FUNCTION(H1_D_iw[16], H1L15, H1_D_iw[14], H1_D_iw[15]);


--H1L49 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[0]~606
H1L49 = AMPP_FUNCTION(H1L33, H1L35, H1L32);


--H1L58 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[4]~607
H1L58 = AMPP_FUNCTION(H1_D_iw[21], H1_D_iw[26], H1L14);


--H1L55 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[2]~608
H1L55 = AMPP_FUNCTION(H1_D_iw[19], H1_D_iw[24], H1L14);


--H1L50 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[0]~609
H1L50 = AMPP_FUNCTION(H1_D_iw[17], H1_D_iw[22], H1L14);


--A1L104 is rtl~2847
A1L104 = H1L49 & !H1L58 & !H1L55 & !H1L50;


--H1L52 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[1]~610
H1L52 = AMPP_FUNCTION(H1_D_iw[18], H1_D_iw[23], H1L14);


--H1L53 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[1]~611
H1L53 = AMPP_FUNCTION(H1L33, H1L52, H1L32);


--H1L54 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[1]~612
H1L54 = AMPP_FUNCTION(H1L53, H1L34, A1L67, A1L73);


--H1L57 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[3]~613
H1L57 = AMPP_FUNCTION(H1_D_iw[20], H1_D_iw[25], H1L14, H1L49);


--H1L98 is DE2_Board:inst|cpu_0:the_cpu_0|D_wr_dst_reg~87
H1L98 = AMPP_FUNCTION(A1L104, H1L54, H1L57, H1L99);


--H1L51 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[0]~614
H1L51 = AMPP_FUNCTION(H1L35, H1L32, H1L50, H1L33);


--DB1_q_a[27] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[27]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[27]_PORT_A_data_in = H1_d_writedata[27];
DB1_q_a[27]_PORT_A_data_in_reg = DFFE(DB1_q_a[27]_PORT_A_data_in, DB1_q_a[27]_clock_0, , , );
DB1_q_a[27]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[27]_PORT_A_address_reg = DFFE(DB1_q_a[27]_PORT_A_address, DB1_q_a[27]_clock_0, , , );
DB1_q_a[27]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[27]_PORT_B_address_reg = DFFE(DB1_q_a[27]_PORT_B_address, DB1_q_a[27]_clock_0, , , );
DB1_q_a[27]_PORT_A_write_enable = L1L1;
DB1_q_a[27]_PORT_A_write_enable_reg = DFFE(DB1_q_a[27]_PORT_A_write_enable, DB1_q_a[27]_clock_0, , , );
DB1_q_a[27]_PORT_A_byte_mask = M1L25;
DB1_q_a[27]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[27]_PORT_A_byte_mask, DB1_q_a[27]_clock_0, , , );
DB1_q_a[27]_clock_0 = CLOCK_50;
DB1_q_a[27]_PORT_A_data_out = MEMORY(DB1_q_a[27]_PORT_A_data_in_reg, , DB1_q_a[27]_PORT_A_address_reg, DB1_q_a[27]_PORT_B_address_reg, DB1_q_a[27]_PORT_A_write_enable_reg, , DB1_q_a[27]_PORT_A_byte_mask_reg, , DB1_q_a[27]_clock_0, , , , , );
DB1_q_a[27] = DB1_q_a[27]_PORT_A_data_out[0];


--EB1_q_a[27] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[27]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[27]_PORT_A_data_in = H1_d_writedata[27];
EB1_q_a[27]_PORT_A_data_in_reg = DFFE(EB1_q_a[27]_PORT_A_data_in, EB1_q_a[27]_clock_0, , , );
EB1_q_a[27]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[27]_PORT_A_address_reg = DFFE(EB1_q_a[27]_PORT_A_address, EB1_q_a[27]_clock_0, , , );
EB1_q_a[27]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[27]_PORT_B_address_reg = DFFE(EB1_q_a[27]_PORT_B_address, EB1_q_a[27]_clock_0, , , );
EB1_q_a[27]_PORT_A_write_enable = GND;
EB1_q_a[27]_PORT_A_write_enable_reg = DFFE(EB1_q_a[27]_PORT_A_write_enable, EB1_q_a[27]_clock_0, , , );
EB1_q_a[27]_PORT_A_byte_mask = P1L31;
EB1_q_a[27]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[27]_PORT_A_byte_mask, EB1_q_a[27]_clock_0, , , );
EB1_q_a[27]_clock_0 = CLOCK_50;
EB1_q_a[27]_PORT_A_data_out = MEMORY(EB1_q_a[27]_PORT_A_data_in_reg, , EB1_q_a[27]_PORT_A_address_reg, EB1_q_a[27]_PORT_B_address_reg, EB1_q_a[27]_PORT_A_write_enable_reg, , EB1_q_a[27]_PORT_A_byte_mask_reg, , EB1_q_a[27]_clock_0, , , , , );
EB1_q_a[27] = EB1_q_a[27]_PORT_A_data_out[0];


--H1L500 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3166
H1L500 = AMPP_FUNCTION(DB1_q_a[27], EB1_q_a[27], P1L14, M1L10);


--H1L501 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3167
H1L501 = AMPP_FUNCTION(H1L500, H1L524, VB1L12, T1L17);


--DB1_q_a[28] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[28]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[28]_PORT_A_data_in = H1_d_writedata[28];
DB1_q_a[28]_PORT_A_data_in_reg = DFFE(DB1_q_a[28]_PORT_A_data_in, DB1_q_a[28]_clock_0, , , );
DB1_q_a[28]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[28]_PORT_A_address_reg = DFFE(DB1_q_a[28]_PORT_A_address, DB1_q_a[28]_clock_0, , , );
DB1_q_a[28]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[28]_PORT_B_address_reg = DFFE(DB1_q_a[28]_PORT_B_address, DB1_q_a[28]_clock_0, , , );
DB1_q_a[28]_PORT_A_write_enable = L1L1;
DB1_q_a[28]_PORT_A_write_enable_reg = DFFE(DB1_q_a[28]_PORT_A_write_enable, DB1_q_a[28]_clock_0, , , );
DB1_q_a[28]_PORT_A_byte_mask = M1L25;
DB1_q_a[28]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[28]_PORT_A_byte_mask, DB1_q_a[28]_clock_0, , , );
DB1_q_a[28]_clock_0 = CLOCK_50;
DB1_q_a[28]_PORT_A_data_out = MEMORY(DB1_q_a[28]_PORT_A_data_in_reg, , DB1_q_a[28]_PORT_A_address_reg, DB1_q_a[28]_PORT_B_address_reg, DB1_q_a[28]_PORT_A_write_enable_reg, , DB1_q_a[28]_PORT_A_byte_mask_reg, , DB1_q_a[28]_clock_0, , , , , );
DB1_q_a[28] = DB1_q_a[28]_PORT_A_data_out[0];


--EB1_q_a[28] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[28]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[28]_PORT_A_data_in = H1_d_writedata[28];
EB1_q_a[28]_PORT_A_data_in_reg = DFFE(EB1_q_a[28]_PORT_A_data_in, EB1_q_a[28]_clock_0, , , );
EB1_q_a[28]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[28]_PORT_A_address_reg = DFFE(EB1_q_a[28]_PORT_A_address, EB1_q_a[28]_clock_0, , , );
EB1_q_a[28]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[28]_PORT_B_address_reg = DFFE(EB1_q_a[28]_PORT_B_address, EB1_q_a[28]_clock_0, , , );
EB1_q_a[28]_PORT_A_write_enable = GND;
EB1_q_a[28]_PORT_A_write_enable_reg = DFFE(EB1_q_a[28]_PORT_A_write_enable, EB1_q_a[28]_clock_0, , , );
EB1_q_a[28]_PORT_A_byte_mask = P1L31;
EB1_q_a[28]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[28]_PORT_A_byte_mask, EB1_q_a[28]_clock_0, , , );
EB1_q_a[28]_clock_0 = CLOCK_50;
EB1_q_a[28]_PORT_A_data_out = MEMORY(EB1_q_a[28]_PORT_A_data_in_reg, , EB1_q_a[28]_PORT_A_address_reg, EB1_q_a[28]_PORT_B_address_reg, EB1_q_a[28]_PORT_A_write_enable_reg, , EB1_q_a[28]_PORT_A_byte_mask_reg, , EB1_q_a[28]_clock_0, , , , , );
EB1_q_a[28] = EB1_q_a[28]_PORT_A_data_out[0];


--H1L502 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3168
H1L502 = AMPP_FUNCTION(DB1_q_a[28], EB1_q_a[28], P1L14, M1L10);


--H1L503 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3169
H1L503 = AMPP_FUNCTION(H1L502, H1L525, VB1L13, T1L17);


--H1L56 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[2]~615
H1L56 = AMPP_FUNCTION(H1L35, H1L32, H1L55, H1L33);


--DB1_q_a[29] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[29]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[29]_PORT_A_data_in = H1_d_writedata[29];
DB1_q_a[29]_PORT_A_data_in_reg = DFFE(DB1_q_a[29]_PORT_A_data_in, DB1_q_a[29]_clock_0, , , );
DB1_q_a[29]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[29]_PORT_A_address_reg = DFFE(DB1_q_a[29]_PORT_A_address, DB1_q_a[29]_clock_0, , , );
DB1_q_a[29]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[29]_PORT_B_address_reg = DFFE(DB1_q_a[29]_PORT_B_address, DB1_q_a[29]_clock_0, , , );
DB1_q_a[29]_PORT_A_write_enable = L1L1;
DB1_q_a[29]_PORT_A_write_enable_reg = DFFE(DB1_q_a[29]_PORT_A_write_enable, DB1_q_a[29]_clock_0, , , );
DB1_q_a[29]_PORT_A_byte_mask = M1L25;
DB1_q_a[29]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[29]_PORT_A_byte_mask, DB1_q_a[29]_clock_0, , , );
DB1_q_a[29]_clock_0 = CLOCK_50;
DB1_q_a[29]_PORT_A_data_out = MEMORY(DB1_q_a[29]_PORT_A_data_in_reg, , DB1_q_a[29]_PORT_A_address_reg, DB1_q_a[29]_PORT_B_address_reg, DB1_q_a[29]_PORT_A_write_enable_reg, , DB1_q_a[29]_PORT_A_byte_mask_reg, , DB1_q_a[29]_clock_0, , , , , );
DB1_q_a[29] = DB1_q_a[29]_PORT_A_data_out[0];


--EB1_q_a[29] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[29]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[29]_PORT_A_data_in = H1_d_writedata[29];
EB1_q_a[29]_PORT_A_data_in_reg = DFFE(EB1_q_a[29]_PORT_A_data_in, EB1_q_a[29]_clock_0, , , );
EB1_q_a[29]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[29]_PORT_A_address_reg = DFFE(EB1_q_a[29]_PORT_A_address, EB1_q_a[29]_clock_0, , , );
EB1_q_a[29]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[29]_PORT_B_address_reg = DFFE(EB1_q_a[29]_PORT_B_address, EB1_q_a[29]_clock_0, , , );
EB1_q_a[29]_PORT_A_write_enable = GND;
EB1_q_a[29]_PORT_A_write_enable_reg = DFFE(EB1_q_a[29]_PORT_A_write_enable, EB1_q_a[29]_clock_0, , , );
EB1_q_a[29]_PORT_A_byte_mask = P1L31;
EB1_q_a[29]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[29]_PORT_A_byte_mask, EB1_q_a[29]_clock_0, , , );
EB1_q_a[29]_clock_0 = CLOCK_50;
EB1_q_a[29]_PORT_A_data_out = MEMORY(EB1_q_a[29]_PORT_A_data_in_reg, , EB1_q_a[29]_PORT_A_address_reg, EB1_q_a[29]_PORT_B_address_reg, EB1_q_a[29]_PORT_A_write_enable_reg, , EB1_q_a[29]_PORT_A_byte_mask_reg, , EB1_q_a[29]_clock_0, , , , , );
EB1_q_a[29] = EB1_q_a[29]_PORT_A_data_out[0];


--H1L504 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3170
H1L504 = AMPP_FUNCTION(DB1_q_a[29], EB1_q_a[29], P1L14, M1L10);


--H1L505 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3171
H1L505 = AMPP_FUNCTION(H1L504, H1L526, VB1L14, T1L17);


--DB1_q_a[30] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[30]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[30]_PORT_A_data_in = H1_d_writedata[30];
DB1_q_a[30]_PORT_A_data_in_reg = DFFE(DB1_q_a[30]_PORT_A_data_in, DB1_q_a[30]_clock_0, , , );
DB1_q_a[30]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[30]_PORT_A_address_reg = DFFE(DB1_q_a[30]_PORT_A_address, DB1_q_a[30]_clock_0, , , );
DB1_q_a[30]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[30]_PORT_B_address_reg = DFFE(DB1_q_a[30]_PORT_B_address, DB1_q_a[30]_clock_0, , , );
DB1_q_a[30]_PORT_A_write_enable = L1L1;
DB1_q_a[30]_PORT_A_write_enable_reg = DFFE(DB1_q_a[30]_PORT_A_write_enable, DB1_q_a[30]_clock_0, , , );
DB1_q_a[30]_PORT_A_byte_mask = M1L25;
DB1_q_a[30]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[30]_PORT_A_byte_mask, DB1_q_a[30]_clock_0, , , );
DB1_q_a[30]_clock_0 = CLOCK_50;
DB1_q_a[30]_PORT_A_data_out = MEMORY(DB1_q_a[30]_PORT_A_data_in_reg, , DB1_q_a[30]_PORT_A_address_reg, DB1_q_a[30]_PORT_B_address_reg, DB1_q_a[30]_PORT_A_write_enable_reg, , DB1_q_a[30]_PORT_A_byte_mask_reg, , DB1_q_a[30]_clock_0, , , , , );
DB1_q_a[30] = DB1_q_a[30]_PORT_A_data_out[0];


--EB1_q_a[30] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[30]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[30]_PORT_A_data_in = H1_d_writedata[30];
EB1_q_a[30]_PORT_A_data_in_reg = DFFE(EB1_q_a[30]_PORT_A_data_in, EB1_q_a[30]_clock_0, , , );
EB1_q_a[30]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[30]_PORT_A_address_reg = DFFE(EB1_q_a[30]_PORT_A_address, EB1_q_a[30]_clock_0, , , );
EB1_q_a[30]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[30]_PORT_B_address_reg = DFFE(EB1_q_a[30]_PORT_B_address, EB1_q_a[30]_clock_0, , , );
EB1_q_a[30]_PORT_A_write_enable = GND;
EB1_q_a[30]_PORT_A_write_enable_reg = DFFE(EB1_q_a[30]_PORT_A_write_enable, EB1_q_a[30]_clock_0, , , );
EB1_q_a[30]_PORT_A_byte_mask = P1L31;
EB1_q_a[30]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[30]_PORT_A_byte_mask, EB1_q_a[30]_clock_0, , , );
EB1_q_a[30]_clock_0 = CLOCK_50;
EB1_q_a[30]_PORT_A_data_out = MEMORY(EB1_q_a[30]_PORT_A_data_in_reg, , EB1_q_a[30]_PORT_A_address_reg, EB1_q_a[30]_PORT_B_address_reg, EB1_q_a[30]_PORT_A_write_enable_reg, , EB1_q_a[30]_PORT_A_byte_mask_reg, , EB1_q_a[30]_clock_0, , , , , );
EB1_q_a[30] = EB1_q_a[30]_PORT_A_data_out[0];


--H1L506 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3172
H1L506 = AMPP_FUNCTION(DB1_q_a[30], EB1_q_a[30], P1L14, M1L10);


--H1L507 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3173
H1L507 = AMPP_FUNCTION(H1L506, H1L527, VB1L15, T1L17);


--H1L59 is DE2_Board:inst|cpu_0:the_cpu_0|D_dst_regnum[4]~616
H1L59 = AMPP_FUNCTION(H1L35, H1L32, H1L58, H1L33);


--DB1_q_a[31] is DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|q_a[31]
--RAM Block Operation Mode: Single Port
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
DB1_q_a[31]_PORT_A_data_in = H1_d_writedata[31];
DB1_q_a[31]_PORT_A_data_in_reg = DFFE(DB1_q_a[31]_PORT_A_data_in, DB1_q_a[31]_clock_0, , , );
DB1_q_a[31]_PORT_A_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[31]_PORT_A_address_reg = DFFE(DB1_q_a[31]_PORT_A_address, DB1_q_a[31]_clock_0, , , );
DB1_q_a[31]_PORT_B_address = BUS(M1L11, M1L12, M1L13, M1L14, M1L15, M1L16, M1L17, M1L18);
DB1_q_a[31]_PORT_B_address_reg = DFFE(DB1_q_a[31]_PORT_B_address, DB1_q_a[31]_clock_0, , , );
DB1_q_a[31]_PORT_A_write_enable = L1L1;
DB1_q_a[31]_PORT_A_write_enable_reg = DFFE(DB1_q_a[31]_PORT_A_write_enable, DB1_q_a[31]_clock_0, , , );
DB1_q_a[31]_PORT_A_byte_mask = M1L25;
DB1_q_a[31]_PORT_A_byte_mask_reg = DFFE(DB1_q_a[31]_PORT_A_byte_mask, DB1_q_a[31]_clock_0, , , );
DB1_q_a[31]_clock_0 = CLOCK_50;
DB1_q_a[31]_PORT_A_data_out = MEMORY(DB1_q_a[31]_PORT_A_data_in_reg, , DB1_q_a[31]_PORT_A_address_reg, DB1_q_a[31]_PORT_B_address_reg, DB1_q_a[31]_PORT_A_write_enable_reg, , DB1_q_a[31]_PORT_A_byte_mask_reg, , DB1_q_a[31]_clock_0, , , , , );
DB1_q_a[31] = DB1_q_a[31]_PORT_A_data_out[0];


--EB1_q_a[31] is DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|q_a[31]
--RAM Block Operation Mode: Single Port
--Port A Depth: 896, Port A Width: 1
--Port A Logical Depth: 896, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
EB1_q_a[31]_PORT_A_data_in = H1_d_writedata[31];
EB1_q_a[31]_PORT_A_data_in_reg = DFFE(EB1_q_a[31]_PORT_A_data_in, EB1_q_a[31]_clock_0, , , );
EB1_q_a[31]_PORT_A_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[31]_PORT_A_address_reg = DFFE(EB1_q_a[31]_PORT_A_address, EB1_q_a[31]_clock_0, , , );
EB1_q_a[31]_PORT_B_address = BUS(P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L23, P1L24);
EB1_q_a[31]_PORT_B_address_reg = DFFE(EB1_q_a[31]_PORT_B_address, EB1_q_a[31]_clock_0, , , );
EB1_q_a[31]_PORT_A_write_enable = GND;
EB1_q_a[31]_PORT_A_write_enable_reg = DFFE(EB1_q_a[31]_PORT_A_write_enable, EB1_q_a[31]_clock_0, , , );
EB1_q_a[31]_PORT_A_byte_mask = P1L31;
EB1_q_a[31]_PORT_A_byte_mask_reg = DFFE(EB1_q_a[31]_PORT_A_byte_mask, EB1_q_a[31]_clock_0, , , );
EB1_q_a[31]_clock_0 = CLOCK_50;
EB1_q_a[31]_PORT_A_data_out = MEMORY(EB1_q_a[31]_PORT_A_data_in_reg, , EB1_q_a[31]_PORT_A_address_reg, EB1_q_a[31]_PORT_B_address_reg, EB1_q_a[31]_PORT_A_write_enable_reg, , EB1_q_a[31]_PORT_A_byte_mask_reg, , EB1_q_a[31]_clock_0, , , , , );
EB1_q_a[31] = EB1_q_a[31]_PORT_A_data_out[0];


--H1L508 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3174
H1L508 = AMPP_FUNCTION(DB1_q_a[31], EB1_q_a[31], P1L14, M1L10);


--H1L509 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3175
H1L509 = AMPP_FUNCTION(H1L508, H1L528, VB1L16, T1L17);


--J1_registered_cpu_0_data_master_readdata[22] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[22]
J1_registered_cpu_0_data_master_readdata[22] = DFFEAS(Q1L47, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave is DE2_Board:inst|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave
R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave = !A1L98 # !A1L97 # !H1_W_alu_result[16] # !P1L7;


--J1L107 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~166
J1L107 = J1_registered_cpu_0_data_master_readdata[22] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;


--J1_dbs_8_reg_segment_2[6] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6]
J1_dbs_8_reg_segment_2[6] = DFFEAS(W1_incoming_tri_state_bridge_0_data[6], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L96 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~3257
J1L96 = DB1_q_a[22] & (J1_dbs_8_reg_segment_2[6] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[22] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[6] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L97 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~3258
J1L97 = EB1_q_a[22] & (VB1L7 # !T1L11) # !EB1_q_a[22] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (VB1L7 # !T1L11);


--A1L105 is rtl~2848
A1L105 = H1_W_alu_result[18] & !H1_W_alu_result[16];


--G1_asmi_asmi_control_port_chipselect is DE2_Board:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port|asmi_asmi_control_port_chipselect
G1_asmi_asmi_control_port_chipselect = P1L7 & H1_W_alu_result[17] & A1L97 & A1L105;


--J1L98 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[22]~3259
J1L98 = J1L107 & J1L96 & J1L97 & !G1_asmi_asmi_control_port_chipselect;


--H1_R_ctrl_ld_signed is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_ld_signed
H1_R_ctrl_ld_signed = AMPP_FUNCTION(CLOCK_50, H1L36, E1_data_out);


--A1L106 is rtl~2849
A1L106 = H1_D_iw[3] & !H1_D_iw[4];


--H1L951 is DE2_Board:inst|cpu_0:the_cpu_0|av_fill_bit~112
H1L951 = AMPP_FUNCTION(H1_R_ctrl_ld_signed, H1_av_ld_byte1_data[7], H1_av_ld_byte0_data[7], A1L106);


--H1L1057 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[6]~16
H1L1057 = AMPP_FUNCTION(J1L98, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[6] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[6]
H1_av_ld_byte3_data[6] = AMPP_FUNCTION(CLOCK_50, H1L1076, E1_data_out, H1L1103);


--H1L1102 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_rshift8~129
H1L1102 = AMPP_FUNCTION(H1_W_alu_result[1], H1_W_alu_result[0], H1_av_ld_align_cycle[0], H1_av_ld_align_cycle[1]);


--H1L1103 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_rshift8~130
H1L1103 = AMPP_FUNCTION(H1_av_ld_aligning_data, H1L1102);


--J1L32 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[5]~161
J1L32 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[21] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[5]);


--M1L25 is DE2_Board:inst|data_RAM_s1_arbitrator:the_data_RAM_s1|data_RAM_s1_byteenable[3]~19
M1L25 = H1_d_byteenable[3] # M1L6 & !M1_data_RAM_s1_arb_addend[1] # !M1L1;


--P1L31 is DE2_Board:inst|firmware_ROM_s1_arbitrator:the_firmware_ROM_s1|firmware_ROM_s1_byteenable[3]~19
P1L31 = H1_d_byteenable[3] # P1L12 & !P1_firmware_ROM_s1_arb_addend[1] # !P1L4;


--J1L37 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[10]~162
J1L37 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[26] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[10]);


--T1L53 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_byteenable[1]~9
T1L53 = J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[3] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[1]) # !T1L56;


--A1L107 is rtl~2850
A1L107 = !H1_W_alu_result[4] & !H1_W_alu_result[3];


--A1L108 is rtl~2851
A1L108 = A1L95 & A1L96;


--A1L109 is rtl~2852
A1L109 = A1L94 & A1L108 & A1L105 & !H1_W_alu_result[5];


--V1L1 is DE2_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_0_data_master_qualified_request_sysid_control_slave~35
V1L1 = H1_d_read & A1L107 & A1L109 & !H1_W_alu_result[17];


--H1L1071 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~543
H1L1071 = AMPP_FUNCTION(H1_W_alu_result[2], V1L1, G1_asmi_asmi_control_port_chipselect);


--J1_dbs_8_reg_segment_2[5] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[5]
J1_dbs_8_reg_segment_2[5] = DFFEAS(W1_incoming_tri_state_bridge_0_data[5], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L93 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3260
J1L93 = DB1_q_a[21] & (J1_dbs_8_reg_segment_2[5] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[21] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[5] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L105 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~101
J1L105 = H1_W_alu_result[16] # EB1_q_a[21] # !P1L10 # !P1L9;


--J1_registered_cpu_0_data_master_readdata[21] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[21]
J1_registered_cpu_0_data_master_readdata[21] = DFFEAS(Q1L48, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L94 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3261
J1L94 = J1L93 & J1L105 & (J1_registered_cpu_0_data_master_readdata[21] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--J1L95 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3262
J1L95 = H1L1071 & J1L94 & (VB1L6 # !T1L11);


--H1L1054 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[5]~17
H1L1054 = AMPP_FUNCTION(J1L95, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[5] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[5]
H1_av_ld_byte3_data[5] = AMPP_FUNCTION(CLOCK_50, H1L1080, E1_data_out, H1L1103);


--J1L36 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[9]~163
J1L36 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[25] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[9]);


--J1_dbs_8_reg_segment_2[4] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[4]
J1_dbs_8_reg_segment_2[4] = DFFEAS(W1_incoming_tri_state_bridge_0_data[4], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L90 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~3263
J1L90 = DB1_q_a[20] & (J1_dbs_8_reg_segment_2[4] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[20] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[4] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L104 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~100
J1L104 = H1_W_alu_result[16] # EB1_q_a[20] # !P1L10 # !P1L9;


--J1_registered_cpu_0_data_master_readdata[20] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[20]
J1_registered_cpu_0_data_master_readdata[20] = DFFEAS(Q1L49, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L91 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~3264
J1L91 = J1L90 & J1L104 & (J1_registered_cpu_0_data_master_readdata[20] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--J1L92 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[20]~3265
J1L92 = H1L1071 & J1L91 & (VB1L5 # !T1L11);


--H1L1051 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[4]~18
H1L1051 = AMPP_FUNCTION(J1L92, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[4] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[4]
H1_av_ld_byte3_data[4] = AMPP_FUNCTION(CLOCK_50, H1L1083, E1_data_out, H1L1103);


--J1L35 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[8]~164
J1L35 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[24] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[8]);


--J1_dbs_8_reg_segment_2[3] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[3]
J1_dbs_8_reg_segment_2[3] = DFFEAS(W1_incoming_tri_state_bridge_0_data[3], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L87 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~3266
J1L87 = DB1_q_a[19] & (J1_dbs_8_reg_segment_2[3] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[19] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[3] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L103 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~99
J1L103 = H1_W_alu_result[16] # EB1_q_a[19] # !P1L10 # !P1L9;


--J1_registered_cpu_0_data_master_readdata[19] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[19]
J1_registered_cpu_0_data_master_readdata[19] = DFFEAS(Q1L50, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L88 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~3267
J1L88 = J1L87 & J1L103 & (J1_registered_cpu_0_data_master_readdata[19] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--J1L89 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[19]~3268
J1L89 = H1L1071 & J1L88 & (VB1L4 # !T1L11);


--H1L1048 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[3]~19
H1L1048 = AMPP_FUNCTION(J1L89, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[3] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[3]
H1_av_ld_byte3_data[3] = AMPP_FUNCTION(CLOCK_50, H1L1087, E1_data_out, H1L1103);


--J1L34 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[7]~165
J1L34 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[23] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[7]);


--J1_registered_cpu_0_data_master_readdata[18] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[18]
J1_registered_cpu_0_data_master_readdata[18] = DFFEAS(Q1L51, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L106 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~162
J1L106 = J1_registered_cpu_0_data_master_readdata[18] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;


--J1_dbs_8_reg_segment_2[2] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[2]
J1_dbs_8_reg_segment_2[2] = DFFEAS(W1_incoming_tri_state_bridge_0_data[2], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L84 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~3269
J1L84 = DB1_q_a[18] & (J1_dbs_8_reg_segment_2[2] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[18] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[2] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L85 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~3270
J1L85 = EB1_q_a[18] & (VB1L3 # !T1L11) # !EB1_q_a[18] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (VB1L3 # !T1L11);


--J1L86 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[18]~3271
J1L86 = J1L106 & J1L84 & J1L85 & !G1_asmi_asmi_control_port_chipselect;


--H1L1045 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[2]~20
H1L1045 = AMPP_FUNCTION(J1L86, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[2] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[2]
H1_av_ld_byte3_data[2] = AMPP_FUNCTION(CLOCK_50, H1L1090, E1_data_out, H1L1103);


--J1L33 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[6]~166
J1L33 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[22] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[6]);


--J1_dbs_8_reg_segment_2[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[1]
J1_dbs_8_reg_segment_2[1] = DFFEAS(W1_incoming_tri_state_bridge_0_data[1], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L80 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~3272
J1L80 = DB1_q_a[17] & (J1_dbs_8_reg_segment_2[1] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[17] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[1] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L81 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~3273
J1L81 = J1L80 & !G1_asmi_asmi_control_port_chipselect & !V1L1;


--J1L82 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~3274
J1L82 = EB1_q_a[17] & (VB1L2 # !T1L11) # !EB1_q_a[17] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (VB1L2 # !T1L11);


--J1_registered_cpu_0_data_master_readdata[17] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[17]
J1_registered_cpu_0_data_master_readdata[17] = DFFEAS(Q1L52, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L83 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[17]~3275
J1L83 = J1L81 & J1L82 & (J1_registered_cpu_0_data_master_readdata[17] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1042 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[1]~21
H1L1042 = AMPP_FUNCTION(J1L83, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[1] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[1]
H1_av_ld_byte3_data[1] = AMPP_FUNCTION(CLOCK_50, H1L1094, E1_data_out, H1L1103);


--J1_dbs_8_reg_segment_2[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[0]
J1_dbs_8_reg_segment_2[0] = DFFEAS(W1_incoming_tri_state_bridge_0_data[0], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L76 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~3276
J1L76 = DB1_q_a[16] & (J1_dbs_8_reg_segment_2[0] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[16] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[0] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L77 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~3277
J1L77 = EB1_q_a[16] & (VB1L1 # !T1L11) # !EB1_q_a[16] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (VB1L1 # !T1L11);


--J1_registered_cpu_0_data_master_readdata[16] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[16]
J1_registered_cpu_0_data_master_readdata[16] = DFFEAS(Q1L53, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L78 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~3278
J1L78 = J1L77 & (J1_registered_cpu_0_data_master_readdata[16] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--J1L79 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[16]~3279
J1L79 = J1L76 & J1L78 & !G1_asmi_asmi_control_port_chipselect & !V1L1;


--H1L1039 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[0]~22
H1L1039 = AMPP_FUNCTION(J1L79, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte3_data[0] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[0]
H1_av_ld_byte3_data[0] = AMPP_FUNCTION(CLOCK_50, H1L1098, E1_data_out, H1L1103);


--J1L31 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[4]~167
J1L31 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[20] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[4]);


--X1_data_to_cpu[15] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[15]
X1_data_to_cpu[15] = DFFEAS(X1L167, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1_dbs_16_reg_segment_0[15] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[15]
J1_dbs_16_reg_segment_0[15] = DFFEAS(VB1L16, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L72 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~3280
J1L72 = DB1_q_a[15] & (!J1_dbs_16_reg_segment_0[15] & T1L11) # !DB1_q_a[15] & (M1_cpu_0_data_master_requests_data_RAM_s1 # !J1_dbs_16_reg_segment_0[15] & T1L11);


--J1_dbs_8_reg_segment_1[7] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[7]
J1_dbs_8_reg_segment_1[7] = DFFEAS(W1_incoming_tri_state_bridge_0_data[7], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L73 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~3281
J1L73 = EB1_q_a[15] & (J1_dbs_8_reg_segment_1[7] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[15] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[7] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_registered_cpu_0_data_master_readdata[15] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[15]
J1_registered_cpu_0_data_master_readdata[15] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[15], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L74 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~3282
J1L74 = !V1L1 & J1L73 & (J1_registered_cpu_0_data_master_readdata[15] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--J1L75 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[15]~3283
J1L75 = !J1L72 & J1L74 & (X1_data_to_cpu[15] # !G1_asmi_asmi_control_port_chipselect);


--H1L1034 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[7]~32
H1L1034 = AMPP_FUNCTION(J1L75, H1L951, H1_av_ld_aligning_data);


--H1_av_ld_byte2_data[7] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[7]
H1_av_ld_byte2_data[7] = AMPP_FUNCTION(CLOCK_50, H1L1060, H1_av_ld_byte3_data[7], E1_data_out, !H1L1103);


--H1L1036 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data_en~1
H1L1036 = AMPP_FUNCTION(H1_D_iw[4], H1L1102, H1_D_iw[3], H1_av_ld_aligning_data);


--J1L30 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[3]~168
J1L30 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[19] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[3]);


--J1L111 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~276
J1L111 = !V1L1 # !H1_W_alu_result[2];


--J1_dbs_8_reg_segment_1[6] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[6]
J1_dbs_8_reg_segment_1[6] = DFFEAS(W1_incoming_tri_state_bridge_0_data[6], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L68 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~3284
J1L68 = EB1_q_a[14] & (J1_dbs_8_reg_segment_1[6] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[14] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[6] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_dbs_16_reg_segment_0[14] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[14]
J1_dbs_16_reg_segment_0[14] = DFFEAS(VB1L15, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L69 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~3285
J1L69 = DB1_q_a[14] & (J1_dbs_16_reg_segment_0[14] # !T1L11) # !DB1_q_a[14] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_16_reg_segment_0[14] # !T1L11);


--X1_data_to_cpu[14] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[14]
X1_data_to_cpu[14] = DFFEAS(X1L166, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L70 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~3286
J1L70 = J1L68 & J1L69 & (X1_data_to_cpu[14] # !G1_asmi_asmi_control_port_chipselect);


--J1_registered_cpu_0_data_master_readdata[14] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[14]
J1_registered_cpu_0_data_master_readdata[14] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[14], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L71 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[14]~3287
J1L71 = J1L111 & J1L70 & (J1_registered_cpu_0_data_master_readdata[14] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1031 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[6]~33
H1L1031 = AMPP_FUNCTION(J1L71, H1L951, H1_av_ld_aligning_data);


--J1L29 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[2]~169
J1L29 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[18] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[2]);


--J1L112 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~302
J1L112 = H1_W_alu_result[2] # !V1L1;


--J1_dbs_8_reg_segment_1[5] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[5]
J1_dbs_8_reg_segment_1[5] = DFFEAS(W1_incoming_tri_state_bridge_0_data[5], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L64 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~3288
J1L64 = EB1_q_a[13] & (J1_dbs_8_reg_segment_1[5] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[13] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[5] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_dbs_16_reg_segment_0[13] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[13]
J1_dbs_16_reg_segment_0[13] = DFFEAS(VB1L14, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L65 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~3289
J1L65 = DB1_q_a[13] & (J1_dbs_16_reg_segment_0[13] # !T1L11) # !DB1_q_a[13] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_16_reg_segment_0[13] # !T1L11);


--X1_data_to_cpu[13] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[13]
X1_data_to_cpu[13] = DFFEAS(X1L165, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L66 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~3290
J1L66 = J1L64 & J1L65 & (X1_data_to_cpu[13] # !G1_asmi_asmi_control_port_chipselect);


--J1_registered_cpu_0_data_master_readdata[13] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[13]
J1_registered_cpu_0_data_master_readdata[13] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[13], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L67 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[13]~3291
J1L67 = J1L112 & J1L66 & (J1_registered_cpu_0_data_master_readdata[13] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1028 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[5]~34
H1L1028 = AMPP_FUNCTION(J1L67, H1L951, H1_av_ld_aligning_data);


--J1L28 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[1]~170
J1L28 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[17] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[1]);


--J1_dbs_8_reg_segment_1[4] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[4]
J1_dbs_8_reg_segment_1[4] = DFFEAS(W1_incoming_tri_state_bridge_0_data[4], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L60 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~3292
J1L60 = EB1_q_a[12] & (J1_dbs_8_reg_segment_1[4] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[12] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[4] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_dbs_16_reg_segment_0[12] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[12]
J1_dbs_16_reg_segment_0[12] = DFFEAS(VB1L13, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L61 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~3293
J1L61 = DB1_q_a[12] & (J1_dbs_16_reg_segment_0[12] # !T1L11) # !DB1_q_a[12] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_16_reg_segment_0[12] # !T1L11);


--X1_data_to_cpu[12] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[12]
X1_data_to_cpu[12] = DFFEAS(X1L164, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L62 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~3294
J1L62 = J1L60 & J1L61 & (X1_data_to_cpu[12] # !G1_asmi_asmi_control_port_chipselect);


--J1_registered_cpu_0_data_master_readdata[12] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[12]
J1_registered_cpu_0_data_master_readdata[12] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[12], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L63 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[12]~3295
J1L63 = J1L112 & J1L62 & (J1_registered_cpu_0_data_master_readdata[12] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1025 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[4]~35
H1L1025 = AMPP_FUNCTION(J1L63, H1L951, H1_av_ld_aligning_data);


--J1_dbs_8_reg_segment_1[3] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[3]
J1_dbs_8_reg_segment_1[3] = DFFEAS(W1_incoming_tri_state_bridge_0_data[3], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L56 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~3296
J1L56 = EB1_q_a[11] & (J1_dbs_8_reg_segment_1[3] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[11] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[3] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_dbs_16_reg_segment_0[11] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[11]
J1_dbs_16_reg_segment_0[11] = DFFEAS(VB1L12, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L57 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~3297
J1L57 = DB1_q_a[11] & (J1_dbs_16_reg_segment_0[11] # !T1L11) # !DB1_q_a[11] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_16_reg_segment_0[11] # !T1L11);


--X1_data_to_cpu[11] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[11]
X1_data_to_cpu[11] = DFFEAS(X1L163, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L58 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~3298
J1L58 = J1L56 & J1L57 & (X1_data_to_cpu[11] # !G1_asmi_asmi_control_port_chipselect);


--J1_registered_cpu_0_data_master_readdata[31] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[31]
J1_registered_cpu_0_data_master_readdata[31] = DFFEAS(R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L59 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[11]~3299
J1L59 = J1L112 & J1L58 & (J1_registered_cpu_0_data_master_readdata[31] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1022 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[3]~36
H1L1022 = AMPP_FUNCTION(J1L59, H1L951, H1_av_ld_aligning_data);


--J1_dbs_8_reg_segment_1[2] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[2]
J1_dbs_8_reg_segment_1[2] = DFFEAS(W1_incoming_tri_state_bridge_0_data[2], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L52 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~3300
J1L52 = EB1_q_a[10] & (J1_dbs_8_reg_segment_1[2] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[10] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[2] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_dbs_16_reg_segment_0[10] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[10]
J1_dbs_16_reg_segment_0[10] = DFFEAS(VB1L11, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L53 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~3301
J1L53 = DB1_q_a[10] & (J1_dbs_16_reg_segment_0[10] # !T1L11) # !DB1_q_a[10] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_16_reg_segment_0[10] # !T1L11);


--X1_data_to_cpu[10] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[10]
X1_data_to_cpu[10] = DFFEAS(X1L169, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L54 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~3302
J1L54 = J1L52 & J1L53 & (X1_data_to_cpu[10] # !G1_asmi_asmi_control_port_chipselect);


--J1_registered_cpu_0_data_master_readdata[10] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[10]
J1_registered_cpu_0_data_master_readdata[10] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[10], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L55 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[10]~3303
J1L55 = J1L112 & J1L54 & (J1_registered_cpu_0_data_master_readdata[10] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1019 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[2]~37
H1L1019 = AMPP_FUNCTION(J1L55, H1L951, H1_av_ld_aligning_data);


--J1_dbs_8_reg_segment_1[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[1]
J1_dbs_8_reg_segment_1[1] = DFFEAS(W1_incoming_tri_state_bridge_0_data[1], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L48 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~3304
J1L48 = EB1_q_a[9] & (J1_dbs_8_reg_segment_1[1] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !EB1_q_a[9] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_8_reg_segment_1[1] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1_dbs_16_reg_segment_0[9] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[9]
J1_dbs_16_reg_segment_0[9] = DFFEAS(VB1L10, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L49 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~3305
J1L49 = DB1_q_a[9] & (J1_dbs_16_reg_segment_0[9] # !T1L11) # !DB1_q_a[9] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_16_reg_segment_0[9] # !T1L11);


--X1_data_to_cpu[9] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[9]
X1_data_to_cpu[9] = DFFEAS(X1L162, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L50 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~3306
J1L50 = J1L48 & J1L49 & (X1_data_to_cpu[9] # !G1_asmi_asmi_control_port_chipselect);


--J1_registered_cpu_0_data_master_readdata[9] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[9]
J1_registered_cpu_0_data_master_readdata[9] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[9], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L51 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[9]~3307
J1L51 = J1L111 & J1L50 & (J1_registered_cpu_0_data_master_readdata[9] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1016 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[1]~38
H1L1016 = AMPP_FUNCTION(J1L51, H1L951, H1_av_ld_aligning_data);


--J1_dbs_8_reg_segment_1[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_1[0]
J1_dbs_8_reg_segment_1[0] = DFFEAS(W1_incoming_tri_state_bridge_0_data[0], CLOCK_50, E1_data_out,  , J1L4,  ,  ,  ,  );


--J1L44 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~3308
J1L44 = DB1_q_a[8] & (J1_dbs_8_reg_segment_1[0] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[8] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_1[0] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--X1_data_to_cpu[8] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[8]
X1_data_to_cpu[8] = DFFEAS(X1L159, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L45 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~3309
J1L45 = J1L44 & (X1_data_to_cpu[8] # !G1_asmi_asmi_control_port_chipselect);


--J1_dbs_16_reg_segment_0[8] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[8]
J1_dbs_16_reg_segment_0[8] = DFFEAS(VB1L9, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--J1L46 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~3310
J1L46 = EB1_q_a[8] & (J1_dbs_16_reg_segment_0[8] # !T1L11) # !EB1_q_a[8] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (J1_dbs_16_reg_segment_0[8] # !T1L11);


--J1_registered_cpu_0_data_master_readdata[8] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[8]
J1_registered_cpu_0_data_master_readdata[8] = DFFEAS(J1L190, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L47 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[8]~3311
J1L47 = J1L45 & J1L46 & (J1_registered_cpu_0_data_master_readdata[8] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1013 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte1_data[0]~39
H1L1013 = AMPP_FUNCTION(J1L47, H1L951, H1_av_ld_aligning_data);


--J1_registered_cpu_0_data_master_readdata[7] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[7]
J1_registered_cpu_0_data_master_readdata[7] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[7], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L1006 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[7]~604
H1L1006 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[7], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[7] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[7]
J1_dbs_8_reg_segment_0[7] = DFFEAS(W1_incoming_tri_state_bridge_0_data[7], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L1007 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[7]~605
H1L1007 = AMPP_FUNCTION(EB1_q_a[7], J1_dbs_8_reg_segment_0[7], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[7] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[7]
J1_dbs_16_reg_segment_0[7] = DFFEAS(VB1L8, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L1008 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[7]~606
H1L1008 = AMPP_FUNCTION(DB1_q_a[7], J1_dbs_16_reg_segment_0[7], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[7]
X1_data_to_cpu[7] = DFFEAS(X1L156, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L1009 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[7]~607
H1L1009 = AMPP_FUNCTION(H1L1007, H1L1008, X1_data_to_cpu[7], G1_asmi_asmi_control_port_chipselect);


--H1L1010 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[7]~608
H1L1010 = AMPP_FUNCTION(H1_av_ld_byte1_data[7], H1L1006, H1L1009, H1L1103);


--H1L965 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data[2]~72
H1L965 = AMPP_FUNCTION(H1_av_ld_aligning_data, H1L1102);


--J1_registered_cpu_0_data_master_readdata[6] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[6]
J1_registered_cpu_0_data_master_readdata[6] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[6], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L1001 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[6]~609
H1L1001 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[6], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[6] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[6]
J1_dbs_8_reg_segment_0[6] = DFFEAS(W1_incoming_tri_state_bridge_0_data[6], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L1002 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[6]~610
H1L1002 = AMPP_FUNCTION(EB1_q_a[6], J1_dbs_8_reg_segment_0[6], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[6] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[6]
J1_dbs_16_reg_segment_0[6] = DFFEAS(VB1L7, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L1003 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[6]~611
H1L1003 = AMPP_FUNCTION(DB1_q_a[6], J1_dbs_16_reg_segment_0[6], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[6]
X1_data_to_cpu[6] = DFFEAS(X1L153, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L1004 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[6]~612
H1L1004 = AMPP_FUNCTION(H1L1002, H1L1003, X1_data_to_cpu[6], G1_asmi_asmi_control_port_chipselect);


--H1L1005 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[6]~613
H1L1005 = AMPP_FUNCTION(H1_av_ld_byte1_data[6], H1L1001, H1L1004, H1L1103);


--J1_registered_cpu_0_data_master_readdata[5] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[5]
J1_registered_cpu_0_data_master_readdata[5] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[5], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L996 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[5]~614
H1L996 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[5], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[5] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[5]
J1_dbs_8_reg_segment_0[5] = DFFEAS(W1_incoming_tri_state_bridge_0_data[5], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L997 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[5]~615
H1L997 = AMPP_FUNCTION(EB1_q_a[5], J1_dbs_8_reg_segment_0[5], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[5] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[5]
J1_dbs_16_reg_segment_0[5] = DFFEAS(VB1L6, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L998 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[5]~616
H1L998 = AMPP_FUNCTION(DB1_q_a[5], J1_dbs_16_reg_segment_0[5], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[5]
X1_data_to_cpu[5] = DFFEAS(X1L150, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L999 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[5]~617
H1L999 = AMPP_FUNCTION(H1L997, H1L998, X1_data_to_cpu[5], G1_asmi_asmi_control_port_chipselect);


--H1L1000 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[5]~618
H1L1000 = AMPP_FUNCTION(H1_av_ld_byte1_data[5], H1L996, H1L999, H1L1103);


--J1_registered_cpu_0_data_master_readdata[4] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[4]
J1_registered_cpu_0_data_master_readdata[4] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[4], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L991 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[4]~619
H1L991 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[4], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1_W_alu_result[2], V1L1);


--J1_dbs_8_reg_segment_0[4] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[4]
J1_dbs_8_reg_segment_0[4] = DFFEAS(W1_incoming_tri_state_bridge_0_data[4], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--J1L113 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~340
J1L113 = J1_dbs_8_reg_segment_0[4] # !H1_d_read & !AB1_d_write # !H1_W_alu_result[22];


--H1L992 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[4]~620
H1L992 = AMPP_FUNCTION(J1L113, DB1_q_a[4], M1_cpu_0_data_master_requests_data_RAM_s1, H1L1103);


--J1_dbs_16_reg_segment_0[4] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[4]
J1_dbs_16_reg_segment_0[4] = DFFEAS(VB1L5, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L993 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[4]~621
H1L993 = AMPP_FUNCTION(EB1_q_a[4], J1_dbs_16_reg_segment_0[4], T1L11, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--X1_data_to_cpu[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[4]
X1_data_to_cpu[4] = DFFEAS(X1L146, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L994 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[4]~622
H1L994 = AMPP_FUNCTION(H1L992, H1L993, X1_data_to_cpu[4], G1_asmi_asmi_control_port_chipselect);


--H1L995 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[4]~623
H1L995 = AMPP_FUNCTION(H1_av_ld_byte1_data[4], H1L991, H1L994, H1L1103);


--J1_registered_cpu_0_data_master_readdata[3] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[3]
J1_registered_cpu_0_data_master_readdata[3] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[3], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L986 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[3]~624
H1L986 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[3], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[3] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[3]
J1_dbs_8_reg_segment_0[3] = DFFEAS(W1_incoming_tri_state_bridge_0_data[3], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L987 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[3]~625
H1L987 = AMPP_FUNCTION(EB1_q_a[3], J1_dbs_8_reg_segment_0[3], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[3] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[3]
J1_dbs_16_reg_segment_0[3] = DFFEAS(VB1L4, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L988 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[3]~626
H1L988 = AMPP_FUNCTION(DB1_q_a[3], J1_dbs_16_reg_segment_0[3], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[3]
X1_data_to_cpu[3] = DFFEAS(X1L143, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L989 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[3]~627
H1L989 = AMPP_FUNCTION(H1L987, H1L988, X1_data_to_cpu[3], G1_asmi_asmi_control_port_chipselect);


--H1L990 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[3]~628
H1L990 = AMPP_FUNCTION(H1_av_ld_byte1_data[3], H1L986, H1L989, H1L1103);


--J1_registered_cpu_0_data_master_readdata[2] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[2]
J1_registered_cpu_0_data_master_readdata[2] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[2], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L981 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[2]~629
H1L981 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[2], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[2] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[2]
J1_dbs_8_reg_segment_0[2] = DFFEAS(W1_incoming_tri_state_bridge_0_data[2], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L982 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[2]~630
H1L982 = AMPP_FUNCTION(EB1_q_a[2], J1_dbs_8_reg_segment_0[2], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[2] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[2]
J1_dbs_16_reg_segment_0[2] = DFFEAS(VB1L3, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L983 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[2]~631
H1L983 = AMPP_FUNCTION(DB1_q_a[2], J1_dbs_16_reg_segment_0[2], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[2]
X1_data_to_cpu[2] = DFFEAS(X1L140, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L984 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[2]~632
H1L984 = AMPP_FUNCTION(H1L982, H1L983, X1_data_to_cpu[2], G1_asmi_asmi_control_port_chipselect);


--H1L985 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[2]~633
H1L985 = AMPP_FUNCTION(H1_av_ld_byte1_data[2], H1L981, H1L984, H1L1103);


--H1L143 is DE2_Board:inst|cpu_0:the_cpu_0|E_control_rd_data[1]~126
H1L143 = AMPP_FUNCTION(H1_D_iw[7], H1_D_iw[6], H1_W_ienable_reg[1], H1_D_iw[8]);


--H1L139 is DE2_Board:inst|cpu_0:the_cpu_0|E_control_rd_data[0]~127
H1L139 = AMPP_FUNCTION(H1_D_iw[7], H1_D_iw[6]);


--H1L144 is DE2_Board:inst|cpu_0:the_cpu_0|E_control_rd_data[1]~128
H1L144 = AMPP_FUNCTION(H1L143, H1_D_iw[8], H1_W_ipending_reg[1], H1L139);


--H1L672 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[1]~133
H1L672 = AMPP_FUNCTION(H1L150, H1L130, H1_R_ctrl_dst_data_sel_logic_result);


--J1_registered_cpu_0_data_master_readdata[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[1]
J1_registered_cpu_0_data_master_readdata[1] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[1], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L976 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[1]~634
H1L976 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[1], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[1]
J1_dbs_8_reg_segment_0[1] = DFFEAS(W1_incoming_tri_state_bridge_0_data[1], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L977 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[1]~635
H1L977 = AMPP_FUNCTION(EB1_q_a[1], J1_dbs_8_reg_segment_0[1], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[1]
J1_dbs_16_reg_segment_0[1] = DFFEAS(VB1L2, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L978 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[1]~636
H1L978 = AMPP_FUNCTION(DB1_q_a[1], J1_dbs_16_reg_segment_0[1], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[1]
X1_data_to_cpu[1] = DFFEAS(X1L138, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L979 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[1]~637
H1L979 = AMPP_FUNCTION(H1L977, H1L978, X1_data_to_cpu[1], G1_asmi_asmi_control_port_chipselect);


--H1L980 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[1]~638
H1L980 = AMPP_FUNCTION(H1_av_ld_byte1_data[1], H1L976, H1L979, H1L1103);


--H1L140 is DE2_Board:inst|cpu_0:the_cpu_0|E_control_rd_data[0]~129
H1L140 = AMPP_FUNCTION(H1_D_iw[7], H1_W_estatus_reg, H1_D_iw[6], H1_W_status_reg_pie);


--H1L141 is DE2_Board:inst|cpu_0:the_cpu_0|E_control_rd_data[0]~130
H1L141 = AMPP_FUNCTION(H1_W_bstatus_reg, H1_D_iw[7], H1L140, H1_W_ienable_reg[0]);


--H1L142 is DE2_Board:inst|cpu_0:the_cpu_0|E_control_rd_data[0]~131
H1L142 = AMPP_FUNCTION(H1_W_ipending_reg[0], H1L139, H1L141, H1_D_iw[8]);


--H1L669 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[0]~132
H1L669 = AMPP_FUNCTION(H1L149, H1L184, H1_R_ctrl_dst_data_sel_logic_result);


--J1_registered_cpu_0_data_master_readdata[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[0]
J1_registered_cpu_0_data_master_readdata[0] = DFFEAS(J1_p1_registered_cpu_0_data_master_readdata[0], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L971 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[0]~639
H1L971 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[0], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1L1103, V1L1);


--J1_dbs_8_reg_segment_0[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_0[0]
J1_dbs_8_reg_segment_0[0] = DFFEAS(W1_incoming_tri_state_bridge_0_data[0], CLOCK_50, E1_data_out,  , J1L3,  ,  ,  ,  );


--H1L972 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[0]~640
H1L972 = AMPP_FUNCTION(EB1_q_a[0], J1_dbs_8_reg_segment_0[0], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1_dbs_16_reg_segment_0[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_16_reg_segment_0[0]
J1_dbs_16_reg_segment_0[0] = DFFEAS(VB1L1, CLOCK_50, E1_data_out,  , J1L2,  ,  ,  ,  );


--H1L973 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[0]~641
H1L973 = AMPP_FUNCTION(DB1_q_a[0], J1_dbs_16_reg_segment_0[0], T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--X1_data_to_cpu[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[0]
X1_data_to_cpu[0] = DFFEAS(X1L136, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L974 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[0]~642
H1L974 = AMPP_FUNCTION(H1L972, H1L973, X1_data_to_cpu[0], G1_asmi_asmi_control_port_chipselect);


--H1L975 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte0_data_nxt[0]~643
H1L975 = AMPP_FUNCTION(H1_av_ld_byte1_data[0], H1L971, H1L974, H1L1103);


--H1_W_alu_result[31] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[31]
H1_W_alu_result[31] = AMPP_FUNCTION(CLOCK_50, H1L126, E1_data_out);


--H1_av_ld_byte3_data[7] is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data[7]
H1_av_ld_byte3_data[7] = AMPP_FUNCTION(CLOCK_50, H1L1101, E1_data_out, H1L1103);


--H1_W_alu_result[30] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[30]
H1_W_alu_result[30] = AMPP_FUNCTION(CLOCK_50, H1L123, E1_data_out);


--H1_W_alu_result[29] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[29]
H1_W_alu_result[29] = AMPP_FUNCTION(CLOCK_50, H1L120, E1_data_out);


--H1_W_alu_result[28] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[28]
H1_W_alu_result[28] = AMPP_FUNCTION(CLOCK_50, H1L117, E1_data_out);


--H1_W_alu_result[27] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[27]
H1_W_alu_result[27] = AMPP_FUNCTION(CLOCK_50, H1L114, E1_data_out);


--H1_W_alu_result[26] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[26]
H1_W_alu_result[26] = AMPP_FUNCTION(CLOCK_50, H1L111, E1_data_out);


--H1_W_alu_result[25] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[25]
H1_W_alu_result[25] = AMPP_FUNCTION(CLOCK_50, H1L108, E1_data_out);


--H1_W_alu_result[24] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[24]
H1_W_alu_result[24] = AMPP_FUNCTION(CLOCK_50, H1L105, E1_data_out);


--H1_W_alu_result[23] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[23]
H1_W_alu_result[23] = AMPP_FUNCTION(CLOCK_50, H1L102, E1_data_out);


--H1_E_shift_rot_result[25] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[25]
H1_E_shift_rot_result[25] = AMPP_FUNCTION(CLOCK_50, H1L262, H1_E_src1[25], E1_data_out, H1_E_new_inst);


--H1L261 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[24]~467
H1L261 = AMPP_FUNCTION(H1_E_shift_rot_result[25], H1_E_shift_rot_result[23], H1_R_ctrl_shift_rot_right);


--H1L430 is DE2_Board:inst|cpu_0:the_cpu_0|E_wrctl_bstatus~18
H1L430 = AMPP_FUNCTION(H1_D_iw[7], H1_R_ctrl_wrctl_inst, H1_D_iw[8], H1_D_iw[6]);


--H1L749 is DE2_Board:inst|cpu_0:the_cpu_0|W_bstatus_reg_inst_nxt~259
H1L749 = AMPP_FUNCTION(H1_E_src1[0], H1_W_bstatus_reg, H1L430);


--H1L750 is DE2_Board:inst|cpu_0:the_cpu_0|W_bstatus_reg_inst_nxt~260
H1L750 = AMPP_FUNCTION(H1_W_status_reg_pie, H1L749, H1_R_ctrl_break);


--A1L74 is rtl~133
A1L74 = H1_D_iw[16] & H1_D_iw[14] & A1L93 & !H1_D_iw[11];


--H1L756 is DE2_Board:inst|cpu_0:the_cpu_0|W_estatus_reg_inst_nxt~259
H1L756 = AMPP_FUNCTION(H1_E_src1[0], H1_W_estatus_reg, H1_D_iw[6], H1L431);


--H1L757 is DE2_Board:inst|cpu_0:the_cpu_0|W_estatus_reg_inst_nxt~260
H1L757 = AMPP_FUNCTION(H1_W_status_reg_pie, H1L756, H1_R_ctrl_exception);


--H1L432 is DE2_Board:inst|cpu_0:the_cpu_0|E_wrctl_status~10
H1L432 = AMPP_FUNCTION(H1_R_ctrl_wrctl_inst, H1_D_iw[8]);


--H1L761 is DE2_Board:inst|cpu_0:the_cpu_0|W_ienable_reg_nxt~0
H1L761 = AMPP_FUNCTION(H1_E_valid, H1_D_iw[7], H1_D_iw[6], H1L432);


--X1_iE_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|iE_reg
X1_iE_reg = DFFEAS(H1_d_writedata[8], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1_ROE is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|ROE
X1_ROE = DFFEAS(X1L22, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1_iROE_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|iROE_reg
X1_iROE_reg = DFFEAS(H1_d_writedata[3], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1_TOE is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|TOE
X1_TOE = DFFEAS(X1L32, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L130 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|irq_reg~115
X1L130 = X1_iE_reg & (X1_ROE # X1_TOE) # !X1_iE_reg & X1_ROE & X1_iROE_reg;


--X1_iRRDY_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|iRRDY_reg
X1_iRRDY_reg = DFFEAS(H1_d_writedata[7], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1_iEOP_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|iEOP_reg
X1_iEOP_reg = DFFEAS(H1_d_writedata[9], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1_EOP is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP
X1_EOP = DFFEAS(X1L17, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1_RRDY is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|RRDY
X1_RRDY = DFFEAS(X1L24, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L131 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|irq_reg~116
X1L131 = X1_iRRDY_reg & (X1_RRDY # X1_iEOP_reg & X1_EOP) # !X1_iRRDY_reg & X1_iEOP_reg & X1_EOP;


--X1_iTRDY_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|iTRDY_reg
X1_iTRDY_reg = DFFEAS(H1_d_writedata[6], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1_tx_holding_primed is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_primed
X1_tx_holding_primed = DFFEAS(X1L220, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1_transmitting is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|transmitting
X1_transmitting = DFFEAS(X1L218, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L33 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|TRDY~0
X1L33 = !X1_transmitting # !X1_tx_holding_primed;


--X1_iTOE_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|iTOE_reg
X1_iTOE_reg = DFFEAS(H1_d_writedata[4], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1L132 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|irq_reg~117
X1L132 = X1_TOE & (X1_iTOE_reg # X1_iTRDY_reg & X1L33) # !X1_TOE & X1_iTRDY_reg & X1L33;


--X1L133 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|irq_reg~118
X1L133 = X1L130 # X1L131 # X1L132;


--Q1L73 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|ien_AE~15
Q1L73 = AB1_d_write & H1_W_alu_result[2] & A1L99 & !J1_cpu_0_data_master_waitrequest;


--QB2_safe_q[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[3]
QB2_safe_q[3] = DFFEAS(QB2_counter_comb_bita3, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--QB2_safe_q[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[2]
QB2_safe_q[2] = DFFEAS(QB2_counter_comb_bita2, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--QB2_safe_q[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[1]
QB2_safe_q[1] = DFFEAS(QB2_counter_comb_bita1, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--QB2_safe_q[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[0]
QB2_safe_q[0] = DFFEAS(QB2_counter_comb_bita0, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--Q1L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~618
Q1L12 = CARRY(!QB2_safe_q[0]);


--Q1L13 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~619
Q1L13 = QB2_safe_q[1] & (Q1L12 # GND) # !QB2_safe_q[1] & !Q1L12;

--Q1L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~620
Q1L14 = CARRY(QB2_safe_q[1] # !Q1L12);


--Q1L15 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~621
Q1L15 = QB2_safe_q[2] & !Q1L14 & VCC # !QB2_safe_q[2] & (Q1L14 $ GND);

--Q1L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~622
Q1L16 = CARRY(!QB2_safe_q[2] & !Q1L14);


--Q1L17 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~623
Q1L17 = QB2_safe_q[3] & (Q1L16 # GND) # !QB2_safe_q[3] & !Q1L16;

--Q1L18 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~624
Q1L18 = CARRY(QB2_safe_q[3] # !Q1L16);


--Q1L1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~477
Q1L1 = Q1L17 & (QB2_safe_q[0] # Q1L13 # Q1L15);


--QB2_safe_q[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[6]
QB2_safe_q[6] = DFFEAS(QB2_counter_comb_bita6, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--QB2_safe_q[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[5]
QB2_safe_q[5] = DFFEAS(QB2_counter_comb_bita5, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--QB2_safe_q[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[4]
QB2_safe_q[4] = DFFEAS(QB2_counter_comb_bita4, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--Q1L19 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~625
Q1L19 = QB2_safe_q[4] & !Q1L18 & VCC # !QB2_safe_q[4] & (Q1L18 $ GND);

--Q1L20 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~626
Q1L20 = CARRY(!QB2_safe_q[4] & !Q1L18);


--Q1L21 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~627
Q1L21 = QB2_safe_q[5] & (Q1L20 # GND) # !QB2_safe_q[5] & !Q1L20;

--Q1L22 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~628
Q1L22 = CARRY(QB2_safe_q[5] # !Q1L20);


--Q1L23 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~629
Q1L23 = QB2_safe_q[6] & !Q1L22 & VCC # !QB2_safe_q[6] & (Q1L22 $ GND);

--Q1L24 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~630
Q1L24 = CARRY(!QB2_safe_q[6] & !Q1L22);


--QB2_safe_q[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[8]
QB2_safe_q[8] = DFFEAS(QB2_counter_comb_bita8, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--QB2_safe_q[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[7]
QB2_safe_q[7] = DFFEAS(QB2_counter_comb_bita7, CLOCK_50,  ,  , MB2L1,  ,  ,  ,  );


--Q1L25 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~631
Q1L25 = QB2_safe_q[7] & (Q1L24 # GND) # !QB2_safe_q[7] & !Q1L24;

--Q1L26 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~632
Q1L26 = CARRY(QB2_safe_q[7] # !Q1L24);


--Q1L27 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~633
Q1L27 = QB2_safe_q[8] & !Q1L26 & VCC # !QB2_safe_q[8] & (Q1L26 $ GND);

--Q1L28 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~634
Q1L28 = CARRY(!QB2_safe_q[8] & !Q1L26);


--Q1L29 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~635
Q1L29 = MB2_b_full & !Q1L28 # !MB2_b_full & Q1L28 & VCC;

--Q1L30 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~636
Q1L30 = CARRY(MB2_b_full & !Q1L28);


--Q1L31 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~637
Q1L31 = !Q1L30;


--Q1L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~478
Q1L2 = Q1L19 # Q1L27 # Q1L29 # !Q1L31;


--Q1L3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~479
Q1L3 = Q1L21 # Q1L25;


--Q1L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~480
Q1L4 = !Q1L1 & !Q1L23 & !Q1L2 & !Q1L3;


--MB2_b_non_empty is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty
MB2_b_non_empty = DFFEAS(MB2L11, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--FB1L62Q is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~reg0
FB1L62Q = AMPP_FUNCTION(CLOCK_50, FB1L61, E1_data_out);


--Q1_read_0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|read_0
Q1_read_0 = DFFEAS(Q1L69, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--Q1L76 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|pause_irq~14
Q1L76 = MB2_b_non_empty & (FB1L62Q # Q1_pause_irq & !Q1_read_0) # !MB2_b_non_empty & (Q1_pause_irq & !Q1_read_0);


--QB1_safe_q[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[4]
QB1_safe_q[4] = DFFEAS(QB1_counter_comb_bita4, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--MB1_b_full is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full
MB1_b_full = DFFEAS(MB1L6, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--QB1_safe_q[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[3]
QB1_safe_q[3] = DFFEAS(QB1_counter_comb_bita3, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--QB1_safe_q[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[0]
QB1_safe_q[0] = DFFEAS(QB1_counter_comb_bita0, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--QB1_safe_q[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[2]
QB1_safe_q[2] = DFFEAS(QB1_counter_comb_bita2, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--QB1_safe_q[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[1]
QB1_safe_q[1] = DFFEAS(QB1_counter_comb_bita1, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--Q1L5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~481
Q1L5 = QB1_safe_q[3] & (QB1_safe_q[0] # QB1_safe_q[2] # QB1_safe_q[1]);


--QB1_safe_q[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[8]
QB1_safe_q[8] = DFFEAS(QB1_counter_comb_bita8, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--QB1_safe_q[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[7]
QB1_safe_q[7] = DFFEAS(QB1_counter_comb_bita7, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--QB1_safe_q[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[6]
QB1_safe_q[6] = DFFEAS(QB1_counter_comb_bita6, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--QB1_safe_q[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|safe_q[5]
QB1_safe_q[5] = DFFEAS(QB1_counter_comb_bita5, CLOCK_50,  ,  , MB1L1,  ,  ,  ,  );


--Q1L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~482
Q1L6 = !QB1_safe_q[8] & !QB1_safe_q[7] & !QB1_safe_q[6] & !QB1_safe_q[5];


--Q1L7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|LessThan~483
Q1L7 = !QB1_safe_q[4] & !MB1_b_full & !Q1L5 & Q1L6;


--H1_E_shift_rot_result[31] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[31]
H1_E_shift_rot_result[31] = AMPP_FUNCTION(CLOCK_50, H1L268, H1_E_src1[31], E1_data_out, H1_E_new_inst);


--H1_R_ctrl_rot_right is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_rot_right
H1_R_ctrl_rot_right = AMPP_FUNCTION(CLOCK_50, H1L40, E1_data_out);


--H1_R_ctrl_shift_logical is DE2_Board:inst|cpu_0:the_cpu_0|R_ctrl_shift_logical
H1_R_ctrl_shift_logical = AMPP_FUNCTION(CLOCK_50, H1L41, E1_data_out);


--H1L203 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_fill_bit~53
H1L203 = AMPP_FUNCTION(H1_E_shift_rot_result[0], H1_E_shift_rot_result[31], H1_R_ctrl_rot_right, H1_R_ctrl_shift_logical);


--H1L237 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[0]~468
H1L237 = AMPP_FUNCTION(H1_E_shift_rot_result[1], H1L203, H1_R_ctrl_shift_rot_right);


--ZB5L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0]~58
ZB5L3 = AMPP_FUNCTION(ZB3_Q[0], ZB5_Q[0], ZB6_Q[0], D1L18);


--EC1_w_anode28w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode28w[3]
EC1_w_anode28w[3] = AMPP_FUNCTION(ZB3_Q[2], D1L28, ZB3_Q[1], ZB3_Q[3]);


--DC1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5
DC1L18 = AMPP_FUNCTION(DC1_state[8], DC1_state[1], DC1_state[15], DC1_state[0]);


--EC1_dffe1a[7] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[7]
EC1_dffe1a[7] = AMPP_FUNCTION(A1L5, EC1_w_anode78w[3], D1_CLRN_SIGNAL, D1L6);


--D1L2 is sld_hub:sld_hub_inst|BROADCAST_ENA~29
D1L2 = AMPP_FUNCTION(DC1_state[8], D1_OK_TO_UPDATE_IR_Q);


--ZB1L3 is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~58
ZB1L3 = AMPP_FUNCTION(ZB1_Q[0], EC1_dffe1a[7], D1L2, ZB2_Q[0]);


--FB1L15 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~215
FB1L15 = AMPP_FUNCTION(DC1_state[4], FB1_count[9]);


--SB1_q_a[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[7]_PORT_A_data_in = VCC;
SB1_q_a[7]_PORT_A_data_in_reg = DFFE(SB1_q_a[7]_PORT_A_data_in, SB1_q_a[7]_clock_0, , , SB1_q_a[7]_clock_enable_0);
SB1_q_a[7]_PORT_B_data_in = H1_d_writedata[7];
SB1_q_a[7]_PORT_B_data_in_reg = DFFE(SB1_q_a[7]_PORT_B_data_in, SB1_q_a[7]_clock_1, , , );
SB1_q_a[7]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[7]_PORT_A_address_reg = DFFE(SB1_q_a[7]_PORT_A_address, SB1_q_a[7]_clock_0, , , SB1_q_a[7]_clock_enable_0);
SB1_q_a[7]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[7]_PORT_B_address_reg = DFFE(SB1_q_a[7]_PORT_B_address, SB1_q_a[7]_clock_1, , , );
SB1_q_a[7]_PORT_A_write_enable = GND;
SB1_q_a[7]_PORT_A_write_enable_reg = DFFE(SB1_q_a[7]_PORT_A_write_enable, SB1_q_a[7]_clock_0, , , SB1_q_a[7]_clock_enable_0);
SB1_q_a[7]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[7]_PORT_B_write_enable_reg = DFFE(SB1_q_a[7]_PORT_B_write_enable, SB1_q_a[7]_clock_1, , , );
SB1_q_a[7]_clock_0 = CLOCK_50;
SB1_q_a[7]_clock_1 = CLOCK_50;
SB1_q_a[7]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[7]_PORT_A_data_out = MEMORY(SB1_q_a[7]_PORT_A_data_in_reg, SB1_q_a[7]_PORT_B_data_in_reg, SB1_q_a[7]_PORT_A_address_reg, SB1_q_a[7]_PORT_B_address_reg, SB1_q_a[7]_PORT_A_write_enable_reg, SB1_q_a[7]_PORT_B_write_enable_reg, , , SB1_q_a[7]_clock_0, SB1_q_a[7]_clock_1, SB1_q_a[7]_clock_enable_0, , , );
SB1_q_a[7] = SB1_q_a[7]_PORT_A_data_out[0];


--Q1_r_val is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|r_val
Q1_r_val = DFFEAS(Q1_rd_wfifo, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--FB1_r_ena1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena1
FB1_r_ena1 = AMPP_FUNCTION(CLOCK_50, FB1L29, E1_data_out);


--FB1L28 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena~0
FB1L28 = AMPP_FUNCTION(Q1_r_val, FB1_r_ena1);


--MB2L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~107
MB2L4 = QB2_safe_q[8] & QB2_safe_q[7] & QB2_safe_q[6] & QB2_safe_q[5];


--MB2L5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~108
MB2L5 = QB2_safe_q[2] & QB2_safe_q[1] & QB2_safe_q[3] & QB2_safe_q[4];


--FB1L59Q is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~reg0
FB1L59Q = AMPP_FUNCTION(CLOCK_50, FB1L58, E1_data_out);


--MB2L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~109
MB2L6 = QB2_safe_q[0] & MB2_b_non_empty & MB2L5 & FB1L59Q;


--Q1L68 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|fifo_rd~33
Q1L68 = H1_d_read & !H1_W_alu_result[2];


--Q1L81 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|rvalid~18
Q1L81 = A1L99 & MB2_b_non_empty & Q1L68 & !J1_cpu_0_data_master_waitrequest;


--MB2L7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~110
MB2L7 = !Q1L81 & (MB2_b_full # MB2L4 & MB2L6);


--FB1_td_shift[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3]
FB1_td_shift[3] = AMPP_FUNCTION(A1L5, FB1L80, D1_CLRN_SIGNAL, FB1L44);


--FB1_rdata[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[0]
FB1_rdata[0] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[0], E1_data_out, FB1L28);


--FB1L78 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1393
FB1L78 = AMPP_FUNCTION(FB1L70, FB1_td_shift[3], FB1_rdata[0], FB1_count[9]);


--FB1L103 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled~59
FB1L103 = AMPP_FUNCTION(FB1_td_shift[10], FB1_write_stalled, Q1_t_dav, altera_internal_jtag);


--FB1L93 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0]~7
FB1L93 = AMPP_FUNCTION(FB1_count[1], FB1L89);


--FB1L29 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena~1
FB1L29 = AMPP_FUNCTION(FB1_rvalid0, Q1_r_val, FB1_r_ena1);


--FB1_read_write1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1
FB1_read_write1 = AMPP_FUNCTION(CLOCK_50, FB1_read_write, E1_data_out);


--FB1_read_write2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write2
FB1_read_write2 = AMPP_FUNCTION(CLOCK_50, FB1_read_write1, E1_data_out);


--FB1L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always2~2
FB1L2 = AMPP_FUNCTION(FB1_read_write1, FB1_read_write2);


--FB1_read_req is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_req
FB1_read_req = AMPP_FUNCTION(A1L5, FB1_td_shift[9], D1_CLRN_SIGNAL, FB1L93);


--FB1L54 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid0~73
FB1L54 = AMPP_FUNCTION(FB1L29, FB1_user_saw_rvalid, FB1L2, FB1_read_req);


--FB1_count[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[7]
FB1_count[7] = AMPP_FUNCTION(A1L5, FB1L17, D1_CLRN_SIGNAL, FB1L44);


--FB1L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~216
FB1L16 = AMPP_FUNCTION(DC1_state[4], FB1_count[7]);


--DC1_state[14] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14]
DC1_state[14] = AMPP_FUNCTION(A1L5, DC1L28);


--DC1L29 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~29
DC1L29 = AMPP_FUNCTION(DC1_state[12], DC1_state[14]);


--EC1_w_anode18w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode18w[3]
EC1_w_anode18w[3] = AMPP_FUNCTION(ZB3_Q[1], D1L28, ZB3_Q[3], ZB3_Q[2]);


--AC1_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]
AC1_WORD_SR[3] = AMPP_FUNCTION(A1L5, AC1L35, AC1L24);


--AC1_word_counter[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]
AC1_word_counter[3] = AMPP_FUNCTION(A1L5, AC1L15, AC1L6, AC1L7);


--AC1_word_counter[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]
AC1_word_counter[0] = AMPP_FUNCTION(A1L5, AC1L4, AC1L6, AC1L7);


--AC1L29 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~754
AC1L29 = AMPP_FUNCTION(AC1_word_counter[3], AC1_word_counter[0], AC1_word_counter[2]);


--AC1L30 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~755
AC1L30 = AMPP_FUNCTION(AC1_word_counter[2], AC1_word_counter[0], AC1_word_counter[3]);


--AC1_word_counter[4] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]
AC1_word_counter[4] = AMPP_FUNCTION(A1L5, AC1L18, AC1L6, AC1L7);


--AC1L31 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~756
AC1L31 = AMPP_FUNCTION(AC1_word_counter[1], AC1L29, AC1L30, AC1_word_counter[4]);


--AC1L32 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~757
AC1L32 = AMPP_FUNCTION(AC1_WORD_SR[3], AC1L31, DC1_state[4], AC1_clear_signal);


--AC1L4 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~231
AC1L4 = AMPP_FUNCTION(AC1_word_counter[0], GND);

--AC1L5 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~232
AC1L5 = AMPP_FUNCTION(AC1_word_counter[0]);


--AC1L9 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]~233
AC1L9 = AMPP_FUNCTION(AC1_word_counter[1], GND, AC1L5);

--AC1L10 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]~234
AC1L10 = AMPP_FUNCTION(AC1_word_counter[1], AC1L5);


--AC1L6 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~235
AC1L6 = AMPP_FUNCTION(AC1_word_counter[1], AC1_word_counter[4], AC1L30, AC1_clear_signal);


--AC1L7 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~236
AC1L7 = AMPP_FUNCTION(DC1_state[4], DC1_state[3], D1_jtag_debug_mode_usr0, AC1_clear_signal);


--AC1L12 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]~237
AC1L12 = AMPP_FUNCTION(AC1_word_counter[2], GND, AC1L10);

--AC1L13 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]~238
AC1L13 = AMPP_FUNCTION(AC1_word_counter[2], AC1L10);


--DC1L26 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~22
DC1L26 = AMPP_FUNCTION(DC1_state[11], DC1_state[10], DC1_state[14]);


--D1L33 is sld_hub:sld_hub_inst|process0~0
D1L33 = AMPP_FUNCTION(A1L7, DC1_state[2]);


--DC1L40 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~4
DC1L40 = AMPP_FUNCTION(DC1_tms_cnt[2], DC1_tms_cnt[0], DC1_tms_cnt[1]);


--DC1L38 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0
DC1L38 = AMPP_FUNCTION(A1L7, DC1_tms_cnt[0]);


--DC1L39 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~1
DC1L39 = AMPP_FUNCTION(DC1_tms_cnt[0], DC1_tms_cnt[1]);


--DC1L25 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~21
DC1L25 = AMPP_FUNCTION(DC1_state[9], A1L7);


--DC1L22 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~15
DC1L22 = AMPP_FUNCTION(DC1_state[5], DC1_state[6]);


--J1L39 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[12]~171
J1L39 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[28] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[12]);


--J1L42 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[15]~172
J1L42 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[31] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[15]);


--J1L41 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[14]~173
J1L41 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[30] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[14]);


--J1L40 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[13]~174
J1L40 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[29] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[13]);


--J1L38 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_write_16[11]~175
J1L38 = J1_cpu_0_data_master_dbs_address[1] & H1_d_writedata[27] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_writedata[11]);


--Q1L34 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~640
Q1L34 = CARRY(!QB1_safe_q[0]);


--Q1L35 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~641
Q1L35 = QB1_safe_q[1] & (Q1L34 # GND) # !QB1_safe_q[1] & !Q1L34;

--Q1L36 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~642
Q1L36 = CARRY(QB1_safe_q[1] # !Q1L34);


--Q1L37 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~643
Q1L37 = QB1_safe_q[2] & !Q1L36 & VCC # !QB1_safe_q[2] & (Q1L36 $ GND);

--Q1L38 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~644
Q1L38 = CARRY(!QB1_safe_q[2] & !Q1L36);


--Q1L39 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~645
Q1L39 = QB1_safe_q[3] & (Q1L38 # GND) # !QB1_safe_q[3] & !Q1L38;

--Q1L40 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~646
Q1L40 = CARRY(QB1_safe_q[3] # !Q1L38);


--Q1L41 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~647
Q1L41 = QB1_safe_q[4] & !Q1L40 & VCC # !QB1_safe_q[4] & (Q1L40 $ GND);

--Q1L42 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~648
Q1L42 = CARRY(!QB1_safe_q[4] & !Q1L40);


--Q1L43 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~649
Q1L43 = QB1_safe_q[5] & (Q1L42 # GND) # !QB1_safe_q[5] & !Q1L42;

--Q1L44 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~650
Q1L44 = CARRY(QB1_safe_q[5] # !Q1L42);


--Q1L45 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~651
Q1L45 = QB1_safe_q[6] & !Q1L44 & VCC # !QB1_safe_q[6] & (Q1L44 $ GND);

--Q1L46 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~652
Q1L46 = CARRY(!QB1_safe_q[6] & !Q1L44);


--Q1L47 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~653
Q1L47 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[6] # !Q1_read_0 & (Q1L45);


--J1L5 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18
J1L5 = J1_cpu_0_data_master_dbs_address[1] & !J1_cpu_0_data_master_dbs_address[0] & (J1L174 # J1L175);


--H1L36 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_ld_signed~16
H1L36 = AMPP_FUNCTION(H1_D_iw[0], H1_D_iw[1], H1_D_iw[2]);


--H1L1072 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~544
H1L1072 = AMPP_FUNCTION(H1_av_ld_aligning_data, H1L951);


--H1L1073 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~545
H1L1073 = AMPP_FUNCTION(J1_registered_cpu_0_data_master_readdata[31], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, H1_av_ld_aligning_data, G1_asmi_asmi_control_port_chipselect);


--H1L1074 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~546
H1L1074 = AMPP_FUNCTION(DB1_q_a[30], W1_incoming_tri_state_bridge_0_data[6], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1075 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~547
H1L1075 = AMPP_FUNCTION(J1L112, H1L1074, EB1_q_a[30], P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1L110 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~238
J1L110 = TB1_address_reg_a[0] & TB1_ram_block1a30 # !TB1_address_reg_a[0] & (TB1_ram_block1a14) # !T1L11;


--H1L1076 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~548
H1L1076 = AMPP_FUNCTION(H1L1072, H1L1073, H1L1075, J1L110);


--Q1L48 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~654
Q1L48 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[5] # !Q1_read_0 & (Q1L43);


--H1L1077 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~549
H1L1077 = AMPP_FUNCTION(H1L1073, V1L1);


--H1L1078 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~550
H1L1078 = AMPP_FUNCTION(DB1_q_a[29], W1_incoming_tri_state_bridge_0_data[5], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1079 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~551
H1L1079 = AMPP_FUNCTION(EB1_q_a[29], VB1L14, T1L11, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--H1L1080 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~552
H1L1080 = AMPP_FUNCTION(H1L1072, H1L1077, H1L1078, H1L1079);


--Q1L49 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~655
Q1L49 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[4] # !Q1_read_0 & (Q1L41);


--H1L1081 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~553
H1L1081 = AMPP_FUNCTION(DB1_q_a[28], W1_incoming_tri_state_bridge_0_data[4], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1082 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~554
H1L1082 = AMPP_FUNCTION(EB1_q_a[28], VB1L13, T1L11, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--H1L1083 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~555
H1L1083 = AMPP_FUNCTION(H1L1072, H1L1077, H1L1081, H1L1082);


--Q1L50 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~656
Q1L50 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[3] # !Q1_read_0 & (Q1L39);


--H1L1084 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~556
H1L1084 = AMPP_FUNCTION(H1L1073, H1_W_alu_result[2], V1L1);


--H1L1085 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~557
H1L1085 = AMPP_FUNCTION(EB1_q_a[27], W1_incoming_tri_state_bridge_0_data[3], W1_cpu_0_data_master_requests_cfi_flash_0_s1, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--H1L1086 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~558
H1L1086 = AMPP_FUNCTION(DB1_q_a[27], VB1L12, T1L11, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1087 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~559
H1L1087 = AMPP_FUNCTION(H1L1072, H1L1084, H1L1085, H1L1086);


--Q1L51 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~657
Q1L51 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[2] # !Q1_read_0 & (Q1L37);


--H1L1088 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~560
H1L1088 = AMPP_FUNCTION(DB1_q_a[26], W1_incoming_tri_state_bridge_0_data[2], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1089 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~561
H1L1089 = AMPP_FUNCTION(EB1_q_a[26], VB1L11, T1L11, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--H1L1090 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~562
H1L1090 = AMPP_FUNCTION(H1L1072, H1L1077, H1L1088, H1L1089);


--Q1L52 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~658
Q1L52 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[1] # !Q1_read_0 & (Q1L35);


--H1L1091 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~563
H1L1091 = AMPP_FUNCTION(DB1_q_a[25], W1_incoming_tri_state_bridge_0_data[1], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1092 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~564
H1L1092 = AMPP_FUNCTION(H1L1091, EB1_q_a[25], P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1L109 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~233
J1L109 = TB1_address_reg_a[0] & TB1_ram_block1a25 # !TB1_address_reg_a[0] & (TB1_ram_block1a9) # !T1L11;


--J1_registered_cpu_0_data_master_readdata[25] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[25]
J1_registered_cpu_0_data_master_readdata[25] = DFFEAS(Q1L60, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L1093 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~565
H1L1093 = AMPP_FUNCTION(H1L1092, J1L109, J1_registered_cpu_0_data_master_readdata[25], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1094 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~566
H1L1094 = AMPP_FUNCTION(H1L951, H1L1071, H1L1093, H1_av_ld_aligning_data);


--Q1L53 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~659
Q1L53 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[0] # !Q1_read_0 & (QB1_safe_q[0]);


--H1L1095 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~567
H1L1095 = AMPP_FUNCTION(DB1_q_a[24], W1_incoming_tri_state_bridge_0_data[0], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1096 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~568
H1L1096 = AMPP_FUNCTION(H1L1095, EB1_q_a[24], P1_cpu_0_data_master_requests_firmware_ROM_s1);


--J1L108 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata~232
J1L108 = TB1_address_reg_a[0] & TB1_ram_block1a24 # !TB1_address_reg_a[0] & (TB1_ram_block1a8) # !T1L11;


--J1_registered_cpu_0_data_master_readdata[24] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[24]
J1_registered_cpu_0_data_master_readdata[24] = DFFEAS(Q1L61, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1L1097 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~569
H1L1097 = AMPP_FUNCTION(H1L1096, J1L108, J1_registered_cpu_0_data_master_readdata[24], R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--H1L1098 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~570
H1L1098 = AMPP_FUNCTION(H1L951, H1L1071, H1L1097, H1_av_ld_aligning_data);


--X1L103 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[15]~318
X1L103 = H1_W_alu_result[4] & (H1_W_alu_result[3] $ H1_W_alu_result[2]);


--X1_endofpacketvalue_reg[15] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[15]
X1_endofpacketvalue_reg[15] = DFFEAS(H1_d_writedata[15], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[15] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[15]
X1_asmi_slave_select_reg[15] = DFFEAS(X1_asmi_slave_select_holding_reg[15], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--A1L75 is rtl~135
A1L75 = H1_W_alu_result[4] & H1_W_alu_result[3] & !H1_W_alu_result[2];


--X1L167 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[15]~2503
X1L167 = X1L103 & (A1L75 & X1_endofpacketvalue_reg[15] # !A1L75 & (X1_asmi_slave_select_reg[15]));


--J1L2 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always3~9
J1L2 = !J1_cpu_0_data_master_dbs_address[1] & (J1L174 # J1L175);


--J1L4 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always6~0
J1L4 = J1_cpu_0_data_master_dbs_address[0] & !J1_cpu_0_data_master_dbs_address[1] & (J1L174 # J1L175);


--Q1_rvalid is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|rvalid
Q1_rvalid = DFFEAS(Q1L82, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1_p1_registered_cpu_0_data_master_readdata[15] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[15]
J1_p1_registered_cpu_0_data_master_readdata[15] = Q1_rvalid # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;


--J1_dbs_8_reg_segment_2[7] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7]
J1_dbs_8_reg_segment_2[7] = DFFEAS(W1_incoming_tri_state_bridge_0_data[7], CLOCK_50, E1_data_out,  , J1L5,  ,  ,  ,  );


--J1L99 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~3312
J1L99 = DB1_q_a[23] & (J1_dbs_8_reg_segment_2[7] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1) # !DB1_q_a[23] & !M1_cpu_0_data_master_requests_data_RAM_s1 & (J1_dbs_8_reg_segment_2[7] # !W1_cpu_0_data_master_requests_cfi_flash_0_s1);


--J1L100 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~3313
J1L100 = EB1_q_a[23] & (VB1L8 # !T1L11) # !EB1_q_a[23] & !P1_cpu_0_data_master_requests_firmware_ROM_s1 & (VB1L8 # !T1L11);


--J1_registered_cpu_0_data_master_readdata[23] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|registered_cpu_0_data_master_readdata[23]
J1_registered_cpu_0_data_master_readdata[23] = DFFEAS(Q1L62, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1L101 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~3314
J1L101 = J1L100 & (J1_registered_cpu_0_data_master_readdata[23] # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave);


--J1L102 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[23]~3315
J1L102 = J1L99 & J1L101 & !G1_asmi_asmi_control_port_chipselect & !V1L1;


--H1L1060 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte2_data[7]~23
H1L1060 = AMPP_FUNCTION(J1L102, H1L951, H1_av_ld_aligning_data);


--X1_endofpacketvalue_reg[14] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[14]
X1_endofpacketvalue_reg[14] = DFFEAS(H1_d_writedata[14], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[14] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[14]
X1_asmi_slave_select_reg[14] = DFFEAS(X1_asmi_slave_select_holding_reg[14], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L166 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[14]~2504
X1L166 = X1L103 & (A1L75 & X1_endofpacketvalue_reg[14] # !A1L75 & (X1_asmi_slave_select_reg[14]));


--Q1_woverflow is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|woverflow
Q1_woverflow = DFFEAS(Q1L85, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1_p1_registered_cpu_0_data_master_readdata[14] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[14]
J1_p1_registered_cpu_0_data_master_readdata[14] = Q1_woverflow # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;


--X1_endofpacketvalue_reg[13] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[13]
X1_endofpacketvalue_reg[13] = DFFEAS(H1_d_writedata[13], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[13] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[13]
X1_asmi_slave_select_reg[13] = DFFEAS(X1_asmi_slave_select_holding_reg[13], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L165 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[13]~2505
X1L165 = X1L103 & (A1L75 & X1_endofpacketvalue_reg[13] # !A1L75 & (X1_asmi_slave_select_reg[13]));


--J1_p1_registered_cpu_0_data_master_readdata[13] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[13]
J1_p1_registered_cpu_0_data_master_readdata[13] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # !MB1_b_full;


--X1_endofpacketvalue_reg[12] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[12]
X1_endofpacketvalue_reg[12] = DFFEAS(H1_d_writedata[12], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[12] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[12]
X1_asmi_slave_select_reg[12] = DFFEAS(X1_asmi_slave_select_holding_reg[12], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L164 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[12]~2506
X1L164 = X1L103 & (A1L75 & X1_endofpacketvalue_reg[12] # !A1L75 & (X1_asmi_slave_select_reg[12]));


--J1_p1_registered_cpu_0_data_master_readdata[12] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[12]
J1_p1_registered_cpu_0_data_master_readdata[12] = MB2_b_non_empty # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;


--X1_endofpacketvalue_reg[11] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[11]
X1_endofpacketvalue_reg[11] = DFFEAS(H1_d_writedata[11], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[11] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[11]
X1_asmi_slave_select_reg[11] = DFFEAS(X1_asmi_slave_select_holding_reg[11], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L163 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[11]~2507
X1L163 = X1L103 & (A1L75 & X1_endofpacketvalue_reg[11] # !A1L75 & (X1_asmi_slave_select_reg[11]));


--X1_SSO_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|SSO_reg
X1_SSO_reg = DFFEAS(H1_d_writedata[10], CLOCK_50, E1_data_out,  , X1_control_wr_strobe,  ,  ,  ,  );


--X1_endofpacketvalue_reg[10] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[10]
X1_endofpacketvalue_reg[10] = DFFEAS(H1_d_writedata[10], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[10] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[10]
X1_asmi_slave_select_reg[10] = DFFEAS(X1_asmi_slave_select_holding_reg[10], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--A1L110 is rtl~2853
A1L110 = H1_W_alu_result[4] & H1_W_alu_result[2] & !H1_W_alu_result[3];


--X1L168 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu~2508
X1L168 = A1L75 & X1_endofpacketvalue_reg[10] # !A1L75 & (X1_asmi_slave_select_reg[10] & A1L110);


--X1L85 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[0]~319
X1L85 = H1_W_alu_result[3] & !H1_W_alu_result[4];


--X1L169 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu~2509
X1L169 = H1_W_alu_result[2] & (X1L85 & X1_SSO_reg # !X1L85 & (X1L168)) # !H1_W_alu_result[2] & (X1L168);


--Q1_ac is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|ac
Q1_ac = DFFEAS(Q1L10, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--J1_p1_registered_cpu_0_data_master_readdata[10] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[10]
J1_p1_registered_cpu_0_data_master_readdata[10] = Q1_ac # R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;


--X1_endofpacketvalue_reg[9] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[9]
X1_endofpacketvalue_reg[9] = DFFEAS(H1_d_writedata[9], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--A1L111 is rtl~2854
A1L111 = H1_W_alu_result[3] & !H1_W_alu_result[2];


--X1_asmi_slave_select_reg[9] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[9]
X1_asmi_slave_select_reg[9] = DFFEAS(X1_asmi_slave_select_holding_reg[9], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L160 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[9]~2510
X1L160 = A1L111 & (X1L85) # !A1L111 & (X1L85 & X1_iEOP_reg # !X1L85 & (X1_asmi_slave_select_reg[9]));


--X1L161 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[9]~2511
X1L161 = A1L111 & (X1L160 & (X1_EOP) # !X1L160 & X1_endofpacketvalue_reg[9]) # !A1L111 & (X1L160);


--X1L162 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[9]~2512
X1L162 = X1L161 & (H1_W_alu_result[3] $ (H1_W_alu_result[4] & H1_W_alu_result[2]));


--J1_p1_registered_cpu_0_data_master_readdata[9] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[9]
J1_p1_registered_cpu_0_data_master_readdata[9] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_fifo_AE & Q1_ien_AE;


--X1_endofpacketvalue_reg[8] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[8]
X1_endofpacketvalue_reg[8] = DFFEAS(H1_d_writedata[8], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[8] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[8]
X1_asmi_slave_select_reg[8] = DFFEAS(X1_asmi_slave_select_holding_reg[8], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L157 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[8]~2513
X1L157 = A1L111 & (X1L85) # !A1L111 & (X1L85 & X1_iE_reg # !X1L85 & (X1_asmi_slave_select_reg[8]));


--X1_E is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|E
X1_E = X1_ROE # X1_TOE;


--X1L158 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[8]~2514
X1L158 = A1L111 & (X1L157 & (X1_E) # !X1L157 & X1_endofpacketvalue_reg[8]) # !A1L111 & (X1L157);


--X1L159 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[8]~2515
X1L159 = X1L158 & (H1_W_alu_result[3] $ (H1_W_alu_result[4] & H1_W_alu_result[2]));


--SB2_q_a[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[7]_PORT_A_data_in = VCC;
SB2_q_a[7]_PORT_A_data_in_reg = DFFE(SB2_q_a[7]_PORT_A_data_in, SB2_q_a[7]_clock_0, , , SB2_q_a[7]_clock_enable_0);
SB2_q_a[7]_PORT_B_data_in = FB1_wdata[7];
SB2_q_a[7]_PORT_B_data_in_reg = DFFE(SB2_q_a[7]_PORT_B_data_in, SB2_q_a[7]_clock_1, , , );
SB2_q_a[7]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[7]_PORT_A_address_reg = DFFE(SB2_q_a[7]_PORT_A_address, SB2_q_a[7]_clock_0, , , SB2_q_a[7]_clock_enable_0);
SB2_q_a[7]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[7]_PORT_B_address_reg = DFFE(SB2_q_a[7]_PORT_B_address, SB2_q_a[7]_clock_1, , , );
SB2_q_a[7]_PORT_A_write_enable = GND;
SB2_q_a[7]_PORT_A_write_enable_reg = DFFE(SB2_q_a[7]_PORT_A_write_enable, SB2_q_a[7]_clock_0, , , SB2_q_a[7]_clock_enable_0);
SB2_q_a[7]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[7]_PORT_B_write_enable_reg = DFFE(SB2_q_a[7]_PORT_B_write_enable, SB2_q_a[7]_clock_1, , , );
SB2_q_a[7]_clock_0 = CLOCK_50;
SB2_q_a[7]_clock_1 = CLOCK_50;
SB2_q_a[7]_clock_enable_0 = Q1L81;
SB2_q_a[7]_PORT_A_data_out = MEMORY(SB2_q_a[7]_PORT_A_data_in_reg, SB2_q_a[7]_PORT_B_data_in_reg, SB2_q_a[7]_PORT_A_address_reg, SB2_q_a[7]_PORT_B_address_reg, SB2_q_a[7]_PORT_A_write_enable_reg, SB2_q_a[7]_PORT_B_write_enable_reg, , , SB2_q_a[7]_clock_0, SB2_q_a[7]_clock_1, SB2_q_a[7]_clock_enable_0, , , );
SB2_q_a[7] = SB2_q_a[7]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[7] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[7]
J1_p1_registered_cpu_0_data_master_readdata[7] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # SB2_q_a[7] & Q1_read_0;


--J1L3 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always5~9
J1L3 = !J1_cpu_0_data_master_dbs_address[0] & !J1_cpu_0_data_master_dbs_address[1] & (J1L174 # J1L175);


--X1_endofpacketvalue_reg[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[7]
X1_endofpacketvalue_reg[7] = DFFEAS(H1_d_writedata[7], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1L89 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[3]~320
X1L89 = H1_W_alu_result[3] & (H1_W_alu_result[4] $ H1_W_alu_result[2]);


--X1_asmi_slave_select_reg[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[7]
X1_asmi_slave_select_reg[7] = DFFEAS(X1_asmi_slave_select_holding_reg[7], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L90 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_to_cpu[3]~321
X1L90 = H1_W_alu_result[2] & (H1_W_alu_result[4] $ H1_W_alu_result[3]);


--X1_rx_holding_reg[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[7]
X1_rx_holding_reg[7] = DFFEAS(X1_shift_reg[7], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L154 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[7]~2516
X1L154 = X1L89 & (X1L90) # !X1L89 & (X1L90 & X1_asmi_slave_select_reg[7] # !X1L90 & (X1_rx_holding_reg[7]));


--X1L155 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[7]~2517
X1L155 = X1L89 & (X1L154 & (X1_iRRDY_reg) # !X1L154 & X1_endofpacketvalue_reg[7]) # !X1L89 & (X1L154);


--X1L156 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[7]~2518
X1L156 = X1L85 & (H1_W_alu_result[2] & X1L155 # !H1_W_alu_result[2] & (X1_RRDY)) # !X1L85 & X1L155;


--SB2_q_a[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[6]_PORT_A_data_in = VCC;
SB2_q_a[6]_PORT_A_data_in_reg = DFFE(SB2_q_a[6]_PORT_A_data_in, SB2_q_a[6]_clock_0, , , SB2_q_a[6]_clock_enable_0);
SB2_q_a[6]_PORT_B_data_in = FB1_wdata[6];
SB2_q_a[6]_PORT_B_data_in_reg = DFFE(SB2_q_a[6]_PORT_B_data_in, SB2_q_a[6]_clock_1, , , );
SB2_q_a[6]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[6]_PORT_A_address_reg = DFFE(SB2_q_a[6]_PORT_A_address, SB2_q_a[6]_clock_0, , , SB2_q_a[6]_clock_enable_0);
SB2_q_a[6]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[6]_PORT_B_address_reg = DFFE(SB2_q_a[6]_PORT_B_address, SB2_q_a[6]_clock_1, , , );
SB2_q_a[6]_PORT_A_write_enable = GND;
SB2_q_a[6]_PORT_A_write_enable_reg = DFFE(SB2_q_a[6]_PORT_A_write_enable, SB2_q_a[6]_clock_0, , , SB2_q_a[6]_clock_enable_0);
SB2_q_a[6]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[6]_PORT_B_write_enable_reg = DFFE(SB2_q_a[6]_PORT_B_write_enable, SB2_q_a[6]_clock_1, , , );
SB2_q_a[6]_clock_0 = CLOCK_50;
SB2_q_a[6]_clock_1 = CLOCK_50;
SB2_q_a[6]_clock_enable_0 = Q1L81;
SB2_q_a[6]_PORT_A_data_out = MEMORY(SB2_q_a[6]_PORT_A_data_in_reg, SB2_q_a[6]_PORT_B_data_in_reg, SB2_q_a[6]_PORT_A_address_reg, SB2_q_a[6]_PORT_B_address_reg, SB2_q_a[6]_PORT_A_write_enable_reg, SB2_q_a[6]_PORT_B_write_enable_reg, , , SB2_q_a[6]_clock_0, SB2_q_a[6]_clock_1, SB2_q_a[6]_clock_enable_0, , , );
SB2_q_a[6] = SB2_q_a[6]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[6] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[6]
J1_p1_registered_cpu_0_data_master_readdata[6] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # SB2_q_a[6] & Q1_read_0;


--X1_asmi_slave_select_reg[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[6]
X1_asmi_slave_select_reg[6] = DFFEAS(X1_asmi_slave_select_holding_reg[6], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1_endofpacketvalue_reg[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[6]
X1_endofpacketvalue_reg[6] = DFFEAS(H1_d_writedata[6], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_rx_holding_reg[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[6]
X1_rx_holding_reg[6] = DFFEAS(X1_shift_reg[6], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L151 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[6]~2519
X1L151 = X1L90 & (X1L89) # !X1L90 & (X1L89 & X1_endofpacketvalue_reg[6] # !X1L89 & (X1_rx_holding_reg[6]));


--X1L152 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[6]~2520
X1L152 = X1L90 & (X1L151 & (X1_iTRDY_reg) # !X1L151 & X1_asmi_slave_select_reg[6]) # !X1L90 & (X1L151);


--X1L153 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[6]~2521
X1L153 = X1L85 & (H1_W_alu_result[2] & X1L152 # !H1_W_alu_result[2] & (X1L33)) # !X1L85 & X1L152;


--SB2_q_a[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[5]_PORT_A_data_in = VCC;
SB2_q_a[5]_PORT_A_data_in_reg = DFFE(SB2_q_a[5]_PORT_A_data_in, SB2_q_a[5]_clock_0, , , SB2_q_a[5]_clock_enable_0);
SB2_q_a[5]_PORT_B_data_in = FB1_wdata[5];
SB2_q_a[5]_PORT_B_data_in_reg = DFFE(SB2_q_a[5]_PORT_B_data_in, SB2_q_a[5]_clock_1, , , );
SB2_q_a[5]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[5]_PORT_A_address_reg = DFFE(SB2_q_a[5]_PORT_A_address, SB2_q_a[5]_clock_0, , , SB2_q_a[5]_clock_enable_0);
SB2_q_a[5]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[5]_PORT_B_address_reg = DFFE(SB2_q_a[5]_PORT_B_address, SB2_q_a[5]_clock_1, , , );
SB2_q_a[5]_PORT_A_write_enable = GND;
SB2_q_a[5]_PORT_A_write_enable_reg = DFFE(SB2_q_a[5]_PORT_A_write_enable, SB2_q_a[5]_clock_0, , , SB2_q_a[5]_clock_enable_0);
SB2_q_a[5]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[5]_PORT_B_write_enable_reg = DFFE(SB2_q_a[5]_PORT_B_write_enable, SB2_q_a[5]_clock_1, , , );
SB2_q_a[5]_clock_0 = CLOCK_50;
SB2_q_a[5]_clock_1 = CLOCK_50;
SB2_q_a[5]_clock_enable_0 = Q1L81;
SB2_q_a[5]_PORT_A_data_out = MEMORY(SB2_q_a[5]_PORT_A_data_in_reg, SB2_q_a[5]_PORT_B_data_in_reg, SB2_q_a[5]_PORT_A_address_reg, SB2_q_a[5]_PORT_B_address_reg, SB2_q_a[5]_PORT_A_write_enable_reg, SB2_q_a[5]_PORT_B_write_enable_reg, , , SB2_q_a[5]_clock_0, SB2_q_a[5]_clock_1, SB2_q_a[5]_clock_enable_0, , , );
SB2_q_a[5] = SB2_q_a[5]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[5] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[5]
J1_p1_registered_cpu_0_data_master_readdata[5] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # SB2_q_a[5] & Q1_read_0;


--X1_endofpacketvalue_reg[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[5]
X1_endofpacketvalue_reg[5] = DFFEAS(H1_d_writedata[5], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[5]
X1_asmi_slave_select_reg[5] = DFFEAS(X1_asmi_slave_select_holding_reg[5], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1_rx_holding_reg[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[5]
X1_rx_holding_reg[5] = DFFEAS(X1_shift_reg[5], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L147 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[5]~2522
X1L147 = A1L110 & X1_asmi_slave_select_reg[5] # !A1L110 & (X1_rx_holding_reg[5]);


--X1L148 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[5]~2523
X1L148 = A1L75 & X1_endofpacketvalue_reg[5] # !A1L75 & (X1L147);


--X1L149 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[5]~2524
X1L149 = !X1_tx_holding_primed & !X1_transmitting;


--X1L150 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[5]~2525
X1L150 = X1L85 & (X1L149 & !H1_W_alu_result[2]) # !X1L85 & X1L148;


--SB2_q_a[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[4]_PORT_A_data_in = VCC;
SB2_q_a[4]_PORT_A_data_in_reg = DFFE(SB2_q_a[4]_PORT_A_data_in, SB2_q_a[4]_clock_0, , , SB2_q_a[4]_clock_enable_0);
SB2_q_a[4]_PORT_B_data_in = FB1_wdata[4];
SB2_q_a[4]_PORT_B_data_in_reg = DFFE(SB2_q_a[4]_PORT_B_data_in, SB2_q_a[4]_clock_1, , , );
SB2_q_a[4]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[4]_PORT_A_address_reg = DFFE(SB2_q_a[4]_PORT_A_address, SB2_q_a[4]_clock_0, , , SB2_q_a[4]_clock_enable_0);
SB2_q_a[4]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[4]_PORT_B_address_reg = DFFE(SB2_q_a[4]_PORT_B_address, SB2_q_a[4]_clock_1, , , );
SB2_q_a[4]_PORT_A_write_enable = GND;
SB2_q_a[4]_PORT_A_write_enable_reg = DFFE(SB2_q_a[4]_PORT_A_write_enable, SB2_q_a[4]_clock_0, , , SB2_q_a[4]_clock_enable_0);
SB2_q_a[4]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[4]_PORT_B_write_enable_reg = DFFE(SB2_q_a[4]_PORT_B_write_enable, SB2_q_a[4]_clock_1, , , );
SB2_q_a[4]_clock_0 = CLOCK_50;
SB2_q_a[4]_clock_1 = CLOCK_50;
SB2_q_a[4]_clock_enable_0 = Q1L81;
SB2_q_a[4]_PORT_A_data_out = MEMORY(SB2_q_a[4]_PORT_A_data_in_reg, SB2_q_a[4]_PORT_B_data_in_reg, SB2_q_a[4]_PORT_A_address_reg, SB2_q_a[4]_PORT_B_address_reg, SB2_q_a[4]_PORT_A_write_enable_reg, SB2_q_a[4]_PORT_B_write_enable_reg, , , SB2_q_a[4]_clock_0, SB2_q_a[4]_clock_1, SB2_q_a[4]_clock_enable_0, , , );
SB2_q_a[4] = SB2_q_a[4]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[4] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[4]
J1_p1_registered_cpu_0_data_master_readdata[4] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # SB2_q_a[4] & Q1_read_0;


--X1_endofpacketvalue_reg[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[4]
X1_endofpacketvalue_reg[4] = DFFEAS(H1_d_writedata[4], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[4]
X1_asmi_slave_select_reg[4] = DFFEAS(X1_asmi_slave_select_holding_reg[4], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1_rx_holding_reg[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[4]
X1_rx_holding_reg[4] = DFFEAS(X1_shift_reg[4], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L144 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[4]~2526
X1L144 = X1L89 & (X1L90) # !X1L89 & (X1L90 & X1_asmi_slave_select_reg[4] # !X1L90 & (X1_rx_holding_reg[4]));


--X1L145 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[4]~2527
X1L145 = X1L89 & (X1L144 & (X1_iTOE_reg) # !X1L144 & X1_endofpacketvalue_reg[4]) # !X1L89 & (X1L144);


--X1L146 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[4]~2528
X1L146 = X1L85 & (H1_W_alu_result[2] & X1L145 # !H1_W_alu_result[2] & (X1_TOE)) # !X1L85 & X1L145;


--SB2_q_a[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[3]_PORT_A_data_in = VCC;
SB2_q_a[3]_PORT_A_data_in_reg = DFFE(SB2_q_a[3]_PORT_A_data_in, SB2_q_a[3]_clock_0, , , SB2_q_a[3]_clock_enable_0);
SB2_q_a[3]_PORT_B_data_in = FB1_wdata[3];
SB2_q_a[3]_PORT_B_data_in_reg = DFFE(SB2_q_a[3]_PORT_B_data_in, SB2_q_a[3]_clock_1, , , );
SB2_q_a[3]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[3]_PORT_A_address_reg = DFFE(SB2_q_a[3]_PORT_A_address, SB2_q_a[3]_clock_0, , , SB2_q_a[3]_clock_enable_0);
SB2_q_a[3]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[3]_PORT_B_address_reg = DFFE(SB2_q_a[3]_PORT_B_address, SB2_q_a[3]_clock_1, , , );
SB2_q_a[3]_PORT_A_write_enable = GND;
SB2_q_a[3]_PORT_A_write_enable_reg = DFFE(SB2_q_a[3]_PORT_A_write_enable, SB2_q_a[3]_clock_0, , , SB2_q_a[3]_clock_enable_0);
SB2_q_a[3]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[3]_PORT_B_write_enable_reg = DFFE(SB2_q_a[3]_PORT_B_write_enable, SB2_q_a[3]_clock_1, , , );
SB2_q_a[3]_clock_0 = CLOCK_50;
SB2_q_a[3]_clock_1 = CLOCK_50;
SB2_q_a[3]_clock_enable_0 = Q1L81;
SB2_q_a[3]_PORT_A_data_out = MEMORY(SB2_q_a[3]_PORT_A_data_in_reg, SB2_q_a[3]_PORT_B_data_in_reg, SB2_q_a[3]_PORT_A_address_reg, SB2_q_a[3]_PORT_B_address_reg, SB2_q_a[3]_PORT_A_write_enable_reg, SB2_q_a[3]_PORT_B_write_enable_reg, , , SB2_q_a[3]_clock_0, SB2_q_a[3]_clock_1, SB2_q_a[3]_clock_enable_0, , , );
SB2_q_a[3] = SB2_q_a[3]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[3] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[3]
J1_p1_registered_cpu_0_data_master_readdata[3] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # SB2_q_a[3] & Q1_read_0;


--X1_asmi_slave_select_reg[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[3]
X1_asmi_slave_select_reg[3] = DFFEAS(X1_asmi_slave_select_holding_reg[3], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1_endofpacketvalue_reg[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[3]
X1_endofpacketvalue_reg[3] = DFFEAS(H1_d_writedata[3], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_rx_holding_reg[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[3]
X1_rx_holding_reg[3] = DFFEAS(X1_shift_reg[3], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L141 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[3]~2529
X1L141 = X1L90 & (X1L89) # !X1L90 & (X1L89 & X1_endofpacketvalue_reg[3] # !X1L89 & (X1_rx_holding_reg[3]));


--X1L142 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[3]~2530
X1L142 = X1L90 & (X1L141 & (X1_iROE_reg) # !X1L141 & X1_asmi_slave_select_reg[3]) # !X1L90 & (X1L141);


--X1L143 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[3]~2531
X1L143 = X1L85 & (H1_W_alu_result[2] & X1L142 # !H1_W_alu_result[2] & (X1_ROE)) # !X1L85 & X1L142;


--SB2_q_a[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[2]_PORT_A_data_in = VCC;
SB2_q_a[2]_PORT_A_data_in_reg = DFFE(SB2_q_a[2]_PORT_A_data_in, SB2_q_a[2]_clock_0, , , SB2_q_a[2]_clock_enable_0);
SB2_q_a[2]_PORT_B_data_in = FB1_wdata[2];
SB2_q_a[2]_PORT_B_data_in_reg = DFFE(SB2_q_a[2]_PORT_B_data_in, SB2_q_a[2]_clock_1, , , );
SB2_q_a[2]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[2]_PORT_A_address_reg = DFFE(SB2_q_a[2]_PORT_A_address, SB2_q_a[2]_clock_0, , , SB2_q_a[2]_clock_enable_0);
SB2_q_a[2]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[2]_PORT_B_address_reg = DFFE(SB2_q_a[2]_PORT_B_address, SB2_q_a[2]_clock_1, , , );
SB2_q_a[2]_PORT_A_write_enable = GND;
SB2_q_a[2]_PORT_A_write_enable_reg = DFFE(SB2_q_a[2]_PORT_A_write_enable, SB2_q_a[2]_clock_0, , , SB2_q_a[2]_clock_enable_0);
SB2_q_a[2]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[2]_PORT_B_write_enable_reg = DFFE(SB2_q_a[2]_PORT_B_write_enable, SB2_q_a[2]_clock_1, , , );
SB2_q_a[2]_clock_0 = CLOCK_50;
SB2_q_a[2]_clock_1 = CLOCK_50;
SB2_q_a[2]_clock_enable_0 = Q1L81;
SB2_q_a[2]_PORT_A_data_out = MEMORY(SB2_q_a[2]_PORT_A_data_in_reg, SB2_q_a[2]_PORT_B_data_in_reg, SB2_q_a[2]_PORT_A_address_reg, SB2_q_a[2]_PORT_B_address_reg, SB2_q_a[2]_PORT_A_write_enable_reg, SB2_q_a[2]_PORT_B_write_enable_reg, , , SB2_q_a[2]_clock_0, SB2_q_a[2]_clock_1, SB2_q_a[2]_clock_enable_0, , , );
SB2_q_a[2] = SB2_q_a[2]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[2] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[2]
J1_p1_registered_cpu_0_data_master_readdata[2] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # SB2_q_a[2] & Q1_read_0;


--X1_endofpacketvalue_reg[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[2]
X1_endofpacketvalue_reg[2] = DFFEAS(H1_d_writedata[2], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[2]
X1_asmi_slave_select_reg[2] = DFFEAS(X1_asmi_slave_select_holding_reg[2], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1_rx_holding_reg[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[2]
X1_rx_holding_reg[2] = DFFEAS(X1_shift_reg[2], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L139 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[2]~2532
X1L139 = A1L110 & X1_asmi_slave_select_reg[2] # !A1L110 & (X1_rx_holding_reg[2]);


--X1L140 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[2]~2533
X1L140 = !X1L85 & (A1L75 & X1_endofpacketvalue_reg[2] # !A1L75 & (X1L139));


--SB2_q_a[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[1]_PORT_A_data_in = VCC;
SB2_q_a[1]_PORT_A_data_in_reg = DFFE(SB2_q_a[1]_PORT_A_data_in, SB2_q_a[1]_clock_0, , , SB2_q_a[1]_clock_enable_0);
SB2_q_a[1]_PORT_B_data_in = FB1_wdata[1];
SB2_q_a[1]_PORT_B_data_in_reg = DFFE(SB2_q_a[1]_PORT_B_data_in, SB2_q_a[1]_clock_1, , , );
SB2_q_a[1]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[1]_PORT_A_address_reg = DFFE(SB2_q_a[1]_PORT_A_address, SB2_q_a[1]_clock_0, , , SB2_q_a[1]_clock_enable_0);
SB2_q_a[1]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[1]_PORT_B_address_reg = DFFE(SB2_q_a[1]_PORT_B_address, SB2_q_a[1]_clock_1, , , );
SB2_q_a[1]_PORT_A_write_enable = GND;
SB2_q_a[1]_PORT_A_write_enable_reg = DFFE(SB2_q_a[1]_PORT_A_write_enable, SB2_q_a[1]_clock_0, , , SB2_q_a[1]_clock_enable_0);
SB2_q_a[1]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[1]_PORT_B_write_enable_reg = DFFE(SB2_q_a[1]_PORT_B_write_enable, SB2_q_a[1]_clock_1, , , );
SB2_q_a[1]_clock_0 = CLOCK_50;
SB2_q_a[1]_clock_1 = CLOCK_50;
SB2_q_a[1]_clock_enable_0 = Q1L81;
SB2_q_a[1]_PORT_A_data_out = MEMORY(SB2_q_a[1]_PORT_A_data_in_reg, SB2_q_a[1]_PORT_B_data_in_reg, SB2_q_a[1]_PORT_A_address_reg, SB2_q_a[1]_PORT_B_address_reg, SB2_q_a[1]_PORT_A_write_enable_reg, SB2_q_a[1]_PORT_B_write_enable_reg, , , SB2_q_a[1]_clock_0, SB2_q_a[1]_clock_1, SB2_q_a[1]_clock_enable_0, , , );
SB2_q_a[1] = SB2_q_a[1]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[1]
J1_p1_registered_cpu_0_data_master_readdata[1] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & SB2_q_a[1] # !Q1_read_0 & (Q1_ien_AE);


--X1_endofpacketvalue_reg[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[1]
X1_endofpacketvalue_reg[1] = DFFEAS(H1_d_writedata[1], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_reg[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[1]
X1_asmi_slave_select_reg[1] = DFFEAS(X1_asmi_slave_select_holding_reg[1], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1_rx_holding_reg[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[1]
X1_rx_holding_reg[1] = DFFEAS(X1_shift_reg[1], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1L137 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[1]~2534
X1L137 = A1L110 & X1_asmi_slave_select_reg[1] # !A1L110 & (X1_rx_holding_reg[1]);


--X1L138 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[1]~2535
X1L138 = !X1L85 & (A1L75 & X1_endofpacketvalue_reg[1] # !A1L75 & (X1L137));


--SB2_q_a[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB2_q_a[0]_PORT_A_data_in = VCC;
SB2_q_a[0]_PORT_A_data_in_reg = DFFE(SB2_q_a[0]_PORT_A_data_in, SB2_q_a[0]_clock_0, , , SB2_q_a[0]_clock_enable_0);
SB2_q_a[0]_PORT_B_data_in = FB1_wdata[0];
SB2_q_a[0]_PORT_B_data_in_reg = DFFE(SB2_q_a[0]_PORT_B_data_in, SB2_q_a[0]_clock_1, , , );
SB2_q_a[0]_PORT_A_address = BUS(PB3_safe_q[0], PB3_safe_q[1], PB3_safe_q[2], PB3_safe_q[3], PB3_safe_q[4], PB3_safe_q[5], PB3_safe_q[6], PB3_safe_q[7], PB3_safe_q[8]);
SB2_q_a[0]_PORT_A_address_reg = DFFE(SB2_q_a[0]_PORT_A_address, SB2_q_a[0]_clock_0, , , SB2_q_a[0]_clock_enable_0);
SB2_q_a[0]_PORT_B_address = BUS(PB4_safe_q[0], PB4_safe_q[1], PB4_safe_q[2], PB4_safe_q[3], PB4_safe_q[4], PB4_safe_q[5], PB4_safe_q[6], PB4_safe_q[7], PB4_safe_q[8]);
SB2_q_a[0]_PORT_B_address_reg = DFFE(SB2_q_a[0]_PORT_B_address, SB2_q_a[0]_clock_1, , , );
SB2_q_a[0]_PORT_A_write_enable = GND;
SB2_q_a[0]_PORT_A_write_enable_reg = DFFE(SB2_q_a[0]_PORT_A_write_enable, SB2_q_a[0]_clock_0, , , SB2_q_a[0]_clock_enable_0);
SB2_q_a[0]_PORT_B_write_enable = Q1_wr_rfifo;
SB2_q_a[0]_PORT_B_write_enable_reg = DFFE(SB2_q_a[0]_PORT_B_write_enable, SB2_q_a[0]_clock_1, , , );
SB2_q_a[0]_clock_0 = CLOCK_50;
SB2_q_a[0]_clock_1 = CLOCK_50;
SB2_q_a[0]_clock_enable_0 = Q1L81;
SB2_q_a[0]_PORT_A_data_out = MEMORY(SB2_q_a[0]_PORT_A_data_in_reg, SB2_q_a[0]_PORT_B_data_in_reg, SB2_q_a[0]_PORT_A_address_reg, SB2_q_a[0]_PORT_B_address_reg, SB2_q_a[0]_PORT_A_write_enable_reg, SB2_q_a[0]_PORT_B_write_enable_reg, , , SB2_q_a[0]_clock_0, SB2_q_a[0]_clock_1, SB2_q_a[0]_clock_enable_0, , , );
SB2_q_a[0] = SB2_q_a[0]_PORT_A_data_out[0];


--J1_p1_registered_cpu_0_data_master_readdata[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[0]
J1_p1_registered_cpu_0_data_master_readdata[0] = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & SB2_q_a[0] # !Q1_read_0 & (Q1_ien_AF);


--X1_endofpacketvalue_reg[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_reg[0]
X1_endofpacketvalue_reg[0] = DFFEAS(H1_d_writedata[0], CLOCK_50, E1_data_out,  , X1_endofpacketvalue_wr_strobe,  ,  ,  ,  );


--X1_rx_holding_reg[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rx_holding_reg[0]
X1_rx_holding_reg[0] = DFFEAS(X1_shift_reg[0], CLOCK_50, E1_data_out,  , X1L21,  ,  ,  ,  );


--X1_asmi_slave_select_reg[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_reg[0]
X1_asmi_slave_select_reg[0] = DFFEAS(X1_asmi_slave_select_holding_reg[0], CLOCK_50, E1_data_out,  , X1L44,  ,  ,  ,  );


--X1L135 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[0]~2536
X1L135 = A1L110 & (!X1_asmi_slave_select_reg[0]) # !A1L110 & X1_rx_holding_reg[0];


--X1L136 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_to_cpu[0]~2537
X1L136 = !X1L85 & (A1L75 & X1_endofpacketvalue_reg[0] # !A1L75 & (X1L135));


--H1L741 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[26]~170
H1L741 = AMPP_FUNCTION(H1_R_ctrl_dst_data_sel_logic_result, H1_R_ctrl_shift_rot);


--H1L742 is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[26]~171
H1L742 = AMPP_FUNCTION(H1_R_ctrl_shift_rot, H1_E_alu_sub, H1_R_ctrl_dst_data_sel_logic_result);


--H1L124 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[31]~1312
H1L124 = AMPP_FUNCTION(H1L741, H1L927, H1L742, H1L947);


--H1L125 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[31]~1313
H1L125 = AMPP_FUNCTION(H1L180, H1L741, H1L124, H1_E_shift_rot_result[31]);


--H1L126 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[31]~1314
H1L126 = AMPP_FUNCTION(H1L125, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L1099 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~571
H1L1099 = AMPP_FUNCTION(DB1_q_a[31], W1_incoming_tri_state_bridge_0_data[7], W1_cpu_0_data_master_requests_cfi_flash_0_s1, M1_cpu_0_data_master_requests_data_RAM_s1);


--H1L1100 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~572
H1L1100 = AMPP_FUNCTION(EB1_q_a[31], VB1L16, T1L11, P1_cpu_0_data_master_requests_firmware_ROM_s1);


--H1L1101 is DE2_Board:inst|cpu_0:the_cpu_0|av_ld_byte3_data_nxt~573
H1L1101 = AMPP_FUNCTION(H1L1072, H1L1084, H1L1099, H1L1100);


--H1L121 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[30]~1315
H1L121 = AMPP_FUNCTION(H1L742, H1L179, H1L741, H1L945);


--H1_E_shift_rot_result[30] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[30]
H1_E_shift_rot_result[30] = AMPP_FUNCTION(CLOCK_50, H1L267, H1_E_src1[30], E1_data_out, H1_E_new_inst);


--H1L122 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[30]~1316
H1L122 = AMPP_FUNCTION(H1L925, H1L742, H1L121, H1_E_shift_rot_result[30]);


--H1L123 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[30]~1317
H1L123 = AMPP_FUNCTION(H1L122, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L118 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[29]~1318
H1L118 = AMPP_FUNCTION(H1L741, H1L923, H1L742, H1L943);


--H1_E_shift_rot_result[29] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[29]
H1_E_shift_rot_result[29] = AMPP_FUNCTION(CLOCK_50, H1L266, H1_E_src1[29], E1_data_out, H1_E_new_inst);


--H1L119 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[29]~1319
H1L119 = AMPP_FUNCTION(H1L178, H1L741, H1L118, H1_E_shift_rot_result[29]);


--H1L120 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[29]~1320
H1L120 = AMPP_FUNCTION(H1L119, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L115 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[28]~1321
H1L115 = AMPP_FUNCTION(H1L742, H1L177, H1L741, H1L941);


--H1_E_shift_rot_result[28] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[28]
H1_E_shift_rot_result[28] = AMPP_FUNCTION(CLOCK_50, H1L265, H1_E_src1[28], E1_data_out, H1_E_new_inst);


--H1L116 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[28]~1322
H1L116 = AMPP_FUNCTION(H1L921, H1L742, H1L115, H1_E_shift_rot_result[28]);


--H1L117 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[28]~1323
H1L117 = AMPP_FUNCTION(H1L116, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L112 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[27]~1324
H1L112 = AMPP_FUNCTION(H1L741, H1L919, H1L742, H1L939);


--H1_E_shift_rot_result[27] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[27]
H1_E_shift_rot_result[27] = AMPP_FUNCTION(CLOCK_50, H1L264, H1_E_src1[27], E1_data_out, H1_E_new_inst);


--H1L113 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[27]~1325
H1L113 = AMPP_FUNCTION(H1L176, H1L741, H1L112, H1_E_shift_rot_result[27]);


--H1L114 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[27]~1326
H1L114 = AMPP_FUNCTION(H1L113, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L109 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[26]~1327
H1L109 = AMPP_FUNCTION(H1L742, H1L175, H1L741, H1L937);


--H1_E_shift_rot_result[26] is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[26]
H1_E_shift_rot_result[26] = AMPP_FUNCTION(CLOCK_50, H1L263, H1_E_src1[26], E1_data_out, H1_E_new_inst);


--H1L110 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[26]~1328
H1L110 = AMPP_FUNCTION(H1L917, H1L742, H1L109, H1_E_shift_rot_result[26]);


--H1L111 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[26]~1329
H1L111 = AMPP_FUNCTION(H1L110, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L106 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[25]~1330
H1L106 = AMPP_FUNCTION(H1L741, H1L915, H1L742, H1L935);


--H1L107 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[25]~1331
H1L107 = AMPP_FUNCTION(H1L174, H1L741, H1L106, H1_E_shift_rot_result[25]);


--H1L108 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[25]~1332
H1L108 = AMPP_FUNCTION(H1L107, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L103 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[24]~1333
H1L103 = AMPP_FUNCTION(H1L742, H1L173, H1L741, H1L933);


--H1L104 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[24]~1334
H1L104 = AMPP_FUNCTION(H1L913, H1L742, H1L103, H1_E_shift_rot_result[24]);


--H1L105 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[24]~1335
H1L105 = AMPP_FUNCTION(H1L104, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L100 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[23]~1336
H1L100 = AMPP_FUNCTION(H1L741, H1L911, H1L742, H1L931);


--H1L101 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[23]~1337
H1L101 = AMPP_FUNCTION(H1L172, H1L741, H1L100, H1_E_shift_rot_result[23]);


--H1L102 is DE2_Board:inst|cpu_0:the_cpu_0|E_alu_result[23]~1338
H1L102 = AMPP_FUNCTION(H1L101, H1_R_ctrl_dst_data_sel_cmp, H1_R_ctrl_rdctl_inst);


--H1L262 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[25]~469
H1L262 = AMPP_FUNCTION(H1_E_shift_rot_result[26], H1_E_shift_rot_result[24], H1_R_ctrl_shift_rot_right);


--X1_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|wr_strobe
X1_wr_strobe = DFFEAS(X1_p1_wr_strobe, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1_control_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|control_wr_strobe
X1_control_wr_strobe = H1_W_alu_result[3] & H1_W_alu_result[2] & X1_wr_strobe & !H1_W_alu_result[4];


--X1_slowcount[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|slowcount[0]
X1_slowcount[0] = DFFEAS(X1L172, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1_state[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state[0]
X1_state[0] = DFFEAS(X1L34, CLOCK_50, E1_data_out,  , X1L45,  ,  ,  ,  );


--X1_state[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state[4]
X1_state[4] = DFFEAS(X1L213, CLOCK_50, E1_data_out,  , X1L45,  ,  ,  ,  );


--X1_state[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state[3]
X1_state[3] = DFFEAS(X1L40, CLOCK_50, E1_data_out,  , X1L45,  ,  ,  ,  );


--X1_state[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state[2]
X1_state[2] = DFFEAS(X1L38, CLOCK_50, E1_data_out,  , X1L45,  ,  ,  ,  );


--X1_state[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state[1]
X1_state[1] = DFFEAS(X1L214, CLOCK_50, E1_data_out,  , X1L45,  ,  ,  ,  );


--A1L112 is rtl~2855
A1L112 = !X1_state[3] & !X1_state[2] & !X1_state[1];


--X1L21 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|ROE~104
X1L21 = X1_slowcount[0] & X1_state[0] & X1_state[4] & A1L112;


--X1_status_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|status_wr_strobe
X1_status_wr_strobe = H1_W_alu_result[3] & X1_wr_strobe & !H1_W_alu_result[4] & !H1_W_alu_result[2];


--X1L22 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|ROE~105
X1L22 = X1_RRDY & (X1L21 # X1_ROE & !X1_status_wr_strobe) # !X1_RRDY & (X1_ROE & !X1_status_wr_strobe);


--X1_data_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_wr_strobe
X1_data_wr_strobe = DFFEAS(X1_p1_data_wr_strobe, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L32 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|TOE~59
X1L32 = !X1_status_wr_strobe & (X1_TOE # X1_data_wr_strobe & !X1L33);


--X1_rd_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|rd_strobe
X1_rd_strobe = DFFEAS(X1L171, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L171 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_rd_strobe~33
X1L171 = !X1_rd_strobe & H1_d_read & H1_W_alu_result[17] & A1L109;


--X1_p1_data_rd_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_rd_strobe
X1_p1_data_rd_strobe = !H1_W_alu_result[4] & !H1_W_alu_result[3] & !H1_W_alu_result[2] & X1L171;


--X1L174 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_wr_strobe~31
X1L174 = X1_wr_strobe # !AB1_d_write;


--X1_p1_data_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_data_wr_strobe
X1_p1_data_wr_strobe = H1_W_alu_result[2] & A1L107 & G1_asmi_asmi_control_port_chipselect & !X1L174;


--X1L3 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~158
X1L3 = H1_d_writedata[4] & X1_endofpacketvalue_reg[4] & (H1_d_writedata[2] $ !X1_endofpacketvalue_reg[2]) # !H1_d_writedata[4] & !X1_endofpacketvalue_reg[4] & (H1_d_writedata[2] $ !X1_endofpacketvalue_reg[2]);


--X1L4 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~159
X1L4 = H1_d_writedata[7] & X1_endofpacketvalue_reg[7] & (H1_d_writedata[0] $ !X1_endofpacketvalue_reg[0]) # !H1_d_writedata[7] & !X1_endofpacketvalue_reg[7] & (H1_d_writedata[0] $ !X1_endofpacketvalue_reg[0]);


--X1L5 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~160
X1L5 = H1_d_writedata[6] & X1_endofpacketvalue_reg[6] & (H1_d_writedata[3] $ !X1_endofpacketvalue_reg[3]) # !H1_d_writedata[6] & !X1_endofpacketvalue_reg[6] & (H1_d_writedata[3] $ !X1_endofpacketvalue_reg[3]);


--X1L6 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~161
X1L6 = H1_d_writedata[5] & X1_endofpacketvalue_reg[5] & (H1_d_writedata[1] $ !X1_endofpacketvalue_reg[1]) # !H1_d_writedata[5] & !X1_endofpacketvalue_reg[5] & (H1_d_writedata[1] $ !X1_endofpacketvalue_reg[1]);


--X1L7 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~162
X1L7 = X1L3 & X1L4 & X1L5 & X1L6;


--X1L8 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~163
X1L8 = X1_endofpacketvalue_reg[4] & X1_rx_holding_reg[4] & (X1_endofpacketvalue_reg[2] $ !X1_rx_holding_reg[2]) # !X1_endofpacketvalue_reg[4] & !X1_rx_holding_reg[4] & (X1_endofpacketvalue_reg[2] $ !X1_rx_holding_reg[2]);


--X1L9 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~164
X1L9 = X1_endofpacketvalue_reg[7] & X1_rx_holding_reg[7] & (X1_endofpacketvalue_reg[0] $ !X1_rx_holding_reg[0]) # !X1_endofpacketvalue_reg[7] & !X1_rx_holding_reg[7] & (X1_endofpacketvalue_reg[0] $ !X1_rx_holding_reg[0]);


--X1L10 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~165
X1L10 = X1_endofpacketvalue_reg[6] & X1_rx_holding_reg[6] & (X1_endofpacketvalue_reg[3] $ !X1_rx_holding_reg[3]) # !X1_endofpacketvalue_reg[6] & !X1_rx_holding_reg[6] & (X1_endofpacketvalue_reg[3] $ !X1_rx_holding_reg[3]);


--X1L11 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~166
X1L11 = X1_endofpacketvalue_reg[5] & X1_rx_holding_reg[5] & (X1_endofpacketvalue_reg[1] $ !X1_rx_holding_reg[1]) # !X1_endofpacketvalue_reg[5] & !X1_rx_holding_reg[5] & (X1_endofpacketvalue_reg[1] $ !X1_rx_holding_reg[1]);


--X1L12 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~167
X1L12 = X1L8 & X1L9 & X1L10 & X1L11;


--X1L13 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~168
X1L13 = X1_p1_data_rd_strobe & (X1L12 # X1_p1_data_wr_strobe & X1L7) # !X1_p1_data_rd_strobe & X1_p1_data_wr_strobe & X1L7;


--X1L14 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~169
X1L14 = !X1_endofpacketvalue_reg[15] & !X1_endofpacketvalue_reg[14];


--X1L15 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~170
X1L15 = !X1_endofpacketvalue_reg[11] & !X1_endofpacketvalue_reg[10] & !X1_endofpacketvalue_reg[9] & !X1_endofpacketvalue_reg[8];


--X1L16 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~171
X1L16 = X1L14 & X1L15 & !X1_endofpacketvalue_reg[13] & !X1_endofpacketvalue_reg[12];


--X1L17 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|EOP~172
X1L17 = !X1_status_wr_strobe & (X1_EOP # X1L13 & X1L16);


--X1_data_rd_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|data_rd_strobe
X1_data_rd_strobe = DFFEAS(X1_p1_data_rd_strobe, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L24 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|RRDY~64
X1L24 = X1L21 # X1_RRDY & !X1_status_wr_strobe & !X1_data_rd_strobe;


--X1L220 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_primed~30
X1L220 = X1_data_wr_strobe # X1_tx_holding_primed & X1_transmitting;


--Q1_wr_rfifo is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|wr_rfifo
Q1_wr_rfifo = FB1L59Q & !MB2_b_full;


--QB2_counter_comb_bita0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita0
QB2_counter_comb_bita0 = QB2_safe_q[0] $ (VCC # !Q1_wr_rfifo);

--QB2L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita0~COUT
QB2L2 = CARRY(QB2_safe_q[0] $ !Q1_wr_rfifo);


--QB2_counter_comb_bita1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita1
QB2_counter_comb_bita1 = QB2L2 & (QB2_safe_q[1] $ (Q1_wr_rfifo # VCC)) # !QB2L2 & (QB2_safe_q[1] # GND);

--QB2L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita1~COUT
QB2L4 = CARRY(QB2_safe_q[1] $ Q1_wr_rfifo # !QB2L2);


--QB2_counter_comb_bita2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita2
QB2_counter_comb_bita2 = QB2L4 & QB2_safe_q[2] & (VCC) # !QB2L4 & (QB2_safe_q[2] $ (VCC # !Q1_wr_rfifo));

--QB2L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita2~COUT
QB2L6 = CARRY(!QB2L4 & (QB2_safe_q[2] $ !Q1_wr_rfifo));


--QB2_counter_comb_bita3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita3
QB2_counter_comb_bita3 = QB2L6 & (QB2_safe_q[3] $ (Q1_wr_rfifo # VCC)) # !QB2L6 & (QB2_safe_q[3] # GND);

--QB2L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita3~COUT
QB2L8 = CARRY(QB2_safe_q[3] $ Q1_wr_rfifo # !QB2L6);


--Q1L69 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|fifo_rd~34
Q1L69 = H1_d_read & A1L99 & !H1_W_alu_result[2] & !J1_cpu_0_data_master_waitrequest;


--MB2L1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|_~28
MB2L1 = MB2_b_non_empty & (Q1L69 $ (!MB2_b_full & FB1L59Q)) # !MB2_b_non_empty & (!MB2_b_full & FB1L59Q);


--QB2_counter_comb_bita4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita4
QB2_counter_comb_bita4 = QB2L8 & QB2_safe_q[4] & (VCC) # !QB2L8 & (QB2_safe_q[4] $ (VCC # !Q1_wr_rfifo));

--QB2L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita4~COUT
QB2L10 = CARRY(!QB2L8 & (QB2_safe_q[4] $ !Q1_wr_rfifo));


--QB2_counter_comb_bita5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita5
QB2_counter_comb_bita5 = QB2L10 & (QB2_safe_q[5] $ (Q1_wr_rfifo # VCC)) # !QB2L10 & (QB2_safe_q[5] # GND);

--QB2L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita5~COUT
QB2L12 = CARRY(QB2_safe_q[5] $ Q1_wr_rfifo # !QB2L10);


--QB2_counter_comb_bita6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita6
QB2_counter_comb_bita6 = QB2L12 & QB2_safe_q[6] & (VCC) # !QB2L12 & (QB2_safe_q[6] $ (VCC # !Q1_wr_rfifo));

--QB2L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita6~COUT
QB2L14 = CARRY(!QB2L12 & (QB2_safe_q[6] $ !Q1_wr_rfifo));


--QB2_counter_comb_bita7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita7
QB2_counter_comb_bita7 = QB2L14 & (QB2_safe_q[7] $ (Q1_wr_rfifo # VCC)) # !QB2L14 & (QB2_safe_q[7] # GND);

--QB2L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita7~COUT
QB2L16 = CARRY(QB2_safe_q[7] $ Q1_wr_rfifo # !QB2L14);


--QB2_counter_comb_bita8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita8
QB2_counter_comb_bita8 = QB2_safe_q[8] $ !QB2L16;


--MB2L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|_~110
MB2L2 = QB2_safe_q[3] # QB2_safe_q[6] # QB2_safe_q[5] # QB2_safe_q[4];


--MB2L9 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty~132
MB2L9 = !QB2_safe_q[8] & !QB2_safe_q[2] & !QB2_safe_q[1] & QB2_safe_q[0];


--MB2L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty~133
MB2L10 = !QB2_safe_q[7] & !MB2L2 & Q1L81 & MB2L9;


--MB2L11 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty~134
MB2L11 = FB1L59Q # MB2_b_full # MB2_b_non_empty & !MB2L10;


--FB1_write_valid is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_valid
FB1_write_valid = AMPP_FUNCTION(A1L5, FB1_td_shift[10], D1_CLRN_SIGNAL, FB1L93);


--FB1L60 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~70
FB1L60 = AMPP_FUNCTION(Q1_t_dav, FB1_write_stalled, FB1_write_valid);


--FB1_jupdate1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate1
FB1_jupdate1 = AMPP_FUNCTION(CLOCK_50, FB1_jupdate, E1_data_out);


--FB1_jupdate2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate2
FB1_jupdate2 = AMPP_FUNCTION(CLOCK_50, FB1_jupdate1, E1_data_out);


--FB1L61 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~71
FB1L61 = AMPP_FUNCTION(FB1L2, FB1L60, FB1_jupdate1, FB1_jupdate2);


--Q1_fifo_wr is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|fifo_wr
Q1_fifo_wr = DFFEAS(Q1L71, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--QB1_counter_comb_bita0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita0
QB1_counter_comb_bita0 = QB1_safe_q[0] $ (VCC # !Q1_fifo_wr);

--QB1L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita0~COUT
QB1L2 = CARRY(QB1_safe_q[0] $ !Q1_fifo_wr);


--QB1_counter_comb_bita1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita1
QB1_counter_comb_bita1 = QB1L2 & (QB1_safe_q[1] $ (Q1_fifo_wr # VCC)) # !QB1L2 & (QB1_safe_q[1] # GND);

--QB1L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita1~COUT
QB1L4 = CARRY(QB1_safe_q[1] $ Q1_fifo_wr # !QB1L2);


--QB1_counter_comb_bita2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita2
QB1_counter_comb_bita2 = QB1L4 & QB1_safe_q[2] & (VCC) # !QB1L4 & (QB1_safe_q[2] $ (VCC # !Q1_fifo_wr));

--QB1L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita2~COUT
QB1L6 = CARRY(!QB1L4 & (QB1_safe_q[2] $ !Q1_fifo_wr));


--QB1_counter_comb_bita3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita3
QB1_counter_comb_bita3 = QB1L6 & (QB1_safe_q[3] $ (Q1_fifo_wr # VCC)) # !QB1L6 & (QB1_safe_q[3] # GND);

--QB1L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita3~COUT
QB1L8 = CARRY(QB1_safe_q[3] $ Q1_fifo_wr # !QB1L6);


--QB1_counter_comb_bita4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita4
QB1_counter_comb_bita4 = QB1L8 & QB1_safe_q[4] & (VCC) # !QB1L8 & (QB1_safe_q[4] $ (VCC # !Q1_fifo_wr));

--QB1L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita4~COUT
QB1L10 = CARRY(!QB1L8 & (QB1_safe_q[4] $ !Q1_fifo_wr));


--MB1_b_non_empty is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty
MB1_b_non_empty = DFFEAS(MB1L10, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--Q1_rd_wfifo is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|rd_wfifo
Q1_rd_wfifo = MB1_b_non_empty & !FB1_rvalid0 & (!FB1_r_ena1 # !Q1_r_val);


--MB1L1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|_~28
MB1L1 = Q1_fifo_wr $ Q1_rd_wfifo;


--MB1L3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~150
MB1L3 = QB1_safe_q[8] & QB1_safe_q[7] & QB1_safe_q[6] & QB1_safe_q[5];


--MB1L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~151
MB1L4 = QB1_safe_q[4] & QB1_safe_q[3] & QB1_safe_q[0] & QB1_safe_q[2];


--MB1L5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~152
MB1L5 = QB1_safe_q[1] & Q1_fifo_wr & MB1_b_non_empty & MB1L4;


--MB1L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_full~153
MB1L6 = !Q1_rd_wfifo & (MB1_b_full # MB1L3 & MB1L5);


--QB1_counter_comb_bita5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita5
QB1_counter_comb_bita5 = QB1L10 & (QB1_safe_q[5] $ (Q1_fifo_wr # VCC)) # !QB1L10 & (QB1_safe_q[5] # GND);

--QB1L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita5~COUT
QB1L12 = CARRY(QB1_safe_q[5] $ Q1_fifo_wr # !QB1L10);


--QB1_counter_comb_bita6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita6
QB1_counter_comb_bita6 = QB1L12 & QB1_safe_q[6] & (VCC) # !QB1L12 & (QB1_safe_q[6] $ (VCC # !Q1_fifo_wr));

--QB1L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita6~COUT
QB1L14 = CARRY(!QB1L12 & (QB1_safe_q[6] $ !Q1_fifo_wr));


--QB1_counter_comb_bita7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita7
QB1_counter_comb_bita7 = QB1L14 & (QB1_safe_q[7] $ (Q1_fifo_wr # VCC)) # !QB1L14 & (QB1_safe_q[7] # GND);

--QB1L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita7~COUT
QB1L16 = CARRY(QB1_safe_q[7] $ Q1_fifo_wr # !QB1L14);


--QB1_counter_comb_bita8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw|counter_comb_bita8
QB1_counter_comb_bita8 = QB1_safe_q[8] $ !QB1L16;


--H1L268 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[31]~470
H1L268 = AMPP_FUNCTION(H1L203, H1_E_shift_rot_result[30], H1_R_ctrl_shift_rot_right);


--H1L40 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_rot_right~26
H1L40 = AMPP_FUNCTION(H1_D_iw[14], H1L42, H1_D_iw[13], H1_D_iw[15]);


--H1L41 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_shift_logical~32
H1L41 = AMPP_FUNCTION(H1_D_iw[15], H1L42, H1_D_iw[13], H1_D_iw[16]);


--EC1_w_anode78w[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|w_anode78w[3]
EC1_w_anode78w[3] = AMPP_FUNCTION(ZB3_Q[1], ZB3_Q[3], ZB3_Q[2], D1L28);


--PB1_safe_q[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[0]
PB1_safe_q[0] = DFFEAS(PB1_counter_comb_bita0, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[1]
PB1_safe_q[1] = DFFEAS(PB1_counter_comb_bita1, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[2]
PB1_safe_q[2] = DFFEAS(PB1_counter_comb_bita2, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[3]
PB1_safe_q[3] = DFFEAS(PB1_counter_comb_bita3, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[4]
PB1_safe_q[4] = DFFEAS(PB1_counter_comb_bita4, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[5]
PB1_safe_q[5] = DFFEAS(PB1_counter_comb_bita5, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[6]
PB1_safe_q[6] = DFFEAS(PB1_counter_comb_bita6, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[7]
PB1_safe_q[7] = DFFEAS(PB1_counter_comb_bita7, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB1_safe_q[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[8]
PB1_safe_q[8] = DFFEAS(PB1_counter_comb_bita8, CLOCK_50,  ,  , Q1_rd_wfifo,  ,  ,  ,  );


--PB2_safe_q[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[0]
PB2_safe_q[0] = DFFEAS(PB2_counter_comb_bita0, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[1]
PB2_safe_q[1] = DFFEAS(PB2_counter_comb_bita1, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[2]
PB2_safe_q[2] = DFFEAS(PB2_counter_comb_bita2, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[3]
PB2_safe_q[3] = DFFEAS(PB2_counter_comb_bita3, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[4]
PB2_safe_q[4] = DFFEAS(PB2_counter_comb_bita4, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[5]
PB2_safe_q[5] = DFFEAS(PB2_counter_comb_bita5, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[6]
PB2_safe_q[6] = DFFEAS(PB2_counter_comb_bita6, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[7]
PB2_safe_q[7] = DFFEAS(PB2_counter_comb_bita7, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--PB2_safe_q[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[8]
PB2_safe_q[8] = DFFEAS(PB2_counter_comb_bita8, CLOCK_50,  ,  , Q1_fifo_wr,  ,  ,  ,  );


--FB1_td_shift[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4]
FB1_td_shift[4] = AMPP_FUNCTION(A1L5, FB1L82, D1_CLRN_SIGNAL, FB1L44);


--FB1_rdata[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[1]
FB1_rdata[1] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[1], E1_data_out, FB1L28);


--FB1L79 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1394
FB1L79 = AMPP_FUNCTION(FB1_td_shift[4], FB1_rdata[1], FB1_count[9]);


--FB1L80 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1395
FB1L80 = AMPP_FUNCTION(ZB4_Q[0], FB1L79, DC1_state[4], FB1L46);


--SB1_q_a[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[0]_PORT_A_data_in = VCC;
SB1_q_a[0]_PORT_A_data_in_reg = DFFE(SB1_q_a[0]_PORT_A_data_in, SB1_q_a[0]_clock_0, , , SB1_q_a[0]_clock_enable_0);
SB1_q_a[0]_PORT_B_data_in = H1_d_writedata[0];
SB1_q_a[0]_PORT_B_data_in_reg = DFFE(SB1_q_a[0]_PORT_B_data_in, SB1_q_a[0]_clock_1, , , );
SB1_q_a[0]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[0]_PORT_A_address_reg = DFFE(SB1_q_a[0]_PORT_A_address, SB1_q_a[0]_clock_0, , , SB1_q_a[0]_clock_enable_0);
SB1_q_a[0]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[0]_PORT_B_address_reg = DFFE(SB1_q_a[0]_PORT_B_address, SB1_q_a[0]_clock_1, , , );
SB1_q_a[0]_PORT_A_write_enable = GND;
SB1_q_a[0]_PORT_A_write_enable_reg = DFFE(SB1_q_a[0]_PORT_A_write_enable, SB1_q_a[0]_clock_0, , , SB1_q_a[0]_clock_enable_0);
SB1_q_a[0]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[0]_PORT_B_write_enable_reg = DFFE(SB1_q_a[0]_PORT_B_write_enable, SB1_q_a[0]_clock_1, , , );
SB1_q_a[0]_clock_0 = CLOCK_50;
SB1_q_a[0]_clock_1 = CLOCK_50;
SB1_q_a[0]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[0]_PORT_A_data_out = MEMORY(SB1_q_a[0]_PORT_A_data_in_reg, SB1_q_a[0]_PORT_B_data_in_reg, SB1_q_a[0]_PORT_A_address_reg, SB1_q_a[0]_PORT_B_address_reg, SB1_q_a[0]_PORT_A_write_enable_reg, SB1_q_a[0]_PORT_B_write_enable_reg, , , SB1_q_a[0]_clock_0, SB1_q_a[0]_clock_1, SB1_q_a[0]_clock_enable_0, , , );
SB1_q_a[0] = SB1_q_a[0]_PORT_A_data_out[0];


--FB1_read_write is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write
FB1_read_write = AMPP_FUNCTION(A1L5, FB1L43, D1_CLRN_SIGNAL, FB1L95);


--FB1_count[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[6]
FB1_count[6] = AMPP_FUNCTION(A1L5, FB1L18, D1_CLRN_SIGNAL, FB1L44);


--FB1L17 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~217
FB1L17 = AMPP_FUNCTION(DC1_state[4], FB1_count[6]);


--DC1_state[13] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13]
DC1_state[13] = AMPP_FUNCTION(A1L5, DC1L27, A1L7);


--DC1L28 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~28
DC1L28 = AMPP_FUNCTION(A1L7, DC1_state[13]);


--AC1L33 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~758
AC1L33 = AMPP_FUNCTION(D1_jtag_debug_mode_usr1, DC1_state[8], DC1_state[4], AC1_word_counter[0]);


--AC1L34 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~759
AC1L34 = AMPP_FUNCTION(AC1L33, AC1_word_counter[1], AC1_word_counter[2], AC1_word_counter[3]);


--AC1L35 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~760
AC1L35 = AMPP_FUNCTION(AC1L34, altera_internal_jtag, DC1_state[4], AC1_clear_signal);


--AC1L15 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]~239
AC1L15 = AMPP_FUNCTION(AC1_word_counter[3], GND, AC1L13);

--AC1L16 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]~240
AC1L16 = AMPP_FUNCTION(AC1_word_counter[3], AC1L13);


--AC1L18 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]~241
AC1L18 = AMPP_FUNCTION(AC1_word_counter[4], AC1L16);


--Q1L54 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~660
Q1L54 = QB1_safe_q[7] & (Q1L46 # GND) # !QB1_safe_q[7] & !Q1L46;

--Q1L55 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~661
Q1L55 = CARRY(QB1_safe_q[7] # !Q1L46);


--Q1L56 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~662
Q1L56 = QB1_safe_q[8] & !Q1L55 & VCC # !QB1_safe_q[8] & (Q1L55 $ GND);

--Q1L57 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~663
Q1L57 = CARRY(!QB1_safe_q[8] & !Q1L55);


--Q1L58 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~664
Q1L58 = MB1_b_full $ Q1L57;


--Q1L60 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~666
Q1L60 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & MB2_b_full # !Q1_read_0 & (Q1L58);


--Q1L61 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~667
Q1L61 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[8] # !Q1_read_0 & (Q1L56);


--X1_endofpacketvalue_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|endofpacketvalue_wr_strobe
X1_endofpacketvalue_wr_strobe = H1_W_alu_result[4] & H1_W_alu_result[3] & X1_wr_strobe & !H1_W_alu_result[2];


--X1_asmi_slave_select_holding_reg[15] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[15]
X1_asmi_slave_select_holding_reg[15] = DFFEAS(H1_d_writedata[15], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1L217 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|transmitting~84
X1L217 = X1_tx_holding_primed & !X1_transmitting;


--X1L44 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|always6~2
X1L44 = X1L217 # H1_d_writedata[10] & X1_control_wr_strobe & !X1_SSO_reg;


--Q1L82 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|rvalid~19
Q1L82 = Q1L69 & MB2_b_non_empty # !Q1L69 & (Q1_rvalid);


--Q1L62 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|add~668
Q1L62 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_read_0 & QB2_safe_q[7] # !Q1_read_0 & (Q1L54);


--X1_asmi_slave_select_holding_reg[14] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[14]
X1_asmi_slave_select_holding_reg[14] = DFFEAS(H1_d_writedata[14], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--Q1L63 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|always2~32
Q1L63 = AB1_d_write & A1L99 & !J1_cpu_0_data_master_waitrequest;


--Q1L85 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|woverflow~62
Q1L85 = Q1L63 & (H1_W_alu_result[2] & Q1_woverflow # !H1_W_alu_result[2] & (MB1_b_full)) # !Q1L63 & Q1_woverflow;


--X1_asmi_slave_select_holding_reg[13] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[13]
X1_asmi_slave_select_holding_reg[13] = DFFEAS(H1_d_writedata[13], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_holding_reg[12] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[12]
X1_asmi_slave_select_holding_reg[12] = DFFEAS(H1_d_writedata[12], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_holding_reg[11] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[11]
X1_asmi_slave_select_holding_reg[11] = DFFEAS(H1_d_writedata[11], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_holding_reg[10] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[10]
X1_asmi_slave_select_holding_reg[10] = DFFEAS(H1_d_writedata[10], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--Q1L9 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|ac~73
Q1L9 = FB1L62Q # FB1L59Q;


--Q1L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|ac~74
Q1L10 = Q1L9 # Q1_ac & (!Q1L73 # !H1_d_writedata[10]);


--X1_asmi_slave_select_holding_reg[9] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[9]
X1_asmi_slave_select_holding_reg[9] = DFFEAS(H1_d_writedata[9], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_asmi_slave_select_holding_reg[8] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[8]
X1_asmi_slave_select_holding_reg[8] = DFFEAS(H1_d_writedata[8], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--PB3_safe_q[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[0]
PB3_safe_q[0] = DFFEAS(PB3_counter_comb_bita0, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[1]
PB3_safe_q[1] = DFFEAS(PB3_counter_comb_bita1, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[2]
PB3_safe_q[2] = DFFEAS(PB3_counter_comb_bita2, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[3]
PB3_safe_q[3] = DFFEAS(PB3_counter_comb_bita3, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[4]
PB3_safe_q[4] = DFFEAS(PB3_counter_comb_bita4, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[5]
PB3_safe_q[5] = DFFEAS(PB3_counter_comb_bita5, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[6]
PB3_safe_q[6] = DFFEAS(PB3_counter_comb_bita6, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[7]
PB3_safe_q[7] = DFFEAS(PB3_counter_comb_bita7, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--PB3_safe_q[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|safe_q[8]
PB3_safe_q[8] = DFFEAS(PB3_counter_comb_bita8, CLOCK_50,  ,  , Q1L81,  ,  ,  ,  );


--FB1_wdata[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7]
FB1_wdata[7] = AMPP_FUNCTION(A1L5, altera_internal_jtag, D1_CLRN_SIGNAL, FB1L95);


--PB4_safe_q[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[0]
PB4_safe_q[0] = DFFEAS(PB4_counter_comb_bita0, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[1]
PB4_safe_q[1] = DFFEAS(PB4_counter_comb_bita1, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[2]
PB4_safe_q[2] = DFFEAS(PB4_counter_comb_bita2, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[3]
PB4_safe_q[3] = DFFEAS(PB4_counter_comb_bita3, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[4]
PB4_safe_q[4] = DFFEAS(PB4_counter_comb_bita4, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[5]
PB4_safe_q[5] = DFFEAS(PB4_counter_comb_bita5, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[6]
PB4_safe_q[6] = DFFEAS(PB4_counter_comb_bita6, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[7]
PB4_safe_q[7] = DFFEAS(PB4_counter_comb_bita7, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--PB4_safe_q[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|safe_q[8]
PB4_safe_q[8] = DFFEAS(PB4_counter_comb_bita8, CLOCK_50,  ,  , Q1_wr_rfifo,  ,  ,  ,  );


--X1_asmi_slave_select_holding_reg[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[7]
X1_asmi_slave_select_holding_reg[7] = DFFEAS(H1_d_writedata[7], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[7]
X1_shift_reg[7] = DFFEAS(X1L195, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[6]
FB1_wdata[6] = AMPP_FUNCTION(A1L5, FB1_td_shift[10], D1_CLRN_SIGNAL, FB1L95);


--X1_asmi_slave_select_holding_reg[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[6]
X1_asmi_slave_select_holding_reg[6] = DFFEAS(H1_d_writedata[6], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[6]
X1_shift_reg[6] = DFFEAS(X1L196, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[5]
FB1_wdata[5] = AMPP_FUNCTION(A1L5, FB1_td_shift[9], D1_CLRN_SIGNAL, FB1L95);


--X1_asmi_slave_select_holding_reg[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[5]
X1_asmi_slave_select_holding_reg[5] = DFFEAS(H1_d_writedata[5], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[5]
X1_shift_reg[5] = DFFEAS(X1L197, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[4]
FB1_wdata[4] = AMPP_FUNCTION(A1L5, FB1_td_shift[8], D1_CLRN_SIGNAL, FB1L95);


--X1_asmi_slave_select_holding_reg[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[4]
X1_asmi_slave_select_holding_reg[4] = DFFEAS(H1_d_writedata[4], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[4]
X1_shift_reg[4] = DFFEAS(X1L198, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[3]
FB1_wdata[3] = AMPP_FUNCTION(A1L5, FB1_td_shift[7], D1_CLRN_SIGNAL, FB1L95);


--X1_asmi_slave_select_holding_reg[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[3]
X1_asmi_slave_select_holding_reg[3] = DFFEAS(H1_d_writedata[3], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[3]
X1_shift_reg[3] = DFFEAS(X1L199, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[2]
FB1_wdata[2] = AMPP_FUNCTION(A1L5, FB1_td_shift[6], D1_CLRN_SIGNAL, FB1L95);


--X1_asmi_slave_select_holding_reg[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[2]
X1_asmi_slave_select_holding_reg[2] = DFFEAS(H1_d_writedata[2], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[2]
X1_shift_reg[2] = DFFEAS(X1L200, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1]
FB1_wdata[1] = AMPP_FUNCTION(A1L5, FB1_td_shift[5], D1_CLRN_SIGNAL, FB1L95);


--X1_asmi_slave_select_holding_reg[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[1]
X1_asmi_slave_select_holding_reg[1] = DFFEAS(H1_d_writedata[1], CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--X1_shift_reg[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[1]
X1_shift_reg[1] = DFFEAS(X1L201, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--FB1_wdata[0] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0]
FB1_wdata[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, D1_CLRN_SIGNAL, FB1L93);


--X1_shift_reg[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[0]
X1_shift_reg[0] = DFFEAS(X1L202, CLOCK_50, E1_data_out,  , X1L194,  ,  ,  ,  );


--X1_asmi_slave_select_holding_reg[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[0]
X1_asmi_slave_select_holding_reg[0] = DFFEAS(X1L48, CLOCK_50, E1_data_out,  , X1_slaveselect_wr_strobe,  ,  ,  ,  );


--H1L267 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[30]~471
H1L267 = AMPP_FUNCTION(H1_E_shift_rot_result[31], H1_E_shift_rot_result[29], H1_R_ctrl_shift_rot_right);


--H1L266 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[29]~472
H1L266 = AMPP_FUNCTION(H1_E_shift_rot_result[30], H1_E_shift_rot_result[28], H1_R_ctrl_shift_rot_right);


--H1L265 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[28]~473
H1L265 = AMPP_FUNCTION(H1_E_shift_rot_result[29], H1_E_shift_rot_result[27], H1_R_ctrl_shift_rot_right);


--H1L264 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[27]~474
H1L264 = AMPP_FUNCTION(H1_E_shift_rot_result[28], H1_E_shift_rot_result[26], H1_R_ctrl_shift_rot_right);


--H1L263 is DE2_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result_nxt[26]~475
H1L263 = AMPP_FUNCTION(H1_E_shift_rot_result[27], H1_E_shift_rot_result[25], H1_R_ctrl_shift_rot_right);


--X1_p1_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_wr_strobe
X1_p1_wr_strobe = !X1L174 & P1L7 & H1_W_alu_result[17] & A1L109;


--X1L172 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|p1_slowcount[0]~11
X1L172 = X1_transmitting & !X1_slowcount[0];


--X1L34 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~97
X1L34 = X1_state[0] $ VCC;

--X1L35 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~98
X1L35 = CARRY(X1_state[0]);


--X1L45 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|always11~0
X1L45 = X1_transmitting & X1_slowcount[0];


--X1L36 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~99
X1L36 = X1_state[1] & !X1L35 # !X1_state[1] & (X1L35 # GND);

--X1L37 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~100
X1L37 = CARRY(!X1L35 # !X1_state[1]);


--X1L38 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~101
X1L38 = X1_state[2] & (X1L37 $ GND) # !X1_state[2] & !X1L37 & VCC;

--X1L39 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~102
X1L39 = CARRY(X1_state[2] & !X1L37);


--X1L40 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~103
X1L40 = X1_state[3] & !X1L39 # !X1_state[3] & (X1L39 # GND);

--X1L41 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~104
X1L41 = CARRY(!X1L39 # !X1_state[3]);


--X1L42 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|add~105
X1L42 = X1_state[4] $ !X1L41;


--X1L213 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state~88
X1L213 = X1L42 & (!A1L112 # !X1_state[4] # !X1_state[0]);


--X1L214 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|state~89
X1L214 = X1L36 & (!A1L112 # !X1_state[4] # !X1_state[0]);


--FB1_jupdate is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate
FB1_jupdate = AMPP_FUNCTION(!A1L5, FB1L26, D1_CLRN_SIGNAL);


--Q1L71 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|fifo_wr~26
Q1L71 = !H1_W_alu_result[2] & !MB1_b_full & Q1L63;


--MB1L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty~159
MB1L8 = QB1_safe_q[3] # QB1_safe_q[2] # QB1_safe_q[1] # !QB1_safe_q[0];


--MB1L9 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty~160
MB1L9 = QB1_safe_q[4] # MB1L8 # !Q1_rd_wfifo # !Q1L6;


--MB1L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|b_non_empty~161
MB1L10 = MB1_b_full # Q1_fifo_wr # MB1_b_non_empty & MB1L9;


--PB1_counter_comb_bita0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita0
PB1_counter_comb_bita0 = PB1_safe_q[0] $ VCC;

--PB1L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita0~COUT
PB1L2 = CARRY(PB1_safe_q[0]);


--PB1_counter_comb_bita1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita1
PB1_counter_comb_bita1 = PB1_safe_q[1] & !PB1L2 # !PB1_safe_q[1] & (PB1L2 # GND);

--PB1L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita1~COUT
PB1L4 = CARRY(!PB1L2 # !PB1_safe_q[1]);


--PB1_counter_comb_bita2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita2
PB1_counter_comb_bita2 = PB1_safe_q[2] & (PB1L4 $ GND) # !PB1_safe_q[2] & !PB1L4 & VCC;

--PB1L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita2~COUT
PB1L6 = CARRY(PB1_safe_q[2] & !PB1L4);


--PB1_counter_comb_bita3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita3
PB1_counter_comb_bita3 = PB1_safe_q[3] & !PB1L6 # !PB1_safe_q[3] & (PB1L6 # GND);

--PB1L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita3~COUT
PB1L8 = CARRY(!PB1L6 # !PB1_safe_q[3]);


--PB1_counter_comb_bita4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita4
PB1_counter_comb_bita4 = PB1_safe_q[4] & (PB1L8 $ GND) # !PB1_safe_q[4] & !PB1L8 & VCC;

--PB1L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita4~COUT
PB1L10 = CARRY(PB1_safe_q[4] & !PB1L8);


--PB1_counter_comb_bita5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita5
PB1_counter_comb_bita5 = PB1_safe_q[5] & !PB1L10 # !PB1_safe_q[5] & (PB1L10 # GND);

--PB1L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita5~COUT
PB1L12 = CARRY(!PB1L10 # !PB1_safe_q[5]);


--PB1_counter_comb_bita6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita6
PB1_counter_comb_bita6 = PB1_safe_q[6] & (PB1L12 $ GND) # !PB1_safe_q[6] & !PB1L12 & VCC;

--PB1L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita6~COUT
PB1L14 = CARRY(PB1_safe_q[6] & !PB1L12);


--PB1_counter_comb_bita7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita7
PB1_counter_comb_bita7 = PB1_safe_q[7] & !PB1L14 # !PB1_safe_q[7] & (PB1L14 # GND);

--PB1L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita7~COUT
PB1L16 = CARRY(!PB1L14 # !PB1_safe_q[7]);


--PB1_counter_comb_bita8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita8
PB1_counter_comb_bita8 = PB1_safe_q[8] $ !PB1L16;


--PB2_counter_comb_bita0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita0
PB2_counter_comb_bita0 = PB2_safe_q[0] $ VCC;

--PB2L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita0~COUT
PB2L2 = CARRY(PB2_safe_q[0]);


--PB2_counter_comb_bita1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita1
PB2_counter_comb_bita1 = PB2_safe_q[1] & !PB2L2 # !PB2_safe_q[1] & (PB2L2 # GND);

--PB2L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita1~COUT
PB2L4 = CARRY(!PB2L2 # !PB2_safe_q[1]);


--PB2_counter_comb_bita2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita2
PB2_counter_comb_bita2 = PB2_safe_q[2] & (PB2L4 $ GND) # !PB2_safe_q[2] & !PB2L4 & VCC;

--PB2L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita2~COUT
PB2L6 = CARRY(PB2_safe_q[2] & !PB2L4);


--PB2_counter_comb_bita3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita3
PB2_counter_comb_bita3 = PB2_safe_q[3] & !PB2L6 # !PB2_safe_q[3] & (PB2L6 # GND);

--PB2L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita3~COUT
PB2L8 = CARRY(!PB2L6 # !PB2_safe_q[3]);


--PB2_counter_comb_bita4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita4
PB2_counter_comb_bita4 = PB2_safe_q[4] & (PB2L8 $ GND) # !PB2_safe_q[4] & !PB2L8 & VCC;

--PB2L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita4~COUT
PB2L10 = CARRY(PB2_safe_q[4] & !PB2L8);


--PB2_counter_comb_bita5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita5
PB2_counter_comb_bita5 = PB2_safe_q[5] & !PB2L10 # !PB2_safe_q[5] & (PB2L10 # GND);

--PB2L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita5~COUT
PB2L12 = CARRY(!PB2L10 # !PB2_safe_q[5]);


--PB2_counter_comb_bita6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita6
PB2_counter_comb_bita6 = PB2_safe_q[6] & (PB2L12 $ GND) # !PB2_safe_q[6] & !PB2L12 & VCC;

--PB2L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita6~COUT
PB2L14 = CARRY(PB2_safe_q[6] & !PB2L12);


--PB2_counter_comb_bita7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita7
PB2_counter_comb_bita7 = PB2_safe_q[7] & !PB2L14 # !PB2_safe_q[7] & (PB2L14 # GND);

--PB2L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita7~COUT
PB2L16 = CARRY(!PB2L14 # !PB2_safe_q[7]);


--PB2_counter_comb_bita8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita8
PB2_counter_comb_bita8 = PB2_safe_q[8] $ !PB2L16;


--FB1_td_shift[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[5]
FB1_td_shift[5] = AMPP_FUNCTION(A1L5, FB1L83, D1_CLRN_SIGNAL, FB1L44);


--FB1_rdata[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[2]
FB1_rdata[2] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[2], E1_data_out, FB1L28);


--FB1L81 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1396
FB1L81 = AMPP_FUNCTION(FB1_td_shift[5], FB1_rdata[2], FB1_count[9]);


--FB1L82 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1397
FB1L82 = AMPP_FUNCTION(ZB4_Q[0], FB1L81, DC1_state[4], FB1L46);


--SB1_q_a[1] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[1]_PORT_A_data_in = VCC;
SB1_q_a[1]_PORT_A_data_in_reg = DFFE(SB1_q_a[1]_PORT_A_data_in, SB1_q_a[1]_clock_0, , , SB1_q_a[1]_clock_enable_0);
SB1_q_a[1]_PORT_B_data_in = H1_d_writedata[1];
SB1_q_a[1]_PORT_B_data_in_reg = DFFE(SB1_q_a[1]_PORT_B_data_in, SB1_q_a[1]_clock_1, , , );
SB1_q_a[1]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[1]_PORT_A_address_reg = DFFE(SB1_q_a[1]_PORT_A_address, SB1_q_a[1]_clock_0, , , SB1_q_a[1]_clock_enable_0);
SB1_q_a[1]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[1]_PORT_B_address_reg = DFFE(SB1_q_a[1]_PORT_B_address, SB1_q_a[1]_clock_1, , , );
SB1_q_a[1]_PORT_A_write_enable = GND;
SB1_q_a[1]_PORT_A_write_enable_reg = DFFE(SB1_q_a[1]_PORT_A_write_enable, SB1_q_a[1]_clock_0, , , SB1_q_a[1]_clock_enable_0);
SB1_q_a[1]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[1]_PORT_B_write_enable_reg = DFFE(SB1_q_a[1]_PORT_B_write_enable, SB1_q_a[1]_clock_1, , , );
SB1_q_a[1]_clock_0 = CLOCK_50;
SB1_q_a[1]_clock_1 = CLOCK_50;
SB1_q_a[1]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[1]_PORT_A_data_out = MEMORY(SB1_q_a[1]_PORT_A_data_in_reg, SB1_q_a[1]_PORT_B_data_in_reg, SB1_q_a[1]_PORT_A_address_reg, SB1_q_a[1]_PORT_B_address_reg, SB1_q_a[1]_PORT_A_write_enable_reg, SB1_q_a[1]_PORT_B_write_enable_reg, , , SB1_q_a[1]_clock_0, SB1_q_a[1]_clock_1, SB1_q_a[1]_clock_enable_0, , , );
SB1_q_a[1] = SB1_q_a[1]_PORT_A_data_out[0];


--FB1L95 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[1]~6
FB1L95 = AMPP_FUNCTION(FB1_count[8], FB1L89);


--FB1_count[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[5]
FB1_count[5] = AMPP_FUNCTION(A1L5, FB1L19, D1_CLRN_SIGNAL, FB1L44);


--FB1L18 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~218
FB1L18 = AMPP_FUNCTION(DC1_state[4], FB1_count[5]);


--DC1L27 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~26
DC1L27 = AMPP_FUNCTION(DC1_state[12], DC1_state[13]);


--X1_slaveselect_wr_strobe is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|slaveselect_wr_strobe
X1_slaveselect_wr_strobe = H1_W_alu_result[4] & H1_W_alu_result[2] & X1_wr_strobe & !H1_W_alu_result[3];


--PB3_counter_comb_bita0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita0
PB3_counter_comb_bita0 = PB3_safe_q[0] $ VCC;

--PB3L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita0~COUT
PB3L2 = CARRY(PB3_safe_q[0]);


--PB3_counter_comb_bita1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita1
PB3_counter_comb_bita1 = PB3_safe_q[1] & !PB3L2 # !PB3_safe_q[1] & (PB3L2 # GND);

--PB3L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita1~COUT
PB3L4 = CARRY(!PB3L2 # !PB3_safe_q[1]);


--PB3_counter_comb_bita2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita2
PB3_counter_comb_bita2 = PB3_safe_q[2] & (PB3L4 $ GND) # !PB3_safe_q[2] & !PB3L4 & VCC;

--PB3L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita2~COUT
PB3L6 = CARRY(PB3_safe_q[2] & !PB3L4);


--PB3_counter_comb_bita3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita3
PB3_counter_comb_bita3 = PB3_safe_q[3] & !PB3L6 # !PB3_safe_q[3] & (PB3L6 # GND);

--PB3L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita3~COUT
PB3L8 = CARRY(!PB3L6 # !PB3_safe_q[3]);


--PB3_counter_comb_bita4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita4
PB3_counter_comb_bita4 = PB3_safe_q[4] & (PB3L8 $ GND) # !PB3_safe_q[4] & !PB3L8 & VCC;

--PB3L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita4~COUT
PB3L10 = CARRY(PB3_safe_q[4] & !PB3L8);


--PB3_counter_comb_bita5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita5
PB3_counter_comb_bita5 = PB3_safe_q[5] & !PB3L10 # !PB3_safe_q[5] & (PB3L10 # GND);

--PB3L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita5~COUT
PB3L12 = CARRY(!PB3L10 # !PB3_safe_q[5]);


--PB3_counter_comb_bita6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita6
PB3_counter_comb_bita6 = PB3_safe_q[6] & (PB3L12 $ GND) # !PB3_safe_q[6] & !PB3L12 & VCC;

--PB3L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita6~COUT
PB3L14 = CARRY(PB3_safe_q[6] & !PB3L12);


--PB3_counter_comb_bita7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita7
PB3_counter_comb_bita7 = PB3_safe_q[7] & !PB3L14 # !PB3_safe_q[7] & (PB3L14 # GND);

--PB3L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita7~COUT
PB3L16 = CARRY(!PB3L14 # !PB3_safe_q[7]);


--PB3_counter_comb_bita8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count|counter_comb_bita8
PB3_counter_comb_bita8 = PB3_safe_q[8] $ !PB3L16;


--PB4_counter_comb_bita0 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita0
PB4_counter_comb_bita0 = PB4_safe_q[0] $ VCC;

--PB4L2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita0~COUT
PB4L2 = CARRY(PB4_safe_q[0]);


--PB4_counter_comb_bita1 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita1
PB4_counter_comb_bita1 = PB4_safe_q[1] & !PB4L2 # !PB4_safe_q[1] & (PB4L2 # GND);

--PB4L4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita1~COUT
PB4L4 = CARRY(!PB4L2 # !PB4_safe_q[1]);


--PB4_counter_comb_bita2 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita2
PB4_counter_comb_bita2 = PB4_safe_q[2] & (PB4L4 $ GND) # !PB4_safe_q[2] & !PB4L4 & VCC;

--PB4L6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita2~COUT
PB4L6 = CARRY(PB4_safe_q[2] & !PB4L4);


--PB4_counter_comb_bita3 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita3
PB4_counter_comb_bita3 = PB4_safe_q[3] & !PB4L6 # !PB4_safe_q[3] & (PB4L6 # GND);

--PB4L8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita3~COUT
PB4L8 = CARRY(!PB4L6 # !PB4_safe_q[3]);


--PB4_counter_comb_bita4 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita4
PB4_counter_comb_bita4 = PB4_safe_q[4] & (PB4L8 $ GND) # !PB4_safe_q[4] & !PB4L8 & VCC;

--PB4L10 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita4~COUT
PB4L10 = CARRY(PB4_safe_q[4] & !PB4L8);


--PB4_counter_comb_bita5 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita5
PB4_counter_comb_bita5 = PB4_safe_q[5] & !PB4L10 # !PB4_safe_q[5] & (PB4L10 # GND);

--PB4L12 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita5~COUT
PB4L12 = CARRY(!PB4L10 # !PB4_safe_q[5]);


--PB4_counter_comb_bita6 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita6
PB4_counter_comb_bita6 = PB4_safe_q[6] & (PB4L12 $ GND) # !PB4_safe_q[6] & !PB4L12 & VCC;

--PB4L14 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita6~COUT
PB4L14 = CARRY(PB4_safe_q[6] & !PB4L12);


--PB4_counter_comb_bita7 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita7
PB4_counter_comb_bita7 = PB4_safe_q[7] & !PB4L14 # !PB4_safe_q[7] & (PB4L14 # GND);

--PB4L16 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita7~COUT
PB4L16 = CARRY(!PB4L14 # !PB4_safe_q[7]);


--PB4_counter_comb_bita8 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr|counter_comb_bita8
PB4_counter_comb_bita8 = PB4_safe_q[8] $ !PB4L16;


--X1_tx_holding_reg[7] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[7]
X1_tx_holding_reg[7] = DFFEAS(H1_d_writedata[7], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1_SCLK_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|SCLK_reg
X1_SCLK_reg = DFFEAS(X1L27, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1L195 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~423
X1L195 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[6] # !X1_SCLK_reg & (X1_tx_holding_reg[7])) # !X1_slowcount[0] & (X1_tx_holding_reg[7]);


--X1L194 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg[7]~424
X1L194 = X1_transmitting & (X1_slowcount[0] & X1_SCLK_reg) # !X1_transmitting & (X1_tx_holding_primed # X1_slowcount[0] & X1_SCLK_reg);


--X1_tx_holding_reg[6] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[6]
X1_tx_holding_reg[6] = DFFEAS(H1_d_writedata[6], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L196 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~425
X1L196 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[5] # !X1_SCLK_reg & (X1_tx_holding_reg[6])) # !X1_slowcount[0] & (X1_tx_holding_reg[6]);


--X1_tx_holding_reg[5] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[5]
X1_tx_holding_reg[5] = DFFEAS(H1_d_writedata[5], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L197 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~426
X1L197 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[4] # !X1_SCLK_reg & (X1_tx_holding_reg[5])) # !X1_slowcount[0] & (X1_tx_holding_reg[5]);


--FB1_td_shift[8] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8]
FB1_td_shift[8] = AMPP_FUNCTION(A1L5, FB1L84, D1_CLRN_SIGNAL, !DC1_state[4], FB1L44);


--X1_tx_holding_reg[4] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[4]
X1_tx_holding_reg[4] = DFFEAS(H1_d_writedata[4], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L198 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~427
X1L198 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[3] # !X1_SCLK_reg & (X1_tx_holding_reg[4])) # !X1_slowcount[0] & (X1_tx_holding_reg[4]);


--FB1_td_shift[7] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7]
FB1_td_shift[7] = AMPP_FUNCTION(A1L5, FB1L86, D1_CLRN_SIGNAL, FB1L44);


--X1_tx_holding_reg[3] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[3]
X1_tx_holding_reg[3] = DFFEAS(H1_d_writedata[3], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L199 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~428
X1L199 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[2] # !X1_SCLK_reg & (X1_tx_holding_reg[3])) # !X1_slowcount[0] & (X1_tx_holding_reg[3]);


--FB1_td_shift[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[6]
FB1_td_shift[6] = AMPP_FUNCTION(A1L5, FB1L87, D1_CLRN_SIGNAL, FB1L44);


--X1_tx_holding_reg[2] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[2]
X1_tx_holding_reg[2] = DFFEAS(H1_d_writedata[2], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L200 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~429
X1L200 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[1] # !X1_SCLK_reg & (X1_tx_holding_reg[2])) # !X1_slowcount[0] & (X1_tx_holding_reg[2]);


--X1_tx_holding_reg[1] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[1]
X1_tx_holding_reg[1] = DFFEAS(H1_d_writedata[1], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L201 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~430
X1L201 = X1_slowcount[0] & (X1_SCLK_reg & X1_shift_reg[0] # !X1_SCLK_reg & (X1_tx_holding_reg[1])) # !X1_slowcount[0] & (X1_tx_holding_reg[1]);


--X1_MISO_reg is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|MISO_reg
X1_MISO_reg = DFFEAS(X1L19, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--X1_tx_holding_reg[0] is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|tx_holding_reg[0]
X1_tx_holding_reg[0] = DFFEAS(H1_d_writedata[0], CLOCK_50, E1_data_out,  , X1_write_tx_holding,  ,  ,  ,  );


--X1L202 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|shift_reg~431
X1L202 = X1_slowcount[0] & (X1_SCLK_reg & X1_MISO_reg # !X1_SCLK_reg & (X1_tx_holding_reg[0])) # !X1_slowcount[0] & (X1_tx_holding_reg[0]);


--FB1L26 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~41
FB1L26 = AMPP_FUNCTION(FB1_jupdate, ZB4_Q[0], DC1_state[8], FB1L1);


--FB1_rdata[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[3]
FB1_rdata[3] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[3], E1_data_out, FB1L28);


--FB1L83 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1398
FB1L83 = AMPP_FUNCTION(FB1L70, FB1_td_shift[6], FB1_rdata[3], FB1_count[9]);


--SB1_q_a[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[2]_PORT_A_data_in = VCC;
SB1_q_a[2]_PORT_A_data_in_reg = DFFE(SB1_q_a[2]_PORT_A_data_in, SB1_q_a[2]_clock_0, , , SB1_q_a[2]_clock_enable_0);
SB1_q_a[2]_PORT_B_data_in = H1_d_writedata[2];
SB1_q_a[2]_PORT_B_data_in_reg = DFFE(SB1_q_a[2]_PORT_B_data_in, SB1_q_a[2]_clock_1, , , );
SB1_q_a[2]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[2]_PORT_A_address_reg = DFFE(SB1_q_a[2]_PORT_A_address, SB1_q_a[2]_clock_0, , , SB1_q_a[2]_clock_enable_0);
SB1_q_a[2]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[2]_PORT_B_address_reg = DFFE(SB1_q_a[2]_PORT_B_address, SB1_q_a[2]_clock_1, , , );
SB1_q_a[2]_PORT_A_write_enable = GND;
SB1_q_a[2]_PORT_A_write_enable_reg = DFFE(SB1_q_a[2]_PORT_A_write_enable, SB1_q_a[2]_clock_0, , , SB1_q_a[2]_clock_enable_0);
SB1_q_a[2]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[2]_PORT_B_write_enable_reg = DFFE(SB1_q_a[2]_PORT_B_write_enable, SB1_q_a[2]_clock_1, , , );
SB1_q_a[2]_clock_0 = CLOCK_50;
SB1_q_a[2]_clock_1 = CLOCK_50;
SB1_q_a[2]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[2]_PORT_A_data_out = MEMORY(SB1_q_a[2]_PORT_A_data_in_reg, SB1_q_a[2]_PORT_B_data_in_reg, SB1_q_a[2]_PORT_A_address_reg, SB1_q_a[2]_PORT_B_address_reg, SB1_q_a[2]_PORT_A_write_enable_reg, SB1_q_a[2]_PORT_B_write_enable_reg, , , SB1_q_a[2]_clock_0, SB1_q_a[2]_clock_1, SB1_q_a[2]_clock_enable_0, , , );
SB1_q_a[2] = SB1_q_a[2]_PORT_A_data_out[0];


--FB1_count[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[4]
FB1_count[4] = AMPP_FUNCTION(A1L5, FB1L20, D1_CLRN_SIGNAL, FB1L44);


--FB1L19 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~219
FB1L19 = AMPP_FUNCTION(DC1_state[4], FB1_count[4]);


--X1_write_tx_holding is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|write_tx_holding
X1_write_tx_holding = X1_data_wr_strobe & (!X1_transmitting # !X1_tx_holding_primed);


--X1L26 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|SCLK_reg~295
X1L26 = A1L112 & (X1_state[0] $ !X1_state[4]);


--X1L27 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|SCLK_reg~296
X1L27 = X1_slowcount[0] & (X1_SCLK_reg & (!X1L28) # !X1_SCLK_reg & !X1L26 & X1L28) # !X1_slowcount[0] & X1_SCLK_reg;


--FB1_rdata[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[6]
FB1_rdata[6] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[6], E1_data_out, FB1L28);


--FB1L84 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1399
FB1L84 = AMPP_FUNCTION(FB1_td_shift[9], FB1_rdata[6], FB1_count[9]);


--FB1_rdata[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[5]
FB1_rdata[5] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[5], E1_data_out, FB1L28);


--FB1L85 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1400
FB1L85 = AMPP_FUNCTION(FB1_td_shift[8], FB1_rdata[5], FB1_count[9]);


--FB1L86 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1401
FB1L86 = AMPP_FUNCTION(ZB4_Q[0], FB1L85, DC1_state[4], FB1L46);


--FB1_rdata[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rdata[4]
FB1_rdata[4] = AMPP_FUNCTION(CLOCK_50, SB1_q_a[4], E1_data_out, FB1L28);


--FB1L87 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift~1402
FB1L87 = AMPP_FUNCTION(FB1L70, FB1_td_shift[7], FB1_rdata[4], FB1_count[9]);


--Y1_data0out is DE2_Board:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom|data0out
Y1_data0out = ASMIBLOCK(X1_SCLK_reg, X1L30, X1_shift_reg[7], GND).DATA0OUT;


--X1L19 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|MISO_reg~61
X1L19 = X1_slowcount[0] & (X1_SCLK_reg & X1_MISO_reg # !X1_SCLK_reg & (Y1_data0out)) # !X1_slowcount[0] & X1_MISO_reg;


--SB1_q_a[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[3]_PORT_A_data_in = VCC;
SB1_q_a[3]_PORT_A_data_in_reg = DFFE(SB1_q_a[3]_PORT_A_data_in, SB1_q_a[3]_clock_0, , , SB1_q_a[3]_clock_enable_0);
SB1_q_a[3]_PORT_B_data_in = H1_d_writedata[3];
SB1_q_a[3]_PORT_B_data_in_reg = DFFE(SB1_q_a[3]_PORT_B_data_in, SB1_q_a[3]_clock_1, , , );
SB1_q_a[3]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[3]_PORT_A_address_reg = DFFE(SB1_q_a[3]_PORT_A_address, SB1_q_a[3]_clock_0, , , SB1_q_a[3]_clock_enable_0);
SB1_q_a[3]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[3]_PORT_B_address_reg = DFFE(SB1_q_a[3]_PORT_B_address, SB1_q_a[3]_clock_1, , , );
SB1_q_a[3]_PORT_A_write_enable = GND;
SB1_q_a[3]_PORT_A_write_enable_reg = DFFE(SB1_q_a[3]_PORT_A_write_enable, SB1_q_a[3]_clock_0, , , SB1_q_a[3]_clock_enable_0);
SB1_q_a[3]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[3]_PORT_B_write_enable_reg = DFFE(SB1_q_a[3]_PORT_B_write_enable, SB1_q_a[3]_clock_1, , , );
SB1_q_a[3]_clock_0 = CLOCK_50;
SB1_q_a[3]_clock_1 = CLOCK_50;
SB1_q_a[3]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[3]_PORT_A_data_out = MEMORY(SB1_q_a[3]_PORT_A_data_in_reg, SB1_q_a[3]_PORT_B_data_in_reg, SB1_q_a[3]_PORT_A_address_reg, SB1_q_a[3]_PORT_B_address_reg, SB1_q_a[3]_PORT_A_write_enable_reg, SB1_q_a[3]_PORT_B_write_enable_reg, , , SB1_q_a[3]_clock_0, SB1_q_a[3]_clock_1, SB1_q_a[3]_clock_enable_0, , , );
SB1_q_a[3] = SB1_q_a[3]_PORT_A_data_out[0];


--FB1_count[3] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[3]
FB1_count[3] = AMPP_FUNCTION(A1L5, FB1L21, D1_CLRN_SIGNAL, FB1L44);


--FB1L20 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~220
FB1L20 = AMPP_FUNCTION(DC1_state[4], FB1_count[3]);


--SB1_q_a[6] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[6]_PORT_A_data_in = VCC;
SB1_q_a[6]_PORT_A_data_in_reg = DFFE(SB1_q_a[6]_PORT_A_data_in, SB1_q_a[6]_clock_0, , , SB1_q_a[6]_clock_enable_0);
SB1_q_a[6]_PORT_B_data_in = H1_d_writedata[6];
SB1_q_a[6]_PORT_B_data_in_reg = DFFE(SB1_q_a[6]_PORT_B_data_in, SB1_q_a[6]_clock_1, , , );
SB1_q_a[6]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[6]_PORT_A_address_reg = DFFE(SB1_q_a[6]_PORT_A_address, SB1_q_a[6]_clock_0, , , SB1_q_a[6]_clock_enable_0);
SB1_q_a[6]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[6]_PORT_B_address_reg = DFFE(SB1_q_a[6]_PORT_B_address, SB1_q_a[6]_clock_1, , , );
SB1_q_a[6]_PORT_A_write_enable = GND;
SB1_q_a[6]_PORT_A_write_enable_reg = DFFE(SB1_q_a[6]_PORT_A_write_enable, SB1_q_a[6]_clock_0, , , SB1_q_a[6]_clock_enable_0);
SB1_q_a[6]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[6]_PORT_B_write_enable_reg = DFFE(SB1_q_a[6]_PORT_B_write_enable, SB1_q_a[6]_clock_1, , , );
SB1_q_a[6]_clock_0 = CLOCK_50;
SB1_q_a[6]_clock_1 = CLOCK_50;
SB1_q_a[6]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[6]_PORT_A_data_out = MEMORY(SB1_q_a[6]_PORT_A_data_in_reg, SB1_q_a[6]_PORT_B_data_in_reg, SB1_q_a[6]_PORT_A_address_reg, SB1_q_a[6]_PORT_B_address_reg, SB1_q_a[6]_PORT_A_write_enable_reg, SB1_q_a[6]_PORT_B_write_enable_reg, , , SB1_q_a[6]_clock_0, SB1_q_a[6]_clock_1, SB1_q_a[6]_clock_enable_0, , , );
SB1_q_a[6] = SB1_q_a[6]_PORT_A_data_out[0];


--SB1_q_a[5] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[5]_PORT_A_data_in = VCC;
SB1_q_a[5]_PORT_A_data_in_reg = DFFE(SB1_q_a[5]_PORT_A_data_in, SB1_q_a[5]_clock_0, , , SB1_q_a[5]_clock_enable_0);
SB1_q_a[5]_PORT_B_data_in = H1_d_writedata[5];
SB1_q_a[5]_PORT_B_data_in_reg = DFFE(SB1_q_a[5]_PORT_B_data_in, SB1_q_a[5]_clock_1, , , );
SB1_q_a[5]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[5]_PORT_A_address_reg = DFFE(SB1_q_a[5]_PORT_A_address, SB1_q_a[5]_clock_0, , , SB1_q_a[5]_clock_enable_0);
SB1_q_a[5]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[5]_PORT_B_address_reg = DFFE(SB1_q_a[5]_PORT_B_address, SB1_q_a[5]_clock_1, , , );
SB1_q_a[5]_PORT_A_write_enable = GND;
SB1_q_a[5]_PORT_A_write_enable_reg = DFFE(SB1_q_a[5]_PORT_A_write_enable, SB1_q_a[5]_clock_0, , , SB1_q_a[5]_clock_enable_0);
SB1_q_a[5]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[5]_PORT_B_write_enable_reg = DFFE(SB1_q_a[5]_PORT_B_write_enable, SB1_q_a[5]_clock_1, , , );
SB1_q_a[5]_clock_0 = CLOCK_50;
SB1_q_a[5]_clock_1 = CLOCK_50;
SB1_q_a[5]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[5]_PORT_A_data_out = MEMORY(SB1_q_a[5]_PORT_A_data_in_reg, SB1_q_a[5]_PORT_B_data_in_reg, SB1_q_a[5]_PORT_A_address_reg, SB1_q_a[5]_PORT_B_address_reg, SB1_q_a[5]_PORT_A_write_enable_reg, SB1_q_a[5]_PORT_B_write_enable_reg, , , SB1_q_a[5]_clock_0, SB1_q_a[5]_clock_1, SB1_q_a[5]_clock_enable_0, , , );
SB1_q_a[5] = SB1_q_a[5]_PORT_A_data_out[0];


--SB1_q_a[4] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
SB1_q_a[4]_PORT_A_data_in = VCC;
SB1_q_a[4]_PORT_A_data_in_reg = DFFE(SB1_q_a[4]_PORT_A_data_in, SB1_q_a[4]_clock_0, , , SB1_q_a[4]_clock_enable_0);
SB1_q_a[4]_PORT_B_data_in = H1_d_writedata[4];
SB1_q_a[4]_PORT_B_data_in_reg = DFFE(SB1_q_a[4]_PORT_B_data_in, SB1_q_a[4]_clock_1, , , );
SB1_q_a[4]_PORT_A_address = BUS(PB1_safe_q[0], PB1_safe_q[1], PB1_safe_q[2], PB1_safe_q[3], PB1_safe_q[4], PB1_safe_q[5], PB1_safe_q[6], PB1_safe_q[7], PB1_safe_q[8]);
SB1_q_a[4]_PORT_A_address_reg = DFFE(SB1_q_a[4]_PORT_A_address, SB1_q_a[4]_clock_0, , , SB1_q_a[4]_clock_enable_0);
SB1_q_a[4]_PORT_B_address = BUS(PB2_safe_q[0], PB2_safe_q[1], PB2_safe_q[2], PB2_safe_q[3], PB2_safe_q[4], PB2_safe_q[5], PB2_safe_q[6], PB2_safe_q[7], PB2_safe_q[8]);
SB1_q_a[4]_PORT_B_address_reg = DFFE(SB1_q_a[4]_PORT_B_address, SB1_q_a[4]_clock_1, , , );
SB1_q_a[4]_PORT_A_write_enable = GND;
SB1_q_a[4]_PORT_A_write_enable_reg = DFFE(SB1_q_a[4]_PORT_A_write_enable, SB1_q_a[4]_clock_0, , , SB1_q_a[4]_clock_enable_0);
SB1_q_a[4]_PORT_B_write_enable = Q1_fifo_wr;
SB1_q_a[4]_PORT_B_write_enable_reg = DFFE(SB1_q_a[4]_PORT_B_write_enable, SB1_q_a[4]_clock_1, , , );
SB1_q_a[4]_clock_0 = CLOCK_50;
SB1_q_a[4]_clock_1 = CLOCK_50;
SB1_q_a[4]_clock_enable_0 = Q1_rd_wfifo;
SB1_q_a[4]_PORT_A_data_out = MEMORY(SB1_q_a[4]_PORT_A_data_in_reg, SB1_q_a[4]_PORT_B_data_in_reg, SB1_q_a[4]_PORT_A_address_reg, SB1_q_a[4]_PORT_B_address_reg, SB1_q_a[4]_PORT_A_write_enable_reg, SB1_q_a[4]_PORT_B_write_enable_reg, , , SB1_q_a[4]_clock_0, SB1_q_a[4]_clock_1, SB1_q_a[4]_clock_enable_0, , , );
SB1_q_a[4] = SB1_q_a[4]_PORT_A_data_out[0];


--X1_stateZero is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|stateZero
X1_stateZero = DFFEAS(A1L76, CLOCK_50, E1_data_out,  , X1L45,  ,  ,  ,  );


--X1L30 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|SS_n~17
X1L30 = X1_asmi_slave_select_reg[0] # !X1_SSO_reg & (!X1_stateZero # !X1_transmitting);


--FB1_count[2] is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[2]
FB1_count[2] = AMPP_FUNCTION(A1L5, FB1L22, D1_CLRN_SIGNAL, FB1L44);


--FB1L21 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~221
FB1L21 = AMPP_FUNCTION(DC1_state[4], FB1_count[2]);


--A1L76 is rtl~139
A1L76 = !A1L112 # !X1_state[4] # !X1_state[0];


--FB1L22 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count~222
FB1L22 = AMPP_FUNCTION(DC1_state[4], FB1_count[1]);


--W1L128 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[2]~216
W1L128 = W1L136 & !W1L127 & (W1_tri_state_bridge_0_avalon_slave_arb_share_counter[1] # W1L125);


--H1L594 is DE2_Board:inst|cpu_0:the_cpu_0|F_pc_sel_nxt.10~37
H1L594 = AMPP_FUNCTION(H1_R_ctrl_exception, H1_R_ctrl_break, H1L592);


--H1L33 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_implicit_dst_eretaddr~145
H1L33 = AMPP_FUNCTION(H1_D_iw[4], H1_D_iw[3], A1L79, A1L65);


--H1L629 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[1]~1314
H1L629 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[1], H1L639);


--H1L628 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[0]~1315
H1L628 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[0], H1L639);


--H1L46 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_uncond_cti~135
H1L46 = AMPP_FUNCTION(H1_D_iw[11], H1_D_iw[16], H1L35, H1L45);


--T1L3 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|add~527
T1L3 = T1L55 & (T1_payload_buffer_s1_arb_share_counter[1]) # !T1L55 & (T1L13 # T1L8);


--T1L4 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|add~528
T1L4 = T1L55 & (T1_payload_buffer_s1_arb_share_counter[0]) # !T1L55 & !T1L13 & !T1L8;


--T1L42 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_arb_addend[1]~95
T1L42 = T1L13 & (!T1L24) # !T1L13 & (T1L8 & (!T1L24) # !T1L8 & T1_payload_buffer_s1_arb_addend[1]);


--H1L510 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3176
H1L510 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_0[0], H1L1171);


--H1L511 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3177
H1L511 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_0[2], H1L1171);


--H1L512 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3178
H1L512 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_1[4], H1L1171);


--H1L513 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3179
H1L513 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[2], H1L1171);


--H1L514 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3180
H1L514 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[1], H1L1171);


--H1L515 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3181
H1L515 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_1[2], H1L1171);


--H1L516 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3182
H1L516 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[0], H1L1171);


--H1L517 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3183
H1L517 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_1[1], H1L1171);


--H1L518 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3184
H1L518 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_2[7], H1L1171);


--H1L519 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3185
H1L519 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_1[0], H1L1171);


--H1L520 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3186
H1L520 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_2[6], H1L1171);


--H1L521 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3187
H1L521 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_0[7], H1L1171);


--H1L522 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3188
H1L522 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_0[6], H1L1171);


--H1L523 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3189
H1L523 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, K1_dbs_8_reg_segment_2[2], H1L1171);


--H1L638 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[31]~1316
H1L638 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[31], H1L639);


--H1L637 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[30]~1317
H1L637 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[30], H1L639);


--H1L636 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[29]~1318
H1L636 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[29], H1L639);


--H1L635 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[28]~1319
H1L635 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[28], H1L639);


--H1L634 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[27]~1320
H1L634 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[27], H1L639);


--H1L633 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[26]~1321
H1L633 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[26], H1L639);


--H1L632 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[25]~1322
H1L632 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[25], H1L639);


--H1L631 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[24]~1323
H1L631 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[24], H1L639);


--H1L630 is DE2_Board:inst|cpu_0:the_cpu_0|R_src1[23]~1324
H1L630 = AMPP_FUNCTION(H1_E_valid, H1_R_ctrl_jmp_direct, CB1_q_a[23], H1L639);


--Q1L65 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|av_waitrequest~43
Q1L65 = A1L99 & !J1_cpu_0_data_master_waitrequest & (H1_d_read # AB1_d_write);


--H1L524 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3190
H1L524 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[3], H1L1171);


--H1L525 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3191
H1L525 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[4], H1L1171);


--H1L526 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3192
H1L526 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[5], H1L1171);


--H1L527 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3193
H1L527 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[6], H1L1171);


--H1L528 is DE2_Board:inst|cpu_0:the_cpu_0|F_iw~3194
H1L528 = AMPP_FUNCTION(H1_F_pc[20], H1_i_read, W1_incoming_tri_state_bridge_0_data[7], H1L1171);


--J1L190 is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|p1_registered_cpu_0_data_master_readdata[8]~68
J1L190 = R1_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave # Q1_ien_AF & (Q1_fifo_AF # Q1_pause_irq);


--X1L218 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|transmitting~85
X1L218 = !X1L21 & (X1_tx_holding_primed # X1_transmitting);


--FB1L58 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~53
FB1L58 = AMPP_FUNCTION(FB1_read_write1, FB1_read_write2, FB1L59Q, FB1L60);


--X1L28 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|SCLK_reg~297
X1L28 = X1_state[0] & (X1_transmitting # X1_state[4] & A1L112) # !X1_state[0] & X1_transmitting & (X1_state[4] # !A1L112);


--H1L9 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~408
H1L9 = AMPP_FUNCTION(H1_D_iw[2], H1_D_iw[1], H1_D_iw[0]);


--H1L664 is DE2_Board:inst|cpu_0:the_cpu_0|R_src2_use_imm~99
H1L664 = AMPP_FUNCTION(H1_D_iw[0], H1_D_iw[1]);


--H1L99 is DE2_Board:inst|cpu_0:the_cpu_0|D_wr_dst_reg~88
H1L99 = AMPP_FUNCTION(H1_D_iw[0], H1_D_iw[1], H1_D_iw[2], H1_D_iw[4]);


--H1L10 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~409
H1L10 = AMPP_FUNCTION(H1_D_iw[1], H1_D_iw[2], H1_D_iw[0]);


--H1L11 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~410
H1L11 = AMPP_FUNCTION(H1_D_iw[2], H1_D_iw[1], H1_D_iw[0]);


--H1L12 is DE2_Board:inst|cpu_0:the_cpu_0|D_ctrl_alu_subtract~411
H1L12 = AMPP_FUNCTION(H1_D_iw[1], H1_D_iw[2], H1_D_iw[5], H1_D_iw[0]);


--ZB7L3 is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]~3
ZB7L3 = AMPP_FUNCTION(altera_internal_jtag);


--FB1L43 is DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write~4
FB1L43 = AMPP_FUNCTION(FB1_read_write);


--X1L48 is DE2_Board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub|asmi_slave_select_holding_reg[0]~48
X1L48 = !H1_d_writedata[0];


--KEY[0] is KEY[0]
--operation mode is input

KEY[0] = INPUT();


--CLOCK_50 is CLOCK_50
--operation mode is input

CLOCK_50 = INPUT();





--FL_CE_N is FL_CE_N
--operation mode is output

FL_CE_N = OUTPUT(!W1_select_n_to_the_cfi_flash_0);


--FL_OE_N is FL_OE_N
--operation mode is output

FL_OE_N = OUTPUT(!W1_tri_state_bridge_0_readn);


--FL_WE_N is FL_WE_N
--operation mode is output

FL_WE_N = OUTPUT(!W1_write_n_to_the_cfi_flash_0);


--FL_RST_N is FL_RST_N
--operation mode is output

FL_RST_N = OUTPUT(!C1_inst4);


--FL_ADDR[21] is FL_ADDR[21]
--operation mode is output

FL_ADDR[21] = OUTPUT(W1_tri_state_bridge_0_address[21]);


--FL_ADDR[20] is FL_ADDR[20]
--operation mode is output

FL_ADDR[20] = OUTPUT(W1_tri_state_bridge_0_address[20]);


--FL_ADDR[19] is FL_ADDR[19]
--operation mode is output

FL_ADDR[19] = OUTPUT(W1_tri_state_bridge_0_address[19]);


--FL_ADDR[18] is FL_ADDR[18]
--operation mode is output

FL_ADDR[18] = OUTPUT(W1_tri_state_bridge_0_address[18]);


--FL_ADDR[17] is FL_ADDR[17]
--operation mode is output

FL_ADDR[17] = OUTPUT(W1_tri_state_bridge_0_address[17]);


--FL_ADDR[16] is FL_ADDR[16]
--operation mode is output

FL_ADDR[16] = OUTPUT(W1_tri_state_bridge_0_address[16]);


--FL_ADDR[15] is FL_ADDR[15]
--operation mode is output

FL_ADDR[15] = OUTPUT(W1_tri_state_bridge_0_address[15]);


--FL_ADDR[14] is FL_ADDR[14]
--operation mode is output

FL_ADDR[14] = OUTPUT(W1_tri_state_bridge_0_address[14]);


--FL_ADDR[13] is FL_ADDR[13]
--operation mode is output

FL_ADDR[13] = OUTPUT(W1_tri_state_bridge_0_address[13]);


--FL_ADDR[12] is FL_ADDR[12]
--operation mode is output

FL_ADDR[12] = OUTPUT(W1_tri_state_bridge_0_address[12]);


--FL_ADDR[11] is FL_ADDR[11]
--operation mode is output

FL_ADDR[11] = OUTPUT(W1_tri_state_bridge_0_address[11]);


--FL_ADDR[10] is FL_ADDR[10]
--operation mode is output

FL_ADDR[10] = OUTPUT(W1_tri_state_bridge_0_address[10]);


--FL_ADDR[9] is FL_ADDR[9]
--operation mode is output

FL_ADDR[9] = OUTPUT(W1_tri_state_bridge_0_address[9]);


--FL_ADDR[8] is FL_ADDR[8]
--operation mode is output

FL_ADDR[8] = OUTPUT(W1_tri_state_bridge_0_address[8]);


--FL_ADDR[7] is FL_ADDR[7]
--operation mode is output

FL_ADDR[7] = OUTPUT(W1_tri_state_bridge_0_address[7]);


--FL_ADDR[6] is FL_ADDR[6]
--operation mode is output

FL_ADDR[6] = OUTPUT(W1_tri_state_bridge_0_address[6]);


--FL_ADDR[5] is FL_ADDR[5]
--operation mode is output

FL_ADDR[5] = OUTPUT(W1_tri_state_bridge_0_address[5]);


--FL_ADDR[4] is FL_ADDR[4]
--operation mode is output

FL_ADDR[4] = OUTPUT(W1_tri_state_bridge_0_address[4]);


--FL_ADDR[3] is FL_ADDR[3]
--operation mode is output

FL_ADDR[3] = OUTPUT(W1_tri_state_bridge_0_address[3]);


--FL_ADDR[2] is FL_ADDR[2]
--operation mode is output

FL_ADDR[2] = OUTPUT(W1_tri_state_bridge_0_address[2]);


--FL_ADDR[1] is FL_ADDR[1]
--operation mode is output

FL_ADDR[1] = OUTPUT(W1_tri_state_bridge_0_address[1]);


--FL_ADDR[0] is FL_ADDR[0]
--operation mode is output

FL_ADDR[0] = OUTPUT(W1_tri_state_bridge_0_address[0]);



--A1L48 is FL_DQ~0
--operation mode is bidir

A1L48 = FL_DQ[7];

--FL_DQ[7] is FL_DQ[7]
--operation mode is bidir

FL_DQ[7]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[7], !W1_d1_in_a_write_cycle);
FL_DQ[7] = BIDIR(FL_DQ[7]_tri_out);


--A1L49 is FL_DQ~1
--operation mode is bidir

A1L49 = FL_DQ[6];

--FL_DQ[6] is FL_DQ[6]
--operation mode is bidir

FL_DQ[6]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[6], !W1_d1_in_a_write_cycle);
FL_DQ[6] = BIDIR(FL_DQ[6]_tri_out);


--A1L50 is FL_DQ~2
--operation mode is bidir

A1L50 = FL_DQ[5];

--FL_DQ[5] is FL_DQ[5]
--operation mode is bidir

FL_DQ[5]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[5], !W1_d1_in_a_write_cycle);
FL_DQ[5] = BIDIR(FL_DQ[5]_tri_out);


--A1L51 is FL_DQ~3
--operation mode is bidir

A1L51 = FL_DQ[4];

--FL_DQ[4] is FL_DQ[4]
--operation mode is bidir

FL_DQ[4]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[4], !W1_d1_in_a_write_cycle);
FL_DQ[4] = BIDIR(FL_DQ[4]_tri_out);


--A1L52 is FL_DQ~4
--operation mode is bidir

A1L52 = FL_DQ[3];

--FL_DQ[3] is FL_DQ[3]
--operation mode is bidir

FL_DQ[3]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[3], !W1_d1_in_a_write_cycle);
FL_DQ[3] = BIDIR(FL_DQ[3]_tri_out);


--A1L53 is FL_DQ~5
--operation mode is bidir

A1L53 = FL_DQ[2];

--FL_DQ[2] is FL_DQ[2]
--operation mode is bidir

FL_DQ[2]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[2], !W1_d1_in_a_write_cycle);
FL_DQ[2] = BIDIR(FL_DQ[2]_tri_out);


--A1L54 is FL_DQ~6
--operation mode is bidir

A1L54 = FL_DQ[1];

--FL_DQ[1] is FL_DQ[1]
--operation mode is bidir

FL_DQ[1]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[1], !W1_d1_in_a_write_cycle);
FL_DQ[1] = BIDIR(FL_DQ[1]_tri_out);


--A1L55 is FL_DQ~7
--operation mode is bidir

A1L55 = FL_DQ[0];

--FL_DQ[0] is FL_DQ[0]
--operation mode is bidir

FL_DQ[0]_tri_out = TRI(W1_d1_outgoing_tri_state_bridge_0_data[0], !W1_d1_in_a_write_cycle);
FL_DQ[0] = BIDIR(FL_DQ[0]_tri_out);


--T1L39 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_address[12]~150
T1L39 = !T1L38;


--D1L14 is sld_hub:sld_hub_inst|hub_tdo~458
D1L14 = AMPP_FUNCTION(D1_hub_tdo);


