Analysis & Synthesis report for DE2_WEB
Tue Jul 25 22:47:25 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |DE2_WEB|I2C_AV_Config:u1|mSetup_ST
 10. State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state
 11. State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next
 12. State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state
 13. State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next
 14. State Machine - |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state
 15. State Machine - |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state
 16. State Machine - |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state
 17. State Machine - |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state
 18. State Machine - |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize
 19. Registers Protected by Synthesis
 20. Logic Cells Representing Combinational Loops
 21. General Register Statistics
 22. Inverted Register Statistics
 23. Multiplexer Restructuring Statistics (Restructuring Performed)
 24. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component
 25. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated
 26. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram
 27. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram|altsyncram_brg1:altsyncram4
 28. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp
 29. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp|dffpipe_hd9:dffpipe6
 30. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_hn7:wrempty_reg
 31. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_hn7:wrempty_reg|dffpipe_bo8:dffpipe9
 32. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp
 33. Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp|dffpipe_id9:dffpipe11
 34. Source assignments for system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated
 35. Source assignments for system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1
 36. Source assignments for system_0:u0|clock_0:the_clock_0
 37. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
 38. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
 39. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
 40. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
 41. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe
 42. Source assignments for system_0:u0|clock_1:the_clock_1
 43. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync
 44. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync
 45. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync
 46. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync
 47. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe
 48. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated
 49. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1
 50. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated
 51. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated
 52. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1
 53. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated
 54. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated
 55. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated
 56. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated
 57. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 58. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 59. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated
 60. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
 61. Source assignments for system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated
 62. Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 63. Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 64. Source assignments for system_0:u0|sdram_0:the_sdram_0
 65. Source assignments for system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
 66. Source assignments for system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch
 67. Source assignments for system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch
 68. Source assignments for sld_hub:sld_hub_inst
 69. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 70. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 71. Source assignments for I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_ocv:auto_generated
 72. Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component
 73. Parameter Settings for User Entity Instance: Audio_PLL:PLL2|altpll:altpll_component
 74. Parameter Settings for User Entity Instance: system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO
 75. Parameter Settings for User Entity Instance: system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component
 76. Parameter Settings for User Entity Instance: system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL
 77. Parameter Settings for User Entity Instance: system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0
 78. Parameter Settings for User Entity Instance: system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component
 79. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
 80. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
 81. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
 82. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
 83. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
 84. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram
 85. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
 86. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
 87. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
 88. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
 89. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag
 90. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram
 91. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data
 92. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram
 93. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1
 94. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2
 95. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
 96. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 97. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
 98. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 99. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
100. Parameter Settings for User Entity Instance: system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom
101. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
102. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
103. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
104. Parameter Settings for User Entity Instance: I2C_AV_Config:u1
105. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
106. Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u1|altsyncram:Ram0_rtl_0
107. dcfifo Parameter Settings by Entity Instance
108. scfifo Parameter Settings by Entity Instance
109. altmult_add Parameter Settings by Entity Instance
110. Analysis & Synthesis Messages
111. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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Altera or its authorized distributors.  Please refer to the 
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+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Jul 25 22:47:25 2006         ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE2_WEB                                       ;
; Top-level Entity Name              ; DE2_WEB                                       ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 5394                                          ;
; Total registers                    ; 3569                                          ;
; Total pins                         ; 429                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 387,584                                       ;
; Embedded Multiplier 9-bit elements ; 4                                             ;
; Total PLLs                         ; 2                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_WEB            ; DE2_WEB            ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                     ;
+-----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path  ; Used in Netlist ; File Type                        ; File Name with Absolute Path                                      ;
+-----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------------+
; Audio_0.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/Audio_0.v                                          ;
; AUDIO_DAC_FIFO.v                  ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/AUDIO_DAC_FIFO.v                                   ;
; Audio_PLL.v                       ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/Audio_PLL.v                                        ;
; button_pio.v                      ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/button_pio.v                                       ;
; cpu_0.v                           ; yes             ; Encrypted User Verilog HDL File  ; C:/DE2/DE2_WEB/cpu_0.v                                            ;
; cpu_0_jtag_debug_module.v         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/cpu_0_jtag_debug_module.v                          ;
; cpu_0_jtag_debug_module_wrapper.v ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/cpu_0_jtag_debug_module_wrapper.v                  ;
; cpu_0_mult_cell.v                 ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/cpu_0_mult_cell.v                                  ;
; cpu_0_test_bench.v                ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/cpu_0_test_bench.v                                 ;
; DE2_WEB.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/DE2_WEB.v                                          ;
; DM9000A.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/DM9000A.v                                          ;
; DM9000A_IF.v                      ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/DM9000A_IF.v                                       ;
; epcs_controller.v                 ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/epcs_controller.v                                  ;
; FIFO_16_256.v                     ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/FIFO_16_256.v                                      ;
; I2C_AV_Config.v                   ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/I2C_AV_Config.v                                    ;
; I2C_Controller.v                  ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/I2C_Controller.v                                   ;
; Img_RAM.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/Img_RAM.v                                          ;
; ISP1362.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/ISP1362.v                                          ;
; ISP1362_IF.v                      ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/ISP1362_IF.v                                       ;
; jtag_uart_0.v                     ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/jtag_uart_0.v                                      ;
; lcd_16207_0.v                     ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/lcd_16207_0.v                                      ;
; led_green.v                       ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/led_green.v                                        ;
; led_red.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/led_red.v                                          ;
; Reset_Delay.v                     ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/Reset_Delay.v                                      ;
; SD_CLK.v                          ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SD_CLK.v                                           ;
; SD_CMD.v                          ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SD_CMD.v                                           ;
; SD_DAT.v                          ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SD_DAT.v                                           ;
; sdram_0.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/sdram_0.v                                          ;
; SDRAM_PLL.v                       ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SDRAM_PLL.v                                        ;
; SEG7_Display.v                    ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SEG7_Display.v                                     ;
; SEG7_LUT.v                        ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SEG7_LUT.v                                         ;
; SEG7_LUT_8.v                      ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SEG7_LUT_8.v                                       ;
; sram_0.v                          ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/sram_0.v                                           ;
; SRAM_16Bit_512K.v                 ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/SRAM_16Bit_512K.v                                  ;
; switch_pio.v                      ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/switch_pio.v                                       ;
; system_0.v                        ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/system_0.v                                         ;
; timer_0.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/timer_0.v                                          ;
; timer_1.v                         ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/timer_1.v                                          ;
; uart_0.v                          ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/uart_0.v                                           ;
; VGA_0.v                           ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/VGA_0.v                                            ;
; VGA_Controller.v                  ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/VGA_Controller.v                                   ;
; VGA_NIOS_CTRL.v                   ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/VGA_NIOS_CTRL.v                                    ;
; VGA_OSD_RAM.v                     ; yes             ; User Verilog HDL File            ; C:/DE2/DE2_WEB/VGA_OSD_RAM.v                                      ;
; VGA_Param.h                       ; yes             ; Other                            ; C:/DE2/DE2_WEB/VGA_Param.h                                        ;
; altpll.tdf                        ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf            ;
; aglobal60.inc                     ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc         ;
; stratix_pll.inc                   ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc       ;
; stratixii_pll.inc                 ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc     ;
; cycloneii_pll.inc                 ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc     ;
; dcfifo.tdf                        ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/dcfifo.tdf            ;
; lpm_counter.inc                   ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_counter.inc       ;
; lpm_add_sub.inc                   ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.inc       ;
; altdpram.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altdpram.inc          ;
; a_graycounter.inc                 ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_graycounter.inc     ;
; a_fefifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_fefifo.inc          ;
; a_gray2bin.inc                    ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_gray2bin.inc        ;
; dffpipe.inc                       ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/dffpipe.inc           ;
; alt_sync_fifo.inc                 ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/alt_sync_fifo.inc     ;
; lpm_compare.inc                   ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_compare.inc       ;
; altsyncram_fifo.inc               ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altsyncram_fifo.inc   ;
; db/dcfifo_e6c1.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/dcfifo_e6c1.tdf                                 ;
; db/a_graycounter_g86.tdf          ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/a_graycounter_g86.tdf                           ;
; db/a_graycounter_b17.tdf          ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/a_graycounter_b17.tdf                           ;
; db/a_graycounter_a17.tdf          ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/a_graycounter_a17.tdf                           ;
; db/altsyncram_1731.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_1731.tdf                             ;
; db/altsyncram_brg1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_brg1.tdf                             ;
; db/alt_synch_pipe_nc8.tdf         ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/alt_synch_pipe_nc8.tdf                          ;
; db/dffpipe_hd9.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/dffpipe_hd9.tdf                                 ;
; db/alt_synch_pipe_hn7.tdf         ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/alt_synch_pipe_hn7.tdf                          ;
; db/dffpipe_bo8.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/dffpipe_bo8.tdf                                 ;
; db/alt_synch_pipe_oc8.tdf         ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/alt_synch_pipe_oc8.tdf                          ;
; db/dffpipe_id9.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/dffpipe_id9.tdf                                 ;
; altsyncram.tdf                    ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc             ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                       ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                    ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc        ;
; altsyncram.inc                    ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                     ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altrom.inc            ;
; altram.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altram.inc            ;
; altqpram.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_q7o1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_q7o1.tdf                             ;
; db/altsyncram_p132.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_p132.tdf                             ;
; db/decode_1qa.tdf                 ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/decode_1qa.tdf                                  ;
; db/mux_hkb.tdf                    ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/mux_hkb.tdf                                     ;
; db/mux_akb.tdf                    ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/mux_akb.tdf                                     ;
; clock_0.v                         ; yes             ; Other                            ; C:/DE2/DE2_WEB/clock_0.v                                          ;
; clock_1.v                         ; yes             ; Other                            ; C:/DE2/DE2_WEB/clock_1.v                                          ;
; db/altsyncram_cub1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_cub1.tdf                             ;
; db/altsyncram_k1l1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_k1l1.tdf                             ;
; db/altsyncram_tke1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_tke1.tdf                             ;
; db/altsyncram_q8e1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_q8e1.tdf                             ;
; db/altsyncram_pfn1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_pfn1.tdf                             ;
; db/altsyncram_4be1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_4be1.tdf                             ;
; db/altsyncram_5be1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_5be1.tdf                             ;
; db/altsyncram_vf22.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_vf22.tdf                             ;
; db/altsyncram_a422.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_a422.tdf                             ;
; altmult_add.tdf                   ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/altmult_add.tdf       ;
; stratix_mac_mult.inc              ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_mac_mult.inc  ;
; stratix_mac_out.inc               ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_mac_out.inc   ;
; db/mult_add_4cr2.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/mult_add_4cr2.tdf                               ;
; db/ded_mult_2o81.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/ded_mult_2o81.tdf                               ;
; db/dffpipe_93c.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/dffpipe_93c.tdf                                 ;
; db/mult_add_6cr2.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/mult_add_6cr2.tdf                               ;
; db/altsyncram_c572.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_c572.tdf                             ;
; db/altsyncram_e502.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_e502.tdf                             ;
; db/altsyncram_lo31.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_lo31.tdf                             ;
; scfifo.tdf                        ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/scfifo.tdf            ;
; a_regfifo.inc                     ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_regfifo.inc         ;
; a_dpfifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_dpfifo.inc          ;
; a_i2fifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_i2fifo.inc          ;
; a_fffifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_fffifo.inc          ;
; a_f2fifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_f2fifo.inc          ;
; db/scfifo_1n21.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/scfifo_1n21.tdf                                 ;
; db/a_dpfifo_8t21.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/a_dpfifo_8t21.tdf                               ;
; db/a_fefifo_7cf.tdf               ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/a_fefifo_7cf.tdf                                ;
; db/cntr_rj7.tdf                   ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/cntr_rj7.tdf                                    ;
; db/dpram_5h21.tdf                 ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/dpram_5h21.tdf                                  ;
; db/altsyncram_9tl1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_9tl1.tdf                             ;
; db/cntr_dl8.tdf                   ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/cntr_dl8.tdf                                    ;
; alt_jtag_atlantic.v               ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v   ;
; sld_hub.vhd                       ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd           ;
; lpm_shiftreg.tdf                  ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf      ;
; lpm_constant.inc                  ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_constant.inc      ;
; dffeea.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/dffeea.inc            ;
; lpm_decode.tdf                    ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.tdf        ;
; declut.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/declut.inc            ;
; altshift.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altshift.inc          ;
; db/decode_aoi.tdf                 ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/decode_aoi.tdf                                  ;
; sld_dffex.vhd                     ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd         ;
; sld_rom_sr.vhd                    ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd        ;
; db/altsyncram_ocv.tdf             ; yes             ; Auto-Generated Megafunction      ; C:/DE2/DE2_WEB/db/altsyncram_ocv.tdf                              ;
+-----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                ;
+---------------------------------------------+----------------------------------------------+
; Resource                                    ; Usage                                        ;
+---------------------------------------------+----------------------------------------------+
; Estimated Total logic elements              ; 5,394                                        ;
; Total combinational functions               ; 5394                                         ;
; Logic element usage by number of LUT inputs ;                                              ;
;     -- 4 input functions                    ; 3131                                         ;
;     -- 3 input functions                    ; 1393                                         ;
;     -- <=2 input functions                  ; 870                                          ;
;         -- Combinational cells for routing  ; 0                                            ;
; Logic elements by mode                      ;                                              ;
;     -- normal mode                          ; 4861                                         ;
;     -- arithmetic mode                      ; 533                                          ;
; Total registers                             ; 3569                                         ;
; I/O pins                                    ; 429                                          ;
; Total memory bits                           ; 387584                                       ;
; Embedded Multiplier 9-bit elements          ; 4                                            ;
; Total PLLs                                  ; 2                                            ;
; Maximum fan-out node                        ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 3126                                         ;
; Total fan-out                               ; 38961                                        ;
; Average fan-out                             ; 4.00                                         ;
+---------------------------------------------+----------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                                                      ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |DE2_WEB                                                                                        ; 5394 (1)          ; 3569 (0)     ; 387584      ; 91   ; 4            ; 0       ; 2         ; 429  ; 0            ; |DE2_WEB                                                                                                                                                                                                                                                   ;
;    |Audio_PLL:PLL2|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|Audio_PLL:PLL2                                                                                                                                                                                                                                    ;
;       |altpll:altpll_component|                                                                 ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|Audio_PLL:PLL2|altpll:altpll_component                                                                                                                                                                                                            ;
;    |I2C_AV_Config:u1|                                                                           ; 87 (39)           ; 57 (28)      ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|I2C_AV_Config:u1                                                                                                                                                                                                                                  ;
;       |I2C_Controller:u0|                                                                       ; 48 (48)           ; 29 (29)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|I2C_AV_Config:u1|I2C_Controller:u0                                                                                                                                                                                                                ;
;       |altsyncram:Ram0_rtl_0|                                                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|I2C_AV_Config:u1|altsyncram:Ram0_rtl_0                                                                                                                                                                                                            ;
;          |altsyncram_ocv:auto_generated|                                                        ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_ocv:auto_generated                                                                                                                                                                              ;
;    |Reset_Delay:delay1|                                                                         ; 33 (33)           ; 25 (25)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|Reset_Delay:delay1                                                                                                                                                                                                                                ;
;    |SDRAM_PLL:PLL1|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|SDRAM_PLL:PLL1                                                                                                                                                                                                                                    ;
;       |altpll:altpll_component|                                                                 ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|SDRAM_PLL:PLL1|altpll:altpll_component                                                                                                                                                                                                            ;
;    |sld_hub:sld_hub_inst|                                                                       ; 92 (37)           ; 68 (7)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst                                                                                                                                                                                                                              ;
;       |lpm_decode:instruction_decoder|                                                          ; 5 (0)             ; 5 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                                               ;
;          |decode_aoi:auto_generated|                                                            ; 5 (5)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated                                                                                                                                                                     ;
;       |lpm_shiftreg:jtag_ir_register|                                                           ; 0 (0)             ; 10 (10)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                                                ;
;       |sld_dffex:BROADCAST|                                                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                                          ;
;       |sld_dffex:IRF_ENA_0|                                                                     ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                                          ;
;       |sld_dffex:IRF_ENA|                                                                       ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                                            ;
;       |sld_dffex:IRSR|                                                                          ; 4 (4)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                                               ;
;       |sld_dffex:RESET|                                                                         ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                                              ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                                ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                                     ;
;       |sld_dffex:\GEN_IRF:2:IRF|                                                                ; 2 (2)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF                                                                                                                                                                                                     ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                                       ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                                            ;
;       |sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF                                                                                                                                                                                            ;
;       |sld_jtag_state_machine:jtag_state_machine|                                               ; 19 (19)           ; 19 (19)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                                    ;
;       |sld_rom_sr:HUB_INFO_REG|                                                                 ; 22 (22)           ; 9 (9)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                                                                                                                      ;
;    |system_0:u0|                                                                                ; 5181 (1)          ; 3419 (0)     ; 386560      ; 91   ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_WEB|system_0:u0                                                                                                                                                                                                                                       ;
;       |Audio_0:the_Audio_0|                                                                     ; 82 (0)            ; 135 (0)      ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0                                                                                                                                                                                                                   ;
;          |AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|                                                    ; 82 (46)           ; 135 (59)     ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO                                                                                                                                                                                 ;
;             |FIFO_16_256:u0|                                                                    ; 36 (0)            ; 76 (0)       ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0                                                                                                                                                                  ;
;                |dcfifo:dcfifo_component|                                                        ; 36 (0)            ; 76 (0)       ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component                                                                                                                                          ;
;                   |dcfifo_e6c1:auto_generated|                                                  ; 36 (16)           ; 76 (20)      ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated                                                                                                               ;
;                      |a_graycounter_a17:wrptr_gp|                                               ; 10 (10)           ; 10 (10)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|a_graycounter_a17:wrptr_gp                                                                                    ;
;                      |a_graycounter_g86:rdptr_g1p|                                              ; 10 (10)           ; 10 (10)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|a_graycounter_g86:rdptr_g1p                                                                                   ;
;                      |alt_synch_pipe_nc8:rs_dgwp|                                               ; 0 (0)             ; 18 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp                                                                                    ;
;                         |dffpipe_hd9:dffpipe6|                                                  ; 0 (0)             ; 18 (18)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp|dffpipe_hd9:dffpipe6                                                               ;
;                      |alt_synch_pipe_oc8:ws_dgrp|                                               ; 0 (0)             ; 18 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp                                                                                    ;
;                         |dffpipe_id9:dffpipe11|                                                 ; 0 (0)             ; 18 (18)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp|dffpipe_id9:dffpipe11                                                              ;
;                      |altsyncram_1731:fifo_ram|                                                 ; 0 (0)             ; 0 (0)        ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram                                                                                      ;
;                         |altsyncram_brg1:altsyncram4|                                           ; 0 (0)             ; 0 (0)        ; 4096        ; 16   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram|altsyncram_brg1:altsyncram4                                                          ;
;       |Audio_0_avalon_slave_0_arbitrator:the_Audio_0_avalon_slave_0|                            ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|Audio_0_avalon_slave_0_arbitrator:the_Audio_0_avalon_slave_0                                                                                                                                                                          ;
;       |DM9000A:the_DM9000A|                                                                     ; 1 (0)             ; 21 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|DM9000A:the_DM9000A                                                                                                                                                                                                                   ;
;          |DM9000A_IF:the_DM9000A_IF|                                                            ; 1 (1)             ; 21 (21)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF                                                                                                                                                                                         ;
;       |DM9000A_avalon_slave_0_arbitrator:the_DM9000A_avalon_slave_0|                            ; 7 (7)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|DM9000A_avalon_slave_0_arbitrator:the_DM9000A_avalon_slave_0                                                                                                                                                                          ;
;       |ISP1362:the_ISP1362|                                                                     ; 2 (0)             ; 37 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|ISP1362:the_ISP1362                                                                                                                                                                                                                   ;
;          |ISP1362_IF:the_ISP1362_IF|                                                            ; 2 (2)             ; 37 (37)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF                                                                                                                                                                                         ;
;       |ISP1362_avalon_slave_0_arbitrator:the_ISP1362_avalon_slave_0|                            ; 21 (21)           ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|ISP1362_avalon_slave_0_arbitrator:the_ISP1362_avalon_slave_0                                                                                                                                                                          ;
;       |SD_CLK:the_SD_CLK|                                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SD_CLK:the_SD_CLK                                                                                                                                                                                                                     ;
;       |SD_CMD:the_SD_CMD|                                                                       ; 4 (4)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SD_CMD:the_SD_CMD                                                                                                                                                                                                                     ;
;       |SD_CMD_s1_arbitrator:the_SD_CMD_s1|                                                      ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SD_CMD_s1_arbitrator:the_SD_CMD_s1                                                                                                                                                                                                    ;
;       |SD_DAT:the_SD_DAT|                                                                       ; 4 (4)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SD_DAT:the_SD_DAT                                                                                                                                                                                                                     ;
;       |SEG7_Display:the_SEG7_Display|                                                           ; 56 (0)            ; 32 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display                                                                                                                                                                                                         ;
;          |SEG7_LUT_8:the_SEG7_LUT_8|                                                            ; 56 (0)            ; 32 (32)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8                                                                                                                                                                               ;
;             |SEG7_LUT:u0|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u0                                                                                                                                                                   ;
;             |SEG7_LUT:u1|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u1                                                                                                                                                                   ;
;             |SEG7_LUT:u2|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u2                                                                                                                                                                   ;
;             |SEG7_LUT:u3|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u3                                                                                                                                                                   ;
;             |SEG7_LUT:u4|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u4                                                                                                                                                                   ;
;             |SEG7_LUT:u5|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u5                                                                                                                                                                   ;
;             |SEG7_LUT:u6|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u6                                                                                                                                                                   ;
;             |SEG7_LUT:u7|                                                                       ; 7 (7)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u7                                                                                                                                                                   ;
;       |SEG7_Display_avalon_slave_0_arbitrator:the_SEG7_Display_avalon_slave_0|                  ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|SEG7_Display_avalon_slave_0_arbitrator:the_SEG7_Display_avalon_slave_0                                                                                                                                                                ;
;       |VGA_0:the_VGA_0|                                                                         ; 1122 (0)          ; 265 (0)      ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0                                                                                                                                                                                                                       ;
;          |VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|                                                      ; 1122 (108)        ; 265 (124)    ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL                                                                                                                                                                                       ;
;             |VGA_Controller:u0|                                                                 ; 274 (274)         ; 91 (91)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0                                                                                                                                                                     ;
;             |VGA_OSD_RAM:u1|                                                                    ; 740 (38)          ; 50 (36)      ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1                                                                                                                                                                        ;
;                |Img_RAM:u0|                                                                     ; 702 (0)           ; 14 (0)       ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0                                                                                                                                                             ;
;                   |altsyncram:altsyncram_component|                                             ; 702 (0)           ; 14 (0)       ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component                                                                                                                             ;
;                      |altsyncram_q7o1:auto_generated|                                           ; 702 (0)           ; 14 (0)       ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated                                                                                              ;
;                         |altsyncram_p132:altsyncram1|                                           ; 702 (0)           ; 14 (14)      ; 307200      ; 75   ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1                                                                  ;
;                            |decode_1qa:decode4|                                                 ; 88 (88)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode4                                               ;
;                            |decode_1qa:decode_a|                                                ; 87 (87)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode_a                                              ;
;                            |decode_1qa:decode_b|                                                ; 85 (85)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode_b                                              ;
;                            |mux_hkb:mux5|                                                       ; 442 (442)         ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|mux_hkb:mux5                                                     ;
;       |VGA_0_avalon_slave_0_arbitrator:the_VGA_0_avalon_slave_0|                                ; 3 (3)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|VGA_0_avalon_slave_0_arbitrator:the_VGA_0_avalon_slave_0                                                                                                                                                                              ;
;       |button_pio:the_button_pio|                                                               ; 14 (14)           ; 20 (20)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|button_pio:the_button_pio                                                                                                                                                                                                             ;
;       |button_pio_s1_arbitrator:the_button_pio_s1|                                              ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|button_pio_s1_arbitrator:the_button_pio_s1                                                                                                                                                                                            ;
;       |clock_0:the_clock_0|                                                                     ; 33 (17)           ; 130 (112)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0                                                                                                                                                                                                                   ;
;          |clock_0_edge_to_pulse:read_done_edge_to_pulse|                                        ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                                     ;
;          |clock_0_edge_to_pulse:read_request_edge_to_pulse|                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                                  ;
;          |clock_0_edge_to_pulse:write_request_edge_to_pulse|                                    ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                                 ;
;          |clock_0_master_FSM:master_FSM|                                                        ; 8 (8)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM                                                                                                                                                                                     ;
;          |clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|                   ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync                                                                                                                                                ;
;          |clock_0_slave_FSM:slave_FSM|                                                          ; 5 (5)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM                                                                                                                                                                                       ;
;          |clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|               ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync                                                                                                                                            ;
;          |clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|             ; 1 (1)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync                                                                                                                                          ;
;       |clock_0_out_arbitrator:the_clock_0_out|                                                  ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_0_out_arbitrator:the_clock_0_out                                                                                                                                                                                                ;
;       |clock_1:the_clock_1|                                                                     ; 23 (1)            ; 136 (112)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1                                                                                                                                                                                                                   ;
;          |clock_1_edge_to_pulse:read_done_edge_to_pulse|                                        ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                                     ;
;          |clock_1_edge_to_pulse:read_request_edge_to_pulse|                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                                  ;
;          |clock_1_edge_to_pulse:write_done_edge_to_pulse|                                       ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                                                    ;
;          |clock_1_edge_to_pulse:write_request_edge_to_pulse|                                    ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                                 ;
;          |clock_1_master_FSM:master_FSM|                                                        ; 9 (9)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM                                                                                                                                                                                     ;
;          |clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|                   ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync                                                                                                                                                ;
;          |clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|                 ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync                                                                                                                                              ;
;          |clock_1_slave_FSM:slave_FSM|                                                          ; 10 (10)           ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM                                                                                                                                                                                       ;
;          |clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|               ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync                                                                                                                                            ;
;          |clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|             ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync                                                                                                                                          ;
;       |clock_1_in_arbitrator:the_clock_1_in|                                                    ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1_in_arbitrator:the_clock_1_in                                                                                                                                                                                                  ;
;       |clock_1_out_arbitrator:the_clock_1_out|                                                  ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|clock_1_out_arbitrator:the_clock_1_out                                                                                                                                                                                                ;
;       |cpu_0:the_cpu_0|                                                                         ; 1945 (1704)       ; 1533 (1350)  ; 70144       ; 0    ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0                                                                                                                                                                                                                       ;
;          |cpu_0_bht_module:cpu_0_bht|                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht                                                                                                                                                                                            ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram                                                                                                                                                                  ;
;                |altsyncram_q8e1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated                                                                                                                                   ;
;                   |altsyncram_pfn1:altsyncram1|                                                 ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1                                                                                                       ;
;          |cpu_0_dc_data_module:cpu_0_dc_data|                                                   ; 0 (0)             ; 0 (0)        ; 16384       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data                                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 16384       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram                                                                                                                                                          ;
;                |altsyncram_a422:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 16384       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated                                                                                                                           ;
;          |cpu_0_dc_tag_module:cpu_0_dc_tag|                                                     ; 0 (0)             ; 0 (0)        ; 7680        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag                                                                                                                                                                                      ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 7680        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram                                                                                                                                                            ;
;                |altsyncram_vf22:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 7680        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated                                                                                                                             ;
;          |cpu_0_ic_data_module:cpu_0_ic_data|                                                   ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data                                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram                                                                                                                                                          ;
;                |altsyncram_cub1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated                                                                                                                           ;
;                   |altsyncram_k1l1:altsyncram1|                                                 ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1                                                                                               ;
;          |cpu_0_ic_tag_module:cpu_0_ic_tag|                                                     ; 0 (0)             ; 0 (0)        ; 2560        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag                                                                                                                                                                                      ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 2560        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram                                                                                                                                                            ;
;                |altsyncram_tke1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 2560        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated                                                                                                                             ;
;          |cpu_0_mult_cell:the_cpu_0_mult_cell|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell                                                                                                                                                                                   ;
;             |altmult_add:the_altmult_add_part_1|                                                ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1                                                                                                                                                ;
;                |mult_add_4cr2:auto_generated|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated                                                                                                                   ;
;                   |ded_mult_2o81:ded_mult1|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1                                                                                           ;
;             |altmult_add:the_altmult_add_part_2|                                                ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2                                                                                                                                                ;
;                |mult_add_6cr2:auto_generated|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated                                                                                                                   ;
;                   |ded_mult_2o81:ded_mult1|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1                                                                                           ;
;          |cpu_0_nios2_oci:the_cpu_0_nios2_oci|                                                  ; 230 (12)          ; 183 (0)      ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci                                                                                                                                                                                   ;
;             |cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|               ; 107 (0)           ; 90 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper                                                                                                               ;
;                |cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|                           ; 107 (107)         ; 90 (90)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1                                                          ;
;             |cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|                                 ; 14 (14)           ; 10 (10)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg                                                                                                                                 ;
;             |cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|                                   ; 33 (33)           ; 32 (32)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break                                                                                                                                   ;
;             |cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|                                   ; 11 (11)           ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug                                                                                                                                   ;
;             |cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|                                         ; 53 (53)           ; 44 (44)      ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem                                                                                                                                         ;
;                |cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component| ; 0 (0)             ; 0 (0)        ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component                                                          ;
;                   |altsyncram:the_altsyncram|                                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                ;
;                      |altsyncram_c572:auto_generated|                                           ; 0 (0)             ; 0 (0)        ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated ;
;          |cpu_0_register_bank_a_module:cpu_0_register_bank_a|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram                                                                                                                                          ;
;                |altsyncram_4be1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated                                                                                                           ;
;          |cpu_0_register_bank_b_module:cpu_0_register_bank_b|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram                                                                                                                                          ;
;                |altsyncram_5be1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated                                                                                                           ;
;          |cpu_0_test_bench:the_cpu_0_test_bench|                                                ; 11 (11)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench                                                                                                                                                                                 ;
;       |cpu_0_data_master_arbitrator:the_cpu_0_data_master|                                      ; 408 (408)         ; 76 (76)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master                                                                                                                                                                                    ;
;       |cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|                        ; 185 (185)         ; 47 (47)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master                                                                                                                                                                      ;
;       |cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|                          ; 24 (24)           ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module                                                                                                                                                                        ;
;       |epcs_controller:the_epcs_controller|                                                     ; 125 (15)          ; 116 (0)      ; 4096        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller                                                                                                                                                                                                   ;
;          |altsyncram:the_boot_copier_rom|                                                       ; 0 (0)             ; 0 (0)        ; 4096        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom                                                                                                                                                                    ;
;             |altsyncram_lo31:auto_generated|                                                    ; 0 (0)             ; 0 (0)        ; 4096        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated                                                                                                                                     ;
;          |epcs_controller_sub:the_epcs_controller_sub|                                          ; 110 (110)         ; 116 (116)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub                                                                                                                                                       ;
;          |tornado_epcs_controller_atom:the_tornado_epcs_controller_atom|                        ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom                                                                                                                                     ;
;       |epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|      ; 33 (33)           ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port                                                                                                                                                    ;
;       |jtag_uart_0:the_jtag_uart_0|                                                             ; 130 (35)          ; 106 (13)     ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0                                                                                                                                                                                                           ;
;          |alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|                                      ; 44 (44)           ; 53 (53)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic                                                                                                                                                           ;
;          |jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|                                        ; 26 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r                                                                                                                                                             ;
;             |scfifo:rfifo|                                                                      ; 26 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo                                                                                                                                                ;
;                |scfifo_1n21:auto_generated|                                                     ; 26 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated                                                                                                                     ;
;                   |a_dpfifo_8t21:dpfifo|                                                        ; 26 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo                                                                                                ;
;                      |a_fefifo_7cf:fifo_state|                                                  ; 14 (8)            ; 8 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state                                                                        ;
;                         |cntr_rj7:count_usedw|                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw                                                   ;
;                      |cntr_dl8:rd_ptr_count|                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count                                                                          ;
;                      |cntr_dl8:wr_ptr|                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:wr_ptr                                                                                ;
;                      |dpram_5h21:FIFOram|                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram                                                                             ;
;                         |altsyncram_9tl1:altsyncram2|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2                                                 ;
;          |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w                                                                                                                                                             ;
;             |scfifo:wfifo|                                                                      ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo                                                                                                                                                ;
;                |scfifo_1n21:auto_generated|                                                     ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated                                                                                                                     ;
;                   |a_dpfifo_8t21:dpfifo|                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo                                                                                                ;
;                      |a_fefifo_7cf:fifo_state|                                                  ; 13 (7)            ; 8 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state                                                                        ;
;                         |cntr_rj7:count_usedw|                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw                                                   ;
;                      |cntr_dl8:rd_ptr_count|                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count                                                                          ;
;                      |cntr_dl8:wr_ptr|                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:wr_ptr                                                                                ;
;                      |dpram_5h21:FIFOram|                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram                                                                             ;
;                         |altsyncram_9tl1:altsyncram2|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2                                                 ;
;       |jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|              ; 4 (4)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave                                                                                                                                                            ;
;       |lcd_16207_0:the_lcd_16207_0|                                                             ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|lcd_16207_0:the_lcd_16207_0                                                                                                                                                                                                           ;
;       |lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave|                      ; 23 (23)           ; 8 (8)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave                                                                                                                                                                    ;
;       |led_green:the_led_green|                                                                 ; 2 (2)             ; 9 (9)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|led_green:the_led_green                                                                                                                                                                                                               ;
;       |led_red:the_led_red|                                                                     ; 2 (2)             ; 18 (18)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|led_red:the_led_red                                                                                                                                                                                                                   ;
;       |sdram_0:the_sdram_0|                                                                     ; 261 (211)         ; 238 (152)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0                                                                                                                                                                                                                   ;
;          |sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|                            ; 50 (50)           ; 86 (86)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module                                                                                                                                                         ;
;       |sdram_0_s1_arbitrator:the_sdram_0_s1|                                                    ; 102 (52)          ; 34 (3)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1                                                                                                                                                                                                  ;
;          |rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1| ; 25 (25)           ; 12 (12)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1                                                                                                             ;
;          |rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1| ; 25 (25)           ; 19 (19)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1                                                                                                             ;
;       |sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|                              ; 75 (75)           ; 14 (14)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0                                                                                                                                                                            ;
;       |switch_pio:the_switch_pio|                                                               ; 18 (18)           ; 18 (18)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|switch_pio:the_switch_pio                                                                                                                                                                                                             ;
;       |switch_pio_s1_arbitrator:the_switch_pio_s1|                                              ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|switch_pio_s1_arbitrator:the_switch_pio_s1                                                                                                                                                                                            ;
;       |system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|            ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch                                                                                                                                                          ;
;       |system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|                  ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch                                                                                                                                                                ;
;       |timer_0:the_timer_0|                                                                     ; 117 (117)         ; 120 (120)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|timer_0:the_timer_0                                                                                                                                                                                                                   ;
;       |timer_0_s1_arbitrator:the_timer_0_s1|                                                    ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|timer_0_s1_arbitrator:the_timer_0_s1                                                                                                                                                                                                  ;
;       |timer_1:the_timer_1|                                                                     ; 115 (115)         ; 120 (120)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|timer_1:the_timer_1                                                                                                                                                                                                                   ;
;       |timer_1_s1_arbitrator:the_timer_1_s1|                                                    ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|timer_1_s1_arbitrator:the_timer_1_s1                                                                                                                                                                                                  ;
;       |tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|          ; 81 (81)           ; 62 (62)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave                                                                                                                                                        ;
;       |uart_0:the_uart_0|                                                                       ; 122 (0)           ; 94 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|uart_0:the_uart_0                                                                                                                                                                                                                     ;
;          |uart_0_regs:the_uart_0_regs|                                                          ; 41 (41)           ; 29 (29)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs                                                                                                                                                                                         ;
;          |uart_0_rx:the_uart_0_rx|                                                              ; 46 (46)           ; 38 (38)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx                                                                                                                                                                                             ;
;          |uart_0_tx:the_uart_0_tx|                                                              ; 35 (35)           ; 27 (27)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx                                                                                                                                                                                             ;
;       |uart_0_s1_arbitrator:the_uart_0_s1|                                                      ; 7 (7)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_WEB|system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                                                ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------------------------+
; Name                                                                                                                                                                                                                                                         ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                               ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------------------------+
; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_ocv:auto_generated|ALTSYNCRAM                                                                                                                                                                              ; AUTO ; ROM              ; 64           ; 16           ; --           ; --           ; 1024   ; DE2_WEB0.rtl.mif                  ;
; system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram|altsyncram_brg1:altsyncram4|ALTSYNCRAM                                                          ; M4K  ; True Dual Port   ; 256          ; 16           ; 256          ; 16           ; 4096   ; None                              ;
; system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|ALTSYNCRAM                                                                  ; M4K  ; True Dual Port   ; 38400        ; 8            ; 307200       ; 1            ; 307200 ; Img_DATA.hex                      ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1|ALTSYNCRAM                                                                                                       ; AUTO ; True Dual Port   ; 256          ; 2            ; 256          ; 2            ; 512    ; cpu_0_bht_ram.mif                 ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; True Dual Port   ; 512          ; 32           ; 512          ; 32           ; 16384  ; None                              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated|ALTSYNCRAM                                                                                                                             ; AUTO ; True Dual Port   ; 512          ; 15           ; 512          ; 15           ; 7680   ; cpu_0_dc_tag_ram.mif              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1|ALTSYNCRAM                                                                                               ; AUTO ; True Dual Port   ; 1024         ; 32           ; 1024         ; 32           ; 32768  ; None                              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated|ALTSYNCRAM                                                                                                                             ; AUTO ; Simple Dual Port ; 128          ; 20           ; 128          ; 20           ; 2560   ; cpu_0_ic_tag_ram.mif              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192   ; cpu_0_ociram_default_contents.mif ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_0_rf_ram_a.mif                ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024   ; cpu_0_rf_ram_b.mif                ;
; system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated|ALTSYNCRAM                                                                                                                                     ; AUTO ; ROM              ; 128          ; 32           ; --           ; --           ; 4096   ; epcs_controller_boot_rom.hex      ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM                                                 ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512    ; None                              ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM                                                 ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512    ; None                              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 2           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 4           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 2           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+-------------------------------------------------------------------+
; State Machine - |DE2_WEB|I2C_AV_Config:u1|mSetup_ST               ;
+----------------+----------------+----------------+----------------+
; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ;
+----------------+----------------+----------------+----------------+
; mSetup_ST.0000 ; 0              ; 0              ; 0              ;
; mSetup_ST.0001 ; 1              ; 0              ; 1              ;
; mSetup_ST.0010 ; 1              ; 1              ; 0              ;
+----------------+----------------+----------------+----------------+


+-------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state                                ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; i_state.101 ; i_state.111 ; i_state.001 ; i_state.011 ; i_state.010 ; i_state.000 ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; i_state.000 ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ;
; i_state.010 ; 0           ; 0           ; 0           ; 0           ; 1           ; 1           ;
; i_state.011 ; 0           ; 0           ; 0           ; 1           ; 0           ; 1           ;
; i_state.001 ; 0           ; 0           ; 1           ; 0           ; 0           ; 1           ;
; i_state.111 ; 0           ; 1           ; 0           ; 0           ; 0           ; 1           ;
; i_state.101 ; 1           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


+-----------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next ;
+------------+------------+------------+------------+-------------+
; Name       ; i_next.101 ; i_next.010 ; i_next.111 ; i_next.000  ;
+------------+------------+------------+------------+-------------+
; i_next.000 ; 0          ; 0          ; 0          ; 0           ;
; i_next.111 ; 0          ; 0          ; 1          ; 1           ;
; i_next.010 ; 0          ; 1          ; 0          ; 1           ;
; i_next.101 ; 1          ; 0          ; 0          ; 1           ;
+------------+------------+------------+------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state                                                                                                                                      ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; m_state.000000001 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; m_state.000100000 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000010000 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000001000 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; m_state.100000000 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000000100 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; m_state.000000010 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; m_state.001000000 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.010000000 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+----------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next                              ;
+------------------+------------------+------------------+------------------+------------------+
; Name             ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ;
+------------------+------------------+------------------+------------------+------------------+
; m_next.000000001 ; 0                ; 0                ; 0                ; 0                ;
; m_next.000001000 ; 0                ; 0                ; 1                ; 1                ;
; m_next.010000000 ; 1                ; 0                ; 0                ; 1                ;
; m_next.000010000 ; 0                ; 1                ; 0                ; 1                ;
+------------------+------------------+------------------+------------------+------------------+


+-----------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                           ;
+------------------+------------------+------------------+--------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                          ;
; master_state.100 ; 1                ; 0                ; 1                                          ;
; master_state.010 ; 0                ; 1                ; 1                                          ;
+------------------+------------------+------------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                            ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                          ;
; slave_state.010 ; 0               ; 1               ; 1                                          ;
; slave_state.100 ; 1               ; 0               ; 1                                          ;
+-----------------+-----------------+-----------------+--------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                           ;
+------------------+------------------+------------------+--------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                          ;
; master_state.100 ; 1                ; 0                ; 1                                          ;
; master_state.010 ; 0                ; 1                ; 1                                          ;
+------------------+------------------+------------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                            ;
+-----------------+-----------------+-----------------+--------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                          ;
; slave_state.010 ; 0               ; 1               ; 1                                          ;
; slave_state.100 ; 1               ; 0               ; 1                                          ;
+-----------------+-----------------+-----------------+--------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.011 ; DRsize.100 ; DRsize.101 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                                 ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                                          ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                                          ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                                          ;
; DRsize.101 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                                          ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                                          ;
; DRsize.011 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                                          ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                       ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+---------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; system_0:u0|clock_1:the_clock_1|slave_address_d1[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out                         ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_out                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out         ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_out       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_out         ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_in_d1                       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[9]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[9]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[22]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[22]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[10]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[10]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[11]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[11]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[12]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[12]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[13]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[13]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[14]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[14]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[15]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[15]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[16]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[16]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[17]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[17]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[18]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[18]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[19]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[19]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[20]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[20]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[21]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[21]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[1]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[1]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_in_d1                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[2]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[2]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[3]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[3]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[4]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[4]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[5]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[5]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[6]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[6]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[7]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[7]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[8]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[8]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_byteenable[0]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_byteenable[0]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_byteenable[1]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_byteenable[1]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1     ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out     ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_out     ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_out   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[22]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[22]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[16]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[16]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[17]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[17]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[18]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[18]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[19]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[19]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[20]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[20]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[21]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[21]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_byteenable_d1[0]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[0]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_byteenable_d1[1]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[1]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_in_d1   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_in_d1 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[0]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[0]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[0]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[0]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[1]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[1]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[2]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[2]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[3]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[3]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[4]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[4]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[5]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[5]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[6]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[6]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[7]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[7]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[8]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[8]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[9]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[9]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[10]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[10]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[11]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[11]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[12]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[12]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[13]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[13]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[14]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[14]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[15]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[15]                                                              ; yes                                                              ; yes                                        ;
+---------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+-------------------------------------------------------------+
; Logic Cells Representing Combinational Loops                ;
+--------------------------------------------------------+----+
; Logic Cell Name                                        ;    ;
+--------------------------------------------------------+----+
; rtl~0                                                  ;    ;
; rtl~1                                                  ;    ;
; rtl~2                                                  ;    ;
; rtl~3                                                  ;    ;
; rtl~4                                                  ;    ;
; rtl~5                                                  ;    ;
; rtl~6                                                  ;    ;
; rtl~7                                                  ;    ;
; rtl~8                                                  ;    ;
; rtl~9                                                  ;    ;
; Number of logic cells representing combinational loops ; 10 ;
+--------------------------------------------------------+----+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3569  ;
; Number of registers using Synchronous Clear  ; 112   ;
; Number of registers using Synchronous Load   ; 329   ;
; Number of registers using Asynchronous Clear ; 3316  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2250  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                          ; Fan out ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|txd                                                                                                  ; 1       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[0]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[1]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[2]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[3]                                                                                                                   ; 1       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0                                      ; 1       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn                                        ; 1       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0                                     ; 1       ;
; system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_arb_addend[0]                                                 ; 6       ;
; system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|OTG_CS_N                                                                                         ; 1       ;
; system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|OTG_RD_N                                                                                         ; 1       ;
; system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|OTG_WR_N                                                                                         ; 17      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0]                                                                                                           ; 19      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2]                                                                                                           ; 15      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3]                                                                                                           ; 21      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1]                                                                                                           ; 16      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4]                                                                                                           ; 11      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5]                                                                                                           ; 12      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SCLK                                                                                                                    ; 2       ;
; system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|ENET_CS_N                                                                                        ; 1       ;
; system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|ENET_WR_N                                                                                        ; 17      ;
; system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|ENET_RD_N                                                                                        ; 1       ;
; system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest                                                               ; 21      ;
; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|pre_txd                                                                                              ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_addr[11]                                                                                                                 ; 10      ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[0]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[1]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[2]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[3]                                                                                                                   ; 2       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]                   ; 6       ;
; system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_addend[0]             ; 5       ;
; system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]                                           ; 5       ;
; system_0:u0|cpu_0:the_cpu_0|M_pipe_flush                                                                                                                   ; 40      ;
; sld_hub:sld_hub_inst|hub_tdo                                                                                                                               ; 2       ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|av_waitrequest                                                                                                     ; 1       ;
; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|fifo_contains_ones_n ; 3       ;
; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|fifo_contains_ones_n ; 3       ;
; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0]                                                                                  ; 5       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[3]                                                                                                         ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[12]                                                                                                        ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[9]                                                                                                         ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[8]                                                                                                         ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[7]                                                                                                         ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|hbreak_enabled                                                                                                                 ; 12      ;
; I2C_AV_Config:u1|I2C_Controller:u0|END                                                                                                                     ; 5       ;
; I2C_AV_Config:u1|I2C_Controller:u0|SDO                                                                                                                     ; 4       ;
; system_0:u0|cpu_0:the_cpu_0|ic_tag_clr_valid_bits                                                                                                          ; 1       ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9]                                                           ; 11      ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|t_dav                                                                                                              ; 3       ;
; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_ready                                                                                             ; 6       ;
; system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|oINT1_N                                                                                          ; 1       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]                           ; 2       ;
; system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|oINT0_N                                                                                          ; 1       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|A_wr_dst_reg_from_M                                                                                                            ; 66      ;
; system_0:u0|timer_1:the_timer_1|internal_counter[0]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[1]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[2]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[3]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[4]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[7]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[9]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[10]                                                                                                       ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[15]                                                                                                       ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[16]                                                                                                       ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[0]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[1]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[2]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[3]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[4]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[7]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[9]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[10]                                                                                                       ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[15]                                                                                                       ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[16]                                                                                                       ; 3       ;
; system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|tx_shift_empty                                                                                       ; 2       ;
; system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|epcs_slave_select_reg[0]                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_h_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_h_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[1]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[1]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[2]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[2]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[3]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[3]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[4]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[4]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[7]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[7]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[9]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[9]                                                                                                       ; 2       ;
; Total number of inverted registers = 106*                                                                                                                  ;         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
*Too many items, table truncated at 100 items.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 30 bits   ; 60 LEs        ; 30 LEs               ; 30 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|Cur_Color_R[4]                                                                                                    ;
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[3]                                                                                                                                                 ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]                                                                            ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[3]                                                                                                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|D_iw[21]                                                                                                                                                            ;
; 3:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|D_iw[9]                                                                                                                                                             ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|M_st_data[21]                                                                                                                                                       ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|M_st_data[29]                                                                                                                                                       ;
; 3:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|A_inst_result[7]                                                                                                                                                    ;
; 3:1                ; 23 bits   ; 46 LEs        ; 46 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|A_inst_result[24]                                                                                                                                                   ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]                                                                                    ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[1]                                                                                                                                                   ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[2]                                                                                                                                                ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[1]                                                                                            ;
; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[25]                                                                           ;
; 4:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[8]                                                                            ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[9]                                                                            ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_WEB|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]                                                                                                                                                        ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_src2[11]                                                                                                                                                          ;
; 8:1                ; 8 bits    ; 40 LEs        ; 16 LEs               ; 24 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[3]                                                                                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|shift_reg[7]                                                                                        ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1]                                                                       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3]                                                                       ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_wait_counter[0]                                                                                    ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave|lcd_16207_0_control_slave_wait_counter[5]                                                                        ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave|lcd_16207_0_control_slave_wait_counter[6]                                                                        ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|ISP1362_avalon_slave_0_arbitrator:the_ISP1362_avalon_slave_0|ISP1362_avalon_slave_0_wait_counter[3]                                                                                 ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|ISP1362_avalon_slave_0_arbitrator:the_ISP1362_avalon_slave_0|ISP1362_avalon_slave_0_wait_counter[4]                                                                                 ;
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[3]                                                                ;
; 5:1                ; 22 bits   ; 66 LEs        ; 66 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[18]                                                                                                                                              ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[3]                                                                                                                                                    ;
; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_src2[17]                                                                                                                                                          ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_src1[17]                                                                                                                                                          ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |DE2_WEB|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]                                                                                                                                    ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[12]                                                                                     ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[8]                                                                                      ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[0]                                                                                      ;
; 5:1                ; 4 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub|data_to_cpu[7]                                                                                      ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_bank[0]                                                                                                                                                       ;
; 6:1                ; 12 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|F_pc[10]                                                                                                                                                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_count[1]                                                                                                                                                      ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_addr[9]                                                                                                                                                       ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_addr[5]                                                                                                                                                       ;
; 7:1                ; 6 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_addr[6]                                                                                                                                                       ;
; 28:1               ; 4 bits    ; 72 LEs        ; 48 LEs               ; 24 LEs                 ; Yes        ; |DE2_WEB|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                                         ;
; 12:1               ; 41 bits   ; 328 LEs       ; 0 LEs                ; 328 LEs                ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|active_addr[21]                                                                                                                                                 ;
; 13:1               ; 6 bits    ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[8]                                                                                                                            ;
; 13:1               ; 4 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[3]                                                                                                                            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[3]                                                               ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_data[6]                                                                                                                                                       ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; No         ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|oVGA_R[5]                                                                                                         ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; No         ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|oVGA_G[9]                                                                                                         ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; No         ; |DE2_WEB|system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|oVGA_B[5]                                                                                                         ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_WEB|system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_arb_share_counter_next_value[2]                                                                    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cfgdout[2]                                                                            ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[0]                                      ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_WEB|system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_share_counter_next_value[0]                                ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter_next_value[0]                                                              ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|F_iw[1]                                                                                                                                                             ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|F_iw[0]                                                                                                                                                             ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[0]                                                                                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Selector2                                                                                                                           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_WEB|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_set_values[2]                                              ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|comb~2                                                                                                                                                          ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_WEB|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|updated_one_count~15                                      ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_WEB|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|updated_one_count~17                                      ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_logic_result[9]                                                                                                                                                   ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[0]                                                                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_alu_result[31]                                                                                                                                                    ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_alu_result[10]                                                                                                                                                    ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[4]                                                                                                                     ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[0]                                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Selector3                                                                                                                           ;
; 5:1                ; 7 bits    ; 21 LEs        ; 21 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_alu_result[26]                                                                                                                                                    ;
; 5:1                ; 13 bits   ; 39 LEs        ; 39 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|E_alu_result[19]                                                                                                                                                    ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|D_src2_reg[20]                                                                                                                                                      ;
; 5:1                ; 16 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[26]                                                                                                                                            ;
; 5:1                ; 8 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[15]                                                                                                                                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[5]                                                                                                                                             ;
; 6:1                ; 10 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[6]                                                                                                                                             ;
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; No         ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|Selector33                                                                                                                                                      ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|Selector24                                                                                                                                                      ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |DE2_WEB|system_0:u0|sdram_0:the_sdram_0|Selector27                                                                                                                                                      ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[36] ;
; 6:1                ; 6 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12] ;
; 6:1                ; 18 bits   ; 72 LEs        ; 36 LEs               ; 36 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[21] ;
; 6:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[4]  ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[1]                                                                                                ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9]                                                                                             ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7]                                                                                             ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |DE2_WEB|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1]                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                             ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                              ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated ;
+---------------------------------+-------+------------------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From             ; To                                                                                            ;
+---------------------------------+-------+------------------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -                ; -                                                                                             ;
; REMOVE_DUPLICATE_REGISTERS      ; OFF   ; -                ; -                                                                                             ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -                ; -                                                                                             ;
; POWER_UP_LEVEL                  ; LOW   ; -                ; p0addr                                                                                        ;
; SUPPRESS_DA_RULE_INTERNAL       ; c106  ; -                ; rdaclr                                                                                        ;
; POWER_UP_LEVEL                  ; LOW   ; -                ; rdaclr                                                                                        ;
; CUT                             ; ON    ; rdptr_g          ; ws_dgrp|dffpipe11|dffe12a                                                                     ;
; CUT                             ; ON    ; delayed_wrptr_g  ; rs_dgwp|dffpipe6|dffe7a                                                                       ;
; CUT                             ; ON    ; previous_rdempty ; wrempty_reg|dffpipe9|dffe10a                                                                  ;
+---------------------------------+-------+------------------+-----------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                    ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                     ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram|altsyncram_brg1:altsyncram4 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                                                             ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                                                              ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp|dffpipe_hd9:dffpipe6 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                        ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                         ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_hn7:wrempty_reg ;
+-----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                                                                 ;
+-----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                                                                  ;
+-----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_hn7:wrempty_reg|dffpipe_bo8:dffpipe9 ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                            ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                             ;
+---------------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment            ; Value ; From ; To                                                                                                                                             ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                                                                              ;
+-----------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp|dffpipe_id9:dffpipe11 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                         ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                          ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                            ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                             ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                        ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                         ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0                                 ;
+-------------------+-------+----------------------------+-------------------------------+
; Assignment        ; Value ; From                       ; To                            ;
+-------------------+-------+----------------------------+-------------------------------+
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]           ;
; CUT               ; ON    ; *                          ; slave_readdata[15]            ;
; CUT               ; ON    ; *                          ; slave_readdata[14]            ;
; CUT               ; ON    ; *                          ; slave_readdata[13]            ;
; CUT               ; ON    ; *                          ; slave_readdata[12]            ;
; CUT               ; ON    ; *                          ; slave_readdata[11]            ;
; CUT               ; ON    ; *                          ; slave_readdata[10]            ;
; CUT               ; ON    ; *                          ; slave_readdata[9]             ;
; CUT               ; ON    ; *                          ; slave_readdata[8]             ;
; CUT               ; ON    ; *                          ; slave_readdata[7]             ;
; CUT               ; ON    ; *                          ; slave_readdata[6]             ;
; CUT               ; ON    ; *                          ; slave_readdata[5]             ;
; CUT               ; ON    ; *                          ; slave_readdata[4]             ;
; CUT               ; ON    ; *                          ; slave_readdata[3]             ;
; CUT               ; ON    ; *                          ; slave_readdata[2]             ;
; CUT               ; ON    ; *                          ; slave_readdata[1]             ;
; CUT               ; ON    ; *                          ; slave_readdata[0]             ;
; CUT               ; ON    ; *                          ; slave_readdata[15]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[14]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[13]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[12]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[11]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[10]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[9]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[8]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[7]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[6]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[5]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[4]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[3]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[2]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[1]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[0]~reg0        ;
; CUT               ; ON    ; slave_writedata_d1[15]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[15]        ;
; CUT               ; ON    ; slave_writedata_d1[14]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[14]        ;
; CUT               ; ON    ; slave_writedata_d1[13]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[13]        ;
; CUT               ; ON    ; slave_writedata_d1[12]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[12]        ;
; CUT               ; ON    ; slave_writedata_d1[11]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[11]        ;
; CUT               ; ON    ; slave_writedata_d1[10]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[10]        ;
; CUT               ; ON    ; slave_writedata_d1[9]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[9]         ;
; CUT               ; ON    ; slave_writedata_d1[8]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[8]         ;
; CUT               ; ON    ; slave_writedata_d1[7]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[7]         ;
; CUT               ; ON    ; slave_writedata_d1[6]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[6]         ;
; CUT               ; ON    ; slave_writedata_d1[5]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[5]         ;
; CUT               ; ON    ; slave_writedata_d1[4]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[4]         ;
; CUT               ; ON    ; slave_writedata_d1[3]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[3]         ;
; CUT               ; ON    ; slave_writedata_d1[2]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[2]         ;
; CUT               ; ON    ; slave_writedata_d1[1]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[1]         ;
; CUT               ; ON    ; slave_writedata_d1[0]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[0]         ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]~reg0      ;
; CUT               ; ON    ; slave_address_d1[22]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[22]          ;
; CUT               ; ON    ; slave_address_d1[21]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[21]          ;
; CUT               ; ON    ; slave_address_d1[20]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[20]          ;
; CUT               ; ON    ; slave_address_d1[19]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[19]          ;
; CUT               ; ON    ; slave_address_d1[18]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[18]          ;
; CUT               ; ON    ; slave_address_d1[17]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[17]          ;
; CUT               ; ON    ; slave_address_d1[16]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[16]          ;
; CUT               ; ON    ; slave_address_d1[15]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[15]          ;
; CUT               ; ON    ; slave_address_d1[14]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[14]          ;
; CUT               ; ON    ; slave_address_d1[13]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[13]          ;
; CUT               ; ON    ; slave_address_d1[12]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[12]          ;
; CUT               ; ON    ; slave_address_d1[11]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[11]          ;
; CUT               ; ON    ; slave_address_d1[10]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[10]          ;
; CUT               ; ON    ; slave_address_d1[9]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[9]           ;
; CUT               ; ON    ; slave_address_d1[8]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[8]           ;
; CUT               ; ON    ; slave_address_d1[7]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[7]           ;
; CUT               ; ON    ; slave_address_d1[6]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[6]           ;
; CUT               ; ON    ; slave_address_d1[5]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[5]           ;
; CUT               ; ON    ; slave_address_d1[4]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[4]           ;
; CUT               ; ON    ; slave_address_d1[3]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[3]           ;
; CUT               ; ON    ; slave_address_d1[2]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[2]           ;
; CUT               ; ON    ; slave_address_d1[1]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[1]           ;
; CUT               ; ON    ; slave_address_d1[0]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[0]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]~reg0        ;
; CUT               ; ON    ; slave_nativeaddress_d1[21] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[21]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[20] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[20]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[19] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[19]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[18] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[18]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[17] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[17]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[16] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[16]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[15] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[15]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[14] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[14]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[13] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[13]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[12] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[12]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[11] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[11]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[10] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[10]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[9]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[9]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[8]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[8]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[7]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[7]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[6]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[6]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[5]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[5]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[4]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[4]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[3]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[3]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[2]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[2]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[1]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[1]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[0]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]~reg0  ;
; CUT               ; ON    ; slave_byteenable_d1[1]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[1]        ;
; CUT               ; ON    ; slave_byteenable_d1[0]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]~reg0     ;
+-------------------+-------+----------------------------+-------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                     ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                          ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                             ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                             ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                       ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                            ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                               ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                         ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                              ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                           ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                                ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                   ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------------+-----------------------------------------------------+
; Assignment        ; Value ; From       ; To                                                  ;
+-------------------+-------+------------+-----------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -          ; data_out                                            ;
; PRESERVE_REGISTER ; ON    ; -          ; data_out~reg0                                       ;
; CUT               ; ON    ; data_in_d1 ; *                                                   ;
; PRESERVE_REGISTER ; ON    ; -          ; data_in_d1                                          ;
+-------------------+-------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1                                 ;
+-------------------+-------+----------------------------+-------------------------------+
; Assignment        ; Value ; From                       ; To                            ;
+-------------------+-------+----------------------------+-------------------------------+
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]           ;
; CUT               ; ON    ; *                          ; slave_readdata[15]            ;
; CUT               ; ON    ; *                          ; slave_readdata[14]            ;
; CUT               ; ON    ; *                          ; slave_readdata[13]            ;
; CUT               ; ON    ; *                          ; slave_readdata[12]            ;
; CUT               ; ON    ; *                          ; slave_readdata[11]            ;
; CUT               ; ON    ; *                          ; slave_readdata[10]            ;
; CUT               ; ON    ; *                          ; slave_readdata[9]             ;
; CUT               ; ON    ; *                          ; slave_readdata[8]             ;
; CUT               ; ON    ; *                          ; slave_readdata[7]             ;
; CUT               ; ON    ; *                          ; slave_readdata[6]             ;
; CUT               ; ON    ; *                          ; slave_readdata[5]             ;
; CUT               ; ON    ; *                          ; slave_readdata[4]             ;
; CUT               ; ON    ; *                          ; slave_readdata[3]             ;
; CUT               ; ON    ; *                          ; slave_readdata[2]             ;
; CUT               ; ON    ; *                          ; slave_readdata[1]             ;
; CUT               ; ON    ; *                          ; slave_readdata[0]             ;
; CUT               ; ON    ; *                          ; slave_readdata[15]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[14]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[13]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[12]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[11]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[10]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[9]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[8]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[7]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[6]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[5]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[4]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[3]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[2]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[1]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[0]~reg0        ;
; CUT               ; ON    ; slave_writedata_d1[15]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[15]        ;
; CUT               ; ON    ; slave_writedata_d1[14]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[14]        ;
; CUT               ; ON    ; slave_writedata_d1[13]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[13]        ;
; CUT               ; ON    ; slave_writedata_d1[12]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[12]        ;
; CUT               ; ON    ; slave_writedata_d1[11]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[11]        ;
; CUT               ; ON    ; slave_writedata_d1[10]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[10]        ;
; CUT               ; ON    ; slave_writedata_d1[9]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[9]         ;
; CUT               ; ON    ; slave_writedata_d1[8]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[8]         ;
; CUT               ; ON    ; slave_writedata_d1[7]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[7]         ;
; CUT               ; ON    ; slave_writedata_d1[6]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[6]         ;
; CUT               ; ON    ; slave_writedata_d1[5]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[5]         ;
; CUT               ; ON    ; slave_writedata_d1[4]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[4]         ;
; CUT               ; ON    ; slave_writedata_d1[3]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[3]         ;
; CUT               ; ON    ; slave_writedata_d1[2]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[2]         ;
; CUT               ; ON    ; slave_writedata_d1[1]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[1]         ;
; CUT               ; ON    ; slave_writedata_d1[0]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[0]         ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]~reg0      ;
; CUT               ; ON    ; slave_address_d1[22]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[22]          ;
; CUT               ; ON    ; slave_address_d1[21]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[21]          ;
; CUT               ; ON    ; slave_address_d1[20]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[20]          ;
; CUT               ; ON    ; slave_address_d1[19]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[19]          ;
; CUT               ; ON    ; slave_address_d1[18]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[18]          ;
; CUT               ; ON    ; slave_address_d1[17]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[17]          ;
; CUT               ; ON    ; slave_address_d1[16]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[16]          ;
; CUT               ; ON    ; slave_address_d1[15]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[15]          ;
; CUT               ; ON    ; slave_address_d1[14]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[14]          ;
; CUT               ; ON    ; slave_address_d1[13]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[13]          ;
; CUT               ; ON    ; slave_address_d1[12]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[12]          ;
; CUT               ; ON    ; slave_address_d1[11]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[11]          ;
; CUT               ; ON    ; slave_address_d1[10]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[10]          ;
; CUT               ; ON    ; slave_address_d1[9]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[9]           ;
; CUT               ; ON    ; slave_address_d1[8]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[8]           ;
; CUT               ; ON    ; slave_address_d1[7]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[7]           ;
; CUT               ; ON    ; slave_address_d1[6]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[6]           ;
; CUT               ; ON    ; slave_address_d1[5]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[5]           ;
; CUT               ; ON    ; slave_address_d1[4]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[4]           ;
; CUT               ; ON    ; slave_address_d1[3]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[3]           ;
; CUT               ; ON    ; slave_address_d1[2]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[2]           ;
; CUT               ; ON    ; slave_address_d1[1]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[1]           ;
; CUT               ; ON    ; slave_address_d1[0]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[0]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]~reg0        ;
; CUT               ; ON    ; slave_nativeaddress_d1[21] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[21]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[20] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[20]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[19] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[19]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[18] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[18]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[17] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[17]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[16] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[16]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[15] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[15]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[14] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[14]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[13] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[13]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[12] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[12]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[11] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[11]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[10] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[10]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[9]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[9]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[8]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[8]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[7]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[7]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[6]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[6]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[5]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[5]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[4]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[4]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[3]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[3]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[2]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[2]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[1]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[1]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[0]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]~reg0  ;
; CUT               ; ON    ; slave_byteenable_d1[1]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[1]        ;
; CUT               ; ON    ; slave_byteenable_d1[0]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]~reg0     ;
+-------------------+-------+----------------------------+-------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                     ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                          ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                             ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                             ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                       ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                            ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                               ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                         ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                              ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                           ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                                ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                   ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------------+-----------------------------------------------------+
; Assignment        ; Value ; From       ; To                                                  ;
+-------------------+-------+------------+-----------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -          ; data_out                                            ;
; PRESERVE_REGISTER ; ON    ; -          ; data_out~reg0                                       ;
; CUT               ; ON    ; data_in_d1 ; *                                                   ;
; PRESERVE_REGISTER ; ON    ; -          ; data_in_d1                                          ;
+-------------------+-------+------------+-----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                               ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                             ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                              ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                       ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                        ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                   ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                    ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                             ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                              ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                               ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                   ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                    ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                   ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                    ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                              ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------+
; Source assignments for system_0:u0|sdram_0:the_sdram_0        ;
+-----------------------------+-------+------+------------------+
; Assignment                  ; Value ; From ; To               ;
+-----------------------------+-------+------+------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[0]         ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; oe               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]~reg0  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[3]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[2]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[0]         ;
+-----------------------------+-------+------+------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ;
+-----------------------------+-------+------+----------------------------------------------------------------------+
; Assignment                  ; Value ; From ; To                                                                   ;
+-----------------------------+-------+------+----------------------------------------------------------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[7]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[6]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[5]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[4]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[3]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[2]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[1]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[0]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash_0                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[21]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[20]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[19]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[18]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[17]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[16]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[15]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[14]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[13]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[12]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[11]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[10]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[9]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[8]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[7]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[6]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[5]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[4]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[3]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[2]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[1]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[0]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_readn                                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash_0                                           ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[7]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[6]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[5]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[4]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[3]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[2]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[1]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[0]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[7]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[6]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[5]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[4]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[3]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[2]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[1]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[0]                               ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; d1_in_a_write_cycle                                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[21]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[20]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[19]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[18]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[17]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[16]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[15]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[14]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[13]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[12]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[11]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[10]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[9]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[8]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[7]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[6]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[5]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[4]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[3]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[2]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[1]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[0]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash_0~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_readn~reg0                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash_0~reg0                                      ;
+-----------------------------+-------+------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch ;
+-------------------+-------+------+------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                     ;
+-------------------+-------+------+------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                          ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                             ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                             ;
+-------------------+-------+------+------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch ;
+-------------------+-------+------+------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                           ;
+-------------------+-------+------+------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                   ;
+-------------------+-------+------+------------------------------------------------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
+----------------+-------+------+-------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                    ;
+----------------+-------+------+-------------------------------------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; state[0]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[1]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[2]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[3]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[4]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[5]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[6]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[7]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[8]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[9]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[10]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[11]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[12]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[13]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[14]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[15]                                             ;
+----------------+-------+------+-------------------------------------------------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[0]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[1]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[2]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[3]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[4]               ;
+----------------------+-------+------+-------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_ocv:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------+
; Assignment                      ; Value              ; From ; To                            ;
+---------------------------------+--------------------+------+-------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                             ;
+---------------------------------+--------------------+------+-------------------------------+


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component ;
+-------------------------------+-------------+---------------------------------------+
; Parameter Name                ; Value       ; Type                                  ;
+-------------------------------+-------------+---------------------------------------+
; OPERATION_MODE                ; NORMAL      ; Untyped                               ;
; PLL_TYPE                      ; FAST        ; Untyped                               ;
; QUALIFY_CONF_DONE             ; OFF         ; Untyped                               ;
; COMPENSATE_CLOCK              ; CLK0        ; Untyped                               ;
; SCAN_CHAIN                    ; LONG        ; Untyped                               ;
; PRIMARY_CLOCK                 ; INCLK0      ; Untyped                               ;
; INCLK0_INPUT_FREQUENCY        ; 20000       ; Integer                               ;
; INCLK1_INPUT_FREQUENCY        ; 0           ; Untyped                               ;
; GATE_LOCK_SIGNAL              ; NO          ; Untyped                               ;
; GATE_LOCK_COUNTER             ; 0           ; Untyped                               ;
; LOCK_HIGH                     ; 1           ; Untyped                               ;
; LOCK_LOW                      ; 1           ; Untyped                               ;
; VALID_LOCK_MULTIPLIER         ; 1           ; Untyped                               ;
; INVALID_LOCK_MULTIPLIER       ; 5           ; Untyped                               ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF         ; Untyped                               ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF         ; Untyped                               ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF         ; Untyped                               ;
; SKIP_VCO                      ; OFF         ; Untyped                               ;
; SWITCH_OVER_COUNTER           ; 0           ; Untyped                               ;
; SWITCH_OVER_TYPE              ; AUTO        ; Untyped                               ;
; FEEDBACK_SOURCE               ; EXTCLK0     ; Untyped                               ;
; BANDWIDTH                     ; 0           ; Untyped                               ;
; BANDWIDTH_TYPE                ; AUTO        ; Untyped                               ;
; SPREAD_FREQUENCY              ; 0           ; Untyped                               ;
; DOWN_SPREAD                   ; 0           ; Untyped                               ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF         ; Untyped                               ;
; CLK5_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK4_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK3_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK2_MULTIPLY_BY              ; 1           ; Integer                               ;
; CLK1_MULTIPLY_BY              ; 2           ; Integer                               ;
; CLK0_MULTIPLY_BY              ; 1           ; Integer                               ;
; CLK5_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK4_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK3_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK2_DIVIDE_BY                ; 2           ; Integer                               ;
; CLK1_DIVIDE_BY                ; 1           ; Integer                               ;
; CLK0_DIVIDE_BY                ; 1           ; Integer                               ;
; CLK5_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK4_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK3_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK2_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK1_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK0_PHASE_SHIFT              ; -3000       ; Untyped                               ;
; CLK5_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK4_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK3_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK2_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK1_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK0_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK5_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK4_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK3_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK2_DUTY_CYCLE               ; 50          ; Integer                               ;
; CLK1_DUTY_CYCLE               ; 50          ; Integer                               ;
; CLK0_DUTY_CYCLE               ; 50          ; Integer                               ;
; EXTCLK3_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK2_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK1_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK0_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK3_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK2_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK1_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK0_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK3_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK2_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK1_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK0_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK3_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK2_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK1_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK0_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK3_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK2_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK1_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK0_DUTY_CYCLE            ; 50          ; Untyped                               ;
; VCO_MULTIPLY_BY               ; 0           ; Untyped                               ;
; VCO_DIVIDE_BY                 ; 0           ; Untyped                               ;
; SCLKOUT0_PHASE_SHIFT          ; 0           ; Untyped                               ;
; SCLKOUT1_PHASE_SHIFT          ; 0           ; Untyped                               ;
; VCO_MIN                       ; 0           ; Untyped                               ;
; VCO_MAX                       ; 0           ; Untyped                               ;
; VCO_CENTER                    ; 0           ; Untyped                               ;
; PFD_MIN                       ; 0           ; Untyped                               ;
; PFD_MAX                       ; 0           ; Untyped                               ;
; M_INITIAL                     ; 0           ; Untyped                               ;
; M                             ; 0           ; Untyped                               ;
; N                             ; 1           ; Untyped                               ;
; M2                            ; 1           ; Untyped                               ;
; N2                            ; 1           ; Untyped                               ;
; SS                            ; 1           ; Untyped                               ;
; C0_HIGH                       ; 0           ; Untyped                               ;
; C1_HIGH                       ; 0           ; Untyped                               ;
; C2_HIGH                       ; 0           ; Untyped                               ;
; C3_HIGH                       ; 0           ; Untyped                               ;
; C4_HIGH                       ; 0           ; Untyped                               ;
; C5_HIGH                       ; 0           ; Untyped                               ;
; C0_LOW                        ; 0           ; Untyped                               ;
; C1_LOW                        ; 0           ; Untyped                               ;
; C2_LOW                        ; 0           ; Untyped                               ;
; C3_LOW                        ; 0           ; Untyped                               ;
; C4_LOW                        ; 0           ; Untyped                               ;
; C5_LOW                        ; 0           ; Untyped                               ;
; C0_INITIAL                    ; 0           ; Untyped                               ;
; C1_INITIAL                    ; 0           ; Untyped                               ;
; C2_INITIAL                    ; 0           ; Untyped                               ;
; C3_INITIAL                    ; 0           ; Untyped                               ;
; C4_INITIAL                    ; 0           ; Untyped                               ;
; C5_INITIAL                    ; 0           ; Untyped                               ;
; C0_MODE                       ; BYPASS      ; Untyped                               ;
; C1_MODE                       ; BYPASS      ; Untyped                               ;
; C2_MODE                       ; BYPASS      ; Untyped                               ;
; C3_MODE                       ; BYPASS      ; Untyped                               ;
; C4_MODE                       ; BYPASS      ; Untyped                               ;
; C5_MODE                       ; BYPASS      ; Untyped                               ;
; C0_PH                         ; 0           ; Untyped                               ;
; C1_PH                         ; 0           ; Untyped                               ;
; C2_PH                         ; 0           ; Untyped                               ;
; C3_PH                         ; 0           ; Untyped                               ;
; C4_PH                         ; 0           ; Untyped                               ;
; C5_PH                         ; 0           ; Untyped                               ;
; L0_HIGH                       ; 1           ; Untyped                               ;
; L1_HIGH                       ; 1           ; Untyped                               ;
; G0_HIGH                       ; 1           ; Untyped                               ;
; G1_HIGH                       ; 1           ; Untyped                               ;
; G2_HIGH                       ; 1           ; Untyped                               ;
; G3_HIGH                       ; 1           ; Untyped                               ;
; E0_HIGH                       ; 1           ; Untyped                               ;
; E1_HIGH                       ; 1           ; Untyped                               ;
; E2_HIGH                       ; 1           ; Untyped                               ;
; E3_HIGH                       ; 1           ; Untyped                               ;
; L0_LOW                        ; 1           ; Untyped                               ;
; L1_LOW                        ; 1           ; Untyped                               ;
; G0_LOW                        ; 1           ; Untyped                               ;
; G1_LOW                        ; 1           ; Untyped                               ;
; G2_LOW                        ; 1           ; Untyped                               ;
; G3_LOW                        ; 1           ; Untyped                               ;
; E0_LOW                        ; 1           ; Untyped                               ;
; E1_LOW                        ; 1           ; Untyped                               ;
; E2_LOW                        ; 1           ; Untyped                               ;
; E3_LOW                        ; 1           ; Untyped                               ;
; L0_INITIAL                    ; 1           ; Untyped                               ;
; L1_INITIAL                    ; 1           ; Untyped                               ;
; G0_INITIAL                    ; 1           ; Untyped                               ;
; G1_INITIAL                    ; 1           ; Untyped                               ;
; G2_INITIAL                    ; 1           ; Untyped                               ;
; G3_INITIAL                    ; 1           ; Untyped                               ;
; E0_INITIAL                    ; 1           ; Untyped                               ;
; E1_INITIAL                    ; 1           ; Untyped                               ;
; E2_INITIAL                    ; 1           ; Untyped                               ;
; E3_INITIAL                    ; 1           ; Untyped                               ;
; L0_MODE                       ; BYPASS      ; Untyped                               ;
; L1_MODE                       ; BYPASS      ; Untyped                               ;
; G0_MODE                       ; BYPASS      ; Untyped                               ;
; G1_MODE                       ; BYPASS      ; Untyped                               ;
; G2_MODE                       ; BYPASS      ; Untyped                               ;
; G3_MODE                       ; BYPASS      ; Untyped                               ;
; E0_MODE                       ; BYPASS      ; Untyped                               ;
; E1_MODE                       ; BYPASS      ; Untyped                               ;
; E2_MODE                       ; BYPASS      ; Untyped                               ;
; E3_MODE                       ; BYPASS      ; Untyped                               ;
; L0_PH                         ; 0           ; Untyped                               ;
; L1_PH                         ; 0           ; Untyped                               ;
; G0_PH                         ; 0           ; Untyped                               ;
; G1_PH                         ; 0           ; Untyped                               ;
; G2_PH                         ; 0           ; Untyped                               ;
; G3_PH                         ; 0           ; Untyped                               ;
; E0_PH                         ; 0           ; Untyped                               ;
; E1_PH                         ; 0           ; Untyped                               ;
; E2_PH                         ; 0           ; Untyped                               ;
; E3_PH                         ; 0           ; Untyped                               ;
; M_PH                          ; 0           ; Untyped                               ;
; C1_USE_CASC_IN                ; 0           ; Untyped                               ;
; C2_USE_CASC_IN                ; 0           ; Untyped                               ;
; C3_USE_CASC_IN                ; 0           ; Untyped                               ;
; C4_USE_CASC_IN                ; 0           ; Untyped                               ;
; C5_USE_CASC_IN                ; 0           ; Untyped                               ;
; CLK0_COUNTER                  ; G0          ; Untyped                               ;
; CLK1_COUNTER                  ; G0          ; Untyped                               ;
; CLK2_COUNTER                  ; G0          ; Untyped                               ;
; CLK3_COUNTER                  ; G0          ; Untyped                               ;
; CLK4_COUNTER                  ; G0          ; Untyped                               ;
; CLK5_COUNTER                  ; G0          ; Untyped                               ;
; L0_TIME_DELAY                 ; 0           ; Untyped                               ;
; L1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G0_TIME_DELAY                 ; 0           ; Untyped                               ;
; G1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G2_TIME_DELAY                 ; 0           ; Untyped                               ;
; G3_TIME_DELAY                 ; 0           ; Untyped                               ;
; E0_TIME_DELAY                 ; 0           ; Untyped                               ;
; E1_TIME_DELAY                 ; 0           ; Untyped                               ;
; E2_TIME_DELAY                 ; 0           ; Untyped                               ;
; E3_TIME_DELAY                 ; 0           ; Untyped                               ;
; M_TIME_DELAY                  ; 0           ; Untyped                               ;
; N_TIME_DELAY                  ; 0           ; Untyped                               ;
; EXTCLK3_COUNTER               ; E3          ; Untyped                               ;
; EXTCLK2_COUNTER               ; E2          ; Untyped                               ;
; EXTCLK1_COUNTER               ; E1          ; Untyped                               ;
; EXTCLK0_COUNTER               ; E0          ; Untyped                               ;
; ENABLE0_COUNTER               ; L0          ; Untyped                               ;
; ENABLE1_COUNTER               ; L0          ; Untyped                               ;
; CHARGE_PUMP_CURRENT           ; 2           ; Untyped                               ;
; LOOP_FILTER_R                 ;  1.000000   ; Untyped                               ;
; LOOP_FILTER_C                 ; 5           ; Untyped                               ;
; VCO_POST_SCALE                ; 0           ; Untyped                               ;
; CLK2_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK1_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK0_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II  ; Untyped                               ;
; PORT_CLKENA0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA4                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA5                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA0               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA1               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA2               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA3               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK0                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK1                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK2                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK3                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK4                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK5                     ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATA                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATAOUT              ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDONE                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT1                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT0                 ; PORT_UNUSED ; Untyped                               ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKLOSS                  ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK1                   ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK0                   ; PORT_USED   ; Untyped                               ;
; PORT_FBIN                     ; PORT_UNUSED ; Untyped                               ;
; PORT_PLLENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKSWITCH                ; PORT_UNUSED ; Untyped                               ;
; PORT_ARESET                   ; PORT_UNUSED ; Untyped                               ;
; PORT_PFDENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANCLK                  ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANACLR                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANREAD                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANWRITE                ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_LOCKED                   ; PORT_UNUSED ; Untyped                               ;
; M_TEST_SOURCE                 ; 5           ; Untyped                               ;
; C0_TEST_SOURCE                ; 5           ; Untyped                               ;
; C1_TEST_SOURCE                ; 5           ; Untyped                               ;
; C2_TEST_SOURCE                ; 5           ; Untyped                               ;
; C3_TEST_SOURCE                ; 5           ; Untyped                               ;
; C4_TEST_SOURCE                ; 5           ; Untyped                               ;
; C5_TEST_SOURCE                ; 5           ; Untyped                               ;
; DEVICE_FAMILY                 ; Cyclone II  ; Untyped                               ;
; AUTO_CARRY_CHAINS             ; ON          ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS          ; OFF         ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS           ; ON          ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS        ; OFF         ; IGNORE_CASCADE                        ;
+-------------------------------+-------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Audio_PLL:PLL2|altpll:altpll_component ;
+-------------------------------+-------------+---------------------------------------+
; Parameter Name                ; Value       ; Type                                  ;
+-------------------------------+-------------+---------------------------------------+
; OPERATION_MODE                ; NORMAL      ; Untyped                               ;
; PLL_TYPE                      ; FAST        ; Untyped                               ;
; QUALIFY_CONF_DONE             ; OFF         ; Untyped                               ;
; COMPENSATE_CLOCK              ; CLK0        ; Untyped                               ;
; SCAN_CHAIN                    ; LONG        ; Untyped                               ;
; PRIMARY_CLOCK                 ; INCLK0      ; Untyped                               ;
; INCLK0_INPUT_FREQUENCY        ; 37037       ; Integer                               ;
; INCLK1_INPUT_FREQUENCY        ; 0           ; Untyped                               ;
; GATE_LOCK_SIGNAL              ; NO          ; Untyped                               ;
; GATE_LOCK_COUNTER             ; 0           ; Untyped                               ;
; LOCK_HIGH                     ; 1           ; Untyped                               ;
; LOCK_LOW                      ; 1           ; Untyped                               ;
; VALID_LOCK_MULTIPLIER         ; 1           ; Untyped                               ;
; INVALID_LOCK_MULTIPLIER       ; 5           ; Untyped                               ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF         ; Untyped                               ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF         ; Untyped                               ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF         ; Untyped                               ;
; SKIP_VCO                      ; OFF         ; Untyped                               ;
; SWITCH_OVER_COUNTER           ; 0           ; Untyped                               ;
; SWITCH_OVER_TYPE              ; AUTO        ; Untyped                               ;
; FEEDBACK_SOURCE               ; EXTCLK0     ; Untyped                               ;
; BANDWIDTH                     ; 0           ; Untyped                               ;
; BANDWIDTH_TYPE                ; AUTO        ; Untyped                               ;
; SPREAD_FREQUENCY              ; 0           ; Untyped                               ;
; DOWN_SPREAD                   ; 0           ; Untyped                               ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF         ; Untyped                               ;
; CLK5_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK4_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK3_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK2_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK1_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK0_MULTIPLY_BY              ; 92          ; Integer                               ;
; CLK5_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK4_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK3_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK2_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK1_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK0_DIVIDE_BY                ; 135         ; Integer                               ;
; CLK5_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK4_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK3_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK2_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK1_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK0_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK5_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK4_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK3_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK2_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK1_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK0_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK5_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK4_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK3_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK2_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK1_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK0_DUTY_CYCLE               ; 50          ; Integer                               ;
; EXTCLK3_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK2_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK1_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK0_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK3_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK2_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK1_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK0_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK3_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK2_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK1_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK0_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK3_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK2_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK1_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK0_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK3_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK2_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK1_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK0_DUTY_CYCLE            ; 50          ; Untyped                               ;
; VCO_MULTIPLY_BY               ; 0           ; Untyped                               ;
; VCO_DIVIDE_BY                 ; 0           ; Untyped                               ;
; SCLKOUT0_PHASE_SHIFT          ; 0           ; Untyped                               ;
; SCLKOUT1_PHASE_SHIFT          ; 0           ; Untyped                               ;
; VCO_MIN                       ; 0           ; Untyped                               ;
; VCO_MAX                       ; 0           ; Untyped                               ;
; VCO_CENTER                    ; 0           ; Untyped                               ;
; PFD_MIN                       ; 0           ; Untyped                               ;
; PFD_MAX                       ; 0           ; Untyped                               ;
; M_INITIAL                     ; 0           ; Untyped                               ;
; M                             ; 0           ; Untyped                               ;
; N                             ; 1           ; Untyped                               ;
; M2                            ; 1           ; Untyped                               ;
; N2                            ; 1           ; Untyped                               ;
; SS                            ; 1           ; Untyped                               ;
; C0_HIGH                       ; 0           ; Untyped                               ;
; C1_HIGH                       ; 0           ; Untyped                               ;
; C2_HIGH                       ; 0           ; Untyped                               ;
; C3_HIGH                       ; 0           ; Untyped                               ;
; C4_HIGH                       ; 0           ; Untyped                               ;
; C5_HIGH                       ; 0           ; Untyped                               ;
; C0_LOW                        ; 0           ; Untyped                               ;
; C1_LOW                        ; 0           ; Untyped                               ;
; C2_LOW                        ; 0           ; Untyped                               ;
; C3_LOW                        ; 0           ; Untyped                               ;
; C4_LOW                        ; 0           ; Untyped                               ;
; C5_LOW                        ; 0           ; Untyped                               ;
; C0_INITIAL                    ; 0           ; Untyped                               ;
; C1_INITIAL                    ; 0           ; Untyped                               ;
; C2_INITIAL                    ; 0           ; Untyped                               ;
; C3_INITIAL                    ; 0           ; Untyped                               ;
; C4_INITIAL                    ; 0           ; Untyped                               ;
; C5_INITIAL                    ; 0           ; Untyped                               ;
; C0_MODE                       ; BYPASS      ; Untyped                               ;
; C1_MODE                       ; BYPASS      ; Untyped                               ;
; C2_MODE                       ; BYPASS      ; Untyped                               ;
; C3_MODE                       ; BYPASS      ; Untyped                               ;
; C4_MODE                       ; BYPASS      ; Untyped                               ;
; C5_MODE                       ; BYPASS      ; Untyped                               ;
; C0_PH                         ; 0           ; Untyped                               ;
; C1_PH                         ; 0           ; Untyped                               ;
; C2_PH                         ; 0           ; Untyped                               ;
; C3_PH                         ; 0           ; Untyped                               ;
; C4_PH                         ; 0           ; Untyped                               ;
; C5_PH                         ; 0           ; Untyped                               ;
; L0_HIGH                       ; 1           ; Untyped                               ;
; L1_HIGH                       ; 1           ; Untyped                               ;
; G0_HIGH                       ; 1           ; Untyped                               ;
; G1_HIGH                       ; 1           ; Untyped                               ;
; G2_HIGH                       ; 1           ; Untyped                               ;
; G3_HIGH                       ; 1           ; Untyped                               ;
; E0_HIGH                       ; 1           ; Untyped                               ;
; E1_HIGH                       ; 1           ; Untyped                               ;
; E2_HIGH                       ; 1           ; Untyped                               ;
; E3_HIGH                       ; 1           ; Untyped                               ;
; L0_LOW                        ; 1           ; Untyped                               ;
; L1_LOW                        ; 1           ; Untyped                               ;
; G0_LOW                        ; 1           ; Untyped                               ;
; G1_LOW                        ; 1           ; Untyped                               ;
; G2_LOW                        ; 1           ; Untyped                               ;
; G3_LOW                        ; 1           ; Untyped                               ;
; E0_LOW                        ; 1           ; Untyped                               ;
; E1_LOW                        ; 1           ; Untyped                               ;
; E2_LOW                        ; 1           ; Untyped                               ;
; E3_LOW                        ; 1           ; Untyped                               ;
; L0_INITIAL                    ; 1           ; Untyped                               ;
; L1_INITIAL                    ; 1           ; Untyped                               ;
; G0_INITIAL                    ; 1           ; Untyped                               ;
; G1_INITIAL                    ; 1           ; Untyped                               ;
; G2_INITIAL                    ; 1           ; Untyped                               ;
; G3_INITIAL                    ; 1           ; Untyped                               ;
; E0_INITIAL                    ; 1           ; Untyped                               ;
; E1_INITIAL                    ; 1           ; Untyped                               ;
; E2_INITIAL                    ; 1           ; Untyped                               ;
; E3_INITIAL                    ; 1           ; Untyped                               ;
; L0_MODE                       ; BYPASS      ; Untyped                               ;
; L1_MODE                       ; BYPASS      ; Untyped                               ;
; G0_MODE                       ; BYPASS      ; Untyped                               ;
; G1_MODE                       ; BYPASS      ; Untyped                               ;
; G2_MODE                       ; BYPASS      ; Untyped                               ;
; G3_MODE                       ; BYPASS      ; Untyped                               ;
; E0_MODE                       ; BYPASS      ; Untyped                               ;
; E1_MODE                       ; BYPASS      ; Untyped                               ;
; E2_MODE                       ; BYPASS      ; Untyped                               ;
; E3_MODE                       ; BYPASS      ; Untyped                               ;
; L0_PH                         ; 0           ; Untyped                               ;
; L1_PH                         ; 0           ; Untyped                               ;
; G0_PH                         ; 0           ; Untyped                               ;
; G1_PH                         ; 0           ; Untyped                               ;
; G2_PH                         ; 0           ; Untyped                               ;
; G3_PH                         ; 0           ; Untyped                               ;
; E0_PH                         ; 0           ; Untyped                               ;
; E1_PH                         ; 0           ; Untyped                               ;
; E2_PH                         ; 0           ; Untyped                               ;
; E3_PH                         ; 0           ; Untyped                               ;
; M_PH                          ; 0           ; Untyped                               ;
; C1_USE_CASC_IN                ; 0           ; Untyped                               ;
; C2_USE_CASC_IN                ; 0           ; Untyped                               ;
; C3_USE_CASC_IN                ; 0           ; Untyped                               ;
; C4_USE_CASC_IN                ; 0           ; Untyped                               ;
; C5_USE_CASC_IN                ; 0           ; Untyped                               ;
; CLK0_COUNTER                  ; G0          ; Untyped                               ;
; CLK1_COUNTER                  ; G0          ; Untyped                               ;
; CLK2_COUNTER                  ; G0          ; Untyped                               ;
; CLK3_COUNTER                  ; G0          ; Untyped                               ;
; CLK4_COUNTER                  ; G0          ; Untyped                               ;
; CLK5_COUNTER                  ; G0          ; Untyped                               ;
; L0_TIME_DELAY                 ; 0           ; Untyped                               ;
; L1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G0_TIME_DELAY                 ; 0           ; Untyped                               ;
; G1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G2_TIME_DELAY                 ; 0           ; Untyped                               ;
; G3_TIME_DELAY                 ; 0           ; Untyped                               ;
; E0_TIME_DELAY                 ; 0           ; Untyped                               ;
; E1_TIME_DELAY                 ; 0           ; Untyped                               ;
; E2_TIME_DELAY                 ; 0           ; Untyped                               ;
; E3_TIME_DELAY                 ; 0           ; Untyped                               ;
; M_TIME_DELAY                  ; 0           ; Untyped                               ;
; N_TIME_DELAY                  ; 0           ; Untyped                               ;
; EXTCLK3_COUNTER               ; E3          ; Untyped                               ;
; EXTCLK2_COUNTER               ; E2          ; Untyped                               ;
; EXTCLK1_COUNTER               ; E1          ; Untyped                               ;
; EXTCLK0_COUNTER               ; E0          ; Untyped                               ;
; ENABLE0_COUNTER               ; L0          ; Untyped                               ;
; ENABLE1_COUNTER               ; L0          ; Untyped                               ;
; CHARGE_PUMP_CURRENT           ; 2           ; Untyped                               ;
; LOOP_FILTER_R                 ;  1.000000   ; Untyped                               ;
; LOOP_FILTER_C                 ; 5           ; Untyped                               ;
; VCO_POST_SCALE                ; 0           ; Untyped                               ;
; CLK2_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK1_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK0_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II  ; Untyped                               ;
; PORT_CLKENA0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA4                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA5                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA0               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA1               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA2               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA3               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK0                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK1                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK2                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK3                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK4                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK5                     ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATA                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATAOUT              ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDONE                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT1                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT0                 ; PORT_UNUSED ; Untyped                               ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKLOSS                  ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK1                   ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK0                   ; PORT_USED   ; Untyped                               ;
; PORT_FBIN                     ; PORT_UNUSED ; Untyped                               ;
; PORT_PLLENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKSWITCH                ; PORT_UNUSED ; Untyped                               ;
; PORT_ARESET                   ; PORT_USED   ; Untyped                               ;
; PORT_PFDENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANCLK                  ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANACLR                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANREAD                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANWRITE                ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_LOCKED                   ; PORT_UNUSED ; Untyped                               ;
; M_TEST_SOURCE                 ; 5           ; Untyped                               ;
; C0_TEST_SOURCE                ; 5           ; Untyped                               ;
; C1_TEST_SOURCE                ; 5           ; Untyped                               ;
; C2_TEST_SOURCE                ; 5           ; Untyped                               ;
; C3_TEST_SOURCE                ; 5           ; Untyped                               ;
; C4_TEST_SOURCE                ; 5           ; Untyped                               ;
; C5_TEST_SOURCE                ; 5           ; Untyped                               ;
; DEVICE_FAMILY                 ; Cyclone II  ; Untyped                               ;
; AUTO_CARRY_CHAINS             ; ON          ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS          ; OFF         ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS           ; ON          ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS        ; OFF         ; IGNORE_CASCADE                        ;
+-------------------------------+-------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO ;
+----------------+----------+------------------------------------------------------------------------------------+
; Parameter Name ; Value    ; Type                                                                               ;
+----------------+----------+------------------------------------------------------------------------------------+
; REF_CLK        ; 18432000 ; Integer                                                                            ;
; SAMPLE_RATE    ; 48000    ; Integer                                                                            ;
; DATA_WIDTH     ; 16       ; Integer                                                                            ;
; CHANNEL_NUM    ; 2        ; Integer                                                                            ;
+----------------+----------+------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                          ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                                    ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                                  ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                                  ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                                ;
; LPM_WIDTH               ; 16          ; Integer                                                                                                       ;
; LPM_NUMWORDS            ; 256         ; Integer                                                                                                       ;
; LPM_WIDTHU              ; 8           ; Integer                                                                                                       ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                       ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                                       ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                                       ;
; USE_EAB                 ; ON          ; Untyped                                                                                                       ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                       ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                                       ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                                       ;
; RDSYNC_DELAYPIPE        ; 4           ; Integer                                                                                                       ;
; WRSYNC_DELAYPIPE        ; 4           ; Integer                                                                                                       ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                                       ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                                       ;
; CBXI_PARAMETER          ; dcfifo_e6c1 ; Untyped                                                                                                       ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL ;
+----------------+---------------------+-------------------------------------------------------------------+
; Parameter Name ; Value               ; Type                                                              ;
+----------------+---------------------+-------------------------------------------------------------------+
; RAM_SIZE       ; 1001011000000000000 ; Binary                                                            ;
+----------------+---------------------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0 ;
+----------------+-------+---------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------+
; H_SYNC_CYC     ; 96    ; Integer                                                                                           ;
; H_SYNC_BACK    ; 48    ; Integer                                                                                           ;
; H_SYNC_ACT     ; 640   ; Integer                                                                                           ;
; H_SYNC_FRONT   ; 16    ; Integer                                                                                           ;
; H_SYNC_TOTAL   ; 800   ; Integer                                                                                           ;
; V_SYNC_CYC     ; 2     ; Integer                                                                                           ;
; V_SYNC_BACK    ; 32    ; Integer                                                                                           ;
; V_SYNC_ACT     ; 480   ; Integer                                                                                           ;
; V_SYNC_FRONT   ; 11    ; Integer                                                                                           ;
; V_SYNC_TOTAL   ; 525   ; Integer                                                                                           ;
; X_START        ; 148   ; Integer                                                                                           ;
; Y_START        ; 34    ; Integer                                                                                           ;
+----------------+-------+---------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                                                        ;
+------------------------------------+-----------------+-------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                                                                                                     ;
; WIDTH_A                            ; 1               ; Integer                                                                                                     ;
; WIDTHAD_A                          ; 19              ; Integer                                                                                                     ;
; NUMWORDS_A                         ; 307200          ; Integer                                                                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                                                     ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                                                     ;
; WIDTH_B                            ; 8               ; Integer                                                                                                     ;
; WIDTHAD_B                          ; 16              ; Integer                                                                                                     ;
; NUMWORDS_B                         ; 38400           ; Integer                                                                                                     ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                                                     ;
; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                                                     ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                                                     ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                                                                                                     ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                                                                     ;
; RAM_BLOCK_TYPE                     ; M4K             ; Untyped                                                                                                     ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                                                     ;
; INIT_FILE                          ; Img_DATA.hex    ; Untyped                                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_B          ; Untyped                                                                                                     ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_q7o1 ; Untyped                                                                                                     ;
+------------------------------------+-----------------+-------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data ;
+----------------+--------+-----------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                              ;
+----------------+--------+-----------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                            ;
+----------------+--------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                           ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                        ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                   ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                 ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                                                                        ;
; WIDTH_A                            ; 32              ; Integer                                                                        ;
; WIDTHAD_A                          ; 10              ; Integer                                                                        ;
; NUMWORDS_A                         ; 1024            ; Integer                                                                        ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                        ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                        ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WIDTH_B                            ; 32              ; Integer                                                                        ;
; WIDTHAD_B                          ; 10              ; Integer                                                                        ;
; NUMWORDS_B                         ; 1024            ; Integer                                                                        ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                        ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                        ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                        ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                        ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                        ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                        ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                        ;
; MAXIMUM_DEPTH                      ; 0               ; Integer                                                                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                        ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                        ;
; CBXI_PARAMETER                     ; altsyncram_cub1 ; Untyped                                                                        ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag ;
+----------------+----------------------+-------------------------------------------------------------------+
; Parameter Name ; Value                ; Type                                                              ;
+----------------+----------------------+-------------------------------------------------------------------+
; lpm_file       ; cpu_0_ic_tag_ram.mif ; String                                                            ;
+----------------+----------------------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                    ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                 ;
; WIDTH_A                            ; 20                   ; Integer                                                                 ;
; WIDTHAD_A                          ; 7                    ; Integer                                                                 ;
; NUMWORDS_A                         ; 128                  ; Integer                                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                 ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_B                            ; 20                   ; Integer                                                                 ;
; WIDTHAD_B                          ; 7                    ; Integer                                                                 ;
; NUMWORDS_B                         ; 128                  ; Integer                                                                 ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                 ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                 ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                 ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                 ;
; INIT_FILE                          ; cpu_0_ic_tag_ram.mif ; Untyped                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                 ;
; MAXIMUM_DEPTH                      ; 0                    ; Integer                                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                 ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_tke1      ; Untyped                                                                 ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht ;
+----------------+-------------------+----------------------------------------------------------------+
; Parameter Name ; Value             ; Type                                                           ;
+----------------+-------------------+----------------------------------------------------------------+
; lpm_file       ; cpu_0_bht_ram.mif ; String                                                         ;
+----------------+-------------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram ;
+------------------------------------+-------------------+----------------------------------------------------------------------+
; Parameter Name                     ; Value             ; Type                                                                 ;
+------------------------------------+-------------------+----------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                 ; Untyped                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                ; AUTO_CARRY                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF               ; IGNORE_CARRY                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                ; AUTO_CASCADE                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF               ; IGNORE_CASCADE                                                       ;
; OPERATION_MODE                     ; DUAL_PORT         ; Untyped                                                              ;
; WIDTH_A                            ; 2                 ; Integer                                                              ;
; WIDTHAD_A                          ; 8                 ; Integer                                                              ;
; NUMWORDS_A                         ; 256               ; Integer                                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED      ; Untyped                                                              ;
; ADDRESS_ACLR_A                     ; NONE              ; Untyped                                                              ;
; OUTDATA_ACLR_A                     ; NONE              ; Untyped                                                              ;
; WRCONTROL_ACLR_A                   ; NONE              ; Untyped                                                              ;
; INDATA_ACLR_A                      ; NONE              ; Untyped                                                              ;
; BYTEENA_ACLR_A                     ; NONE              ; Untyped                                                              ;
; WIDTH_B                            ; 2                 ; Integer                                                              ;
; WIDTHAD_B                          ; 8                 ; Integer                                                              ;
; NUMWORDS_B                         ; 256               ; Integer                                                              ;
; INDATA_REG_B                       ; CLOCK1            ; Untyped                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1            ; Untyped                                                              ;
; RDCONTROL_REG_B                    ; CLOCK1            ; Untyped                                                              ;
; ADDRESS_REG_B                      ; CLOCK1            ; Untyped                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED      ; Untyped                                                              ;
; BYTEENA_REG_B                      ; CLOCK1            ; Untyped                                                              ;
; INDATA_ACLR_B                      ; NONE              ; Untyped                                                              ;
; WRCONTROL_ACLR_B                   ; NONE              ; Untyped                                                              ;
; ADDRESS_ACLR_B                     ; NONE              ; Untyped                                                              ;
; OUTDATA_ACLR_B                     ; NONE              ; Untyped                                                              ;
; RDCONTROL_ACLR_B                   ; NONE              ; Untyped                                                              ;
; BYTEENA_ACLR_B                     ; NONE              ; Untyped                                                              ;
; WIDTH_BYTEENA_A                    ; 1                 ; Untyped                                                              ;
; WIDTH_BYTEENA_B                    ; 1                 ; Untyped                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO              ; Untyped                                                              ;
; BYTE_SIZE                          ; 8                 ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA          ; Untyped                                                              ;
; INIT_FILE                          ; cpu_0_bht_ram.mif ; Untyped                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A            ; Untyped                                                              ;
; MAXIMUM_DEPTH                      ; 0                 ; Integer                                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL            ; Untyped                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL            ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL            ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL            ; Untyped                                                              ;
; DEVICE_FAMILY                      ; Cyclone II        ; Untyped                                                              ;
; CBXI_PARAMETER                     ; altsyncram_q8e1   ; Untyped                                                              ;
+------------------------------------+-------------------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                                  ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_a.mif ; String                                                                                ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value              ; Type                                                                                        ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                  ; Untyped                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                 ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                 ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                ; IGNORE_CASCADE                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT          ; Untyped                                                                                     ;
; WIDTH_A                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_A                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_A                         ; 32                 ; Integer                                                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED       ; Untyped                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE               ; Untyped                                                                                     ;
; INDATA_ACLR_A                      ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_B                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_B                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_B                         ; 32                 ; Integer                                                                                     ;
; INDATA_REG_B                       ; CLOCK1             ; Untyped                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1             ; Untyped                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1             ; Untyped                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED       ; Untyped                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; INDATA_ACLR_B                      ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_BYTEENA_A                    ; 1                  ; Untyped                                                                                     ;
; WIDTH_BYTEENA_B                    ; 1                  ; Untyped                                                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO               ; Untyped                                                                                     ;
; BYTE_SIZE                          ; 8                  ; Untyped                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA           ; Untyped                                                                                     ;
; INIT_FILE                          ; cpu_0_rf_ram_a.mif ; Untyped                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A             ; Untyped                                                                                     ;
; MAXIMUM_DEPTH                      ; 0                  ; Integer                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL             ; Untyped                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone II         ; Untyped                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_4be1    ; Untyped                                                                                     ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                                  ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_b.mif ; String                                                                                ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value              ; Type                                                                                        ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                  ; Untyped                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                 ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                 ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                ; IGNORE_CASCADE                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT          ; Untyped                                                                                     ;
; WIDTH_A                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_A                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_A                         ; 32                 ; Integer                                                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED       ; Untyped                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE               ; Untyped                                                                                     ;
; INDATA_ACLR_A                      ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_B                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_B                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_B                         ; 32                 ; Integer                                                                                     ;
; INDATA_REG_B                       ; CLOCK1             ; Untyped                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1             ; Untyped                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1             ; Untyped                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED       ; Untyped                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; INDATA_ACLR_B                      ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_BYTEENA_A                    ; 1                  ; Untyped                                                                                     ;
; WIDTH_BYTEENA_B                    ; 1                  ; Untyped                                                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO               ; Untyped                                                                                     ;
; BYTE_SIZE                          ; 8                  ; Untyped                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA           ; Untyped                                                                                     ;
; INIT_FILE                          ; cpu_0_rf_ram_b.mif ; Untyped                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A             ; Untyped                                                                                     ;
; MAXIMUM_DEPTH                      ; 0                  ; Integer                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL             ; Untyped                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone II         ; Untyped                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_5be1    ; Untyped                                                                                     ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag ;
+----------------+----------------------+-------------------------------------------------------------------+
; Parameter Name ; Value                ; Type                                                              ;
+----------------+----------------------+-------------------------------------------------------------------+
; lpm_file       ; cpu_0_dc_tag_ram.mif ; String                                                            ;
+----------------+----------------------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                    ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                          ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                 ;
; WIDTH_A                            ; 15                   ; Integer                                                                 ;
; WIDTHAD_A                          ; 9                    ; Integer                                                                 ;
; NUMWORDS_A                         ; 512                  ; Integer                                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                 ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_B                            ; 15                   ; Integer                                                                 ;
; WIDTHAD_B                          ; 9                    ; Integer                                                                 ;
; NUMWORDS_B                         ; 512                  ; Integer                                                                 ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                 ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                 ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                 ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                 ;
; INIT_FILE                          ; cpu_0_dc_tag_ram.mif ; Untyped                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                 ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                 ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_vf22      ; Untyped                                                                 ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data ;
+----------------+--------+-----------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                              ;
+----------------+--------+-----------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                            ;
+----------------+--------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                           ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                        ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                   ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                 ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                        ;
; WIDTH_A                            ; 32              ; Integer                                                                        ;
; WIDTHAD_A                          ; 9               ; Integer                                                                        ;
; NUMWORDS_A                         ; 512             ; Integer                                                                        ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                        ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                        ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WIDTH_B                            ; 32              ; Integer                                                                        ;
; WIDTHAD_B                          ; 9               ; Integer                                                                        ;
; NUMWORDS_B                         ; 512             ; Integer                                                                        ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                        ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                        ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                        ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                        ;
; WIDTH_BYTEENA_B                    ; 4               ; Integer                                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                        ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA        ; Untyped                                                                        ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                        ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                        ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                        ;
; CBXI_PARAMETER                     ; altsyncram_a422 ; Untyped                                                                        ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; Parameter Name                        ; Value         ; Type                                                                                    ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON            ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS                  ; OFF           ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS                   ; ON            ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS                ; OFF           ; IGNORE_CASCADE                                                                          ;
; NUMBER_OF_MULTIPLIERS                 ; 1             ; Integer                                                                                 ;
; WIDTH_A                               ; 16            ; Integer                                                                                 ;
; WIDTH_B                               ; 16            ; Integer                                                                                 ;
; WIDTH_RESULT                          ; 32            ; Integer                                                                                 ;
; INPUT_REGISTER_A0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_A0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A0                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A1                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A2                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A3                       ; DATAA         ; Untyped                                                                                 ;
; REPRESENTATION_A                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_A                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_A                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0         ; Untyped                                                                                 ;
; INPUT_REGISTER_B0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_B0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B0                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B1                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B2                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B3                       ; DATAB         ; Untyped                                                                                 ;
; REPRESENTATION_B                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_B                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_B                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER0                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR0                      ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER1                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR1                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER1_DIRECTION                 ; ADD           ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED  ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER2                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR2                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER3                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR3                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER3_DIRECTION                 ; UNUSED        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER01_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER01_SATURATION               ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_SATURATION               ; NO            ; Untyped                                                                                 ;
; ADDER1_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; ADDER3_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; PORT_MULT0_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT1_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT2_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT3_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; MULT01_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT23_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT01_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; MULT23_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; PORT_SIGNA                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; PORT_SIGNB                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; OUTPUT_REGISTER                       ; UNREGISTERED  ; Untyped                                                                                 ;
; OUTPUT_ACLR                           ; ACLR0         ; Untyped                                                                                 ;
; EXTRA_LATENCY                         ; 0             ; Untyped                                                                                 ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES           ; Untyped                                                                                 ;
; DSP_BLOCK_BALANCING                   ; AUTO          ; Untyped                                                                                 ;
; CBXI_PARAMETER                        ; mult_add_4cr2 ; Untyped                                                                                 ;
; DEVICE_FAMILY                         ; Cyclone II    ; Untyped                                                                                 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; Parameter Name                        ; Value         ; Type                                                                                    ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON            ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS                  ; OFF           ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS                   ; ON            ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS                ; OFF           ; IGNORE_CASCADE                                                                          ;
; NUMBER_OF_MULTIPLIERS                 ; 1             ; Integer                                                                                 ;
; WIDTH_A                               ; 16            ; Integer                                                                                 ;
; WIDTH_B                               ; 16            ; Integer                                                                                 ;
; WIDTH_RESULT                          ; 16            ; Integer                                                                                 ;
; INPUT_REGISTER_A0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_A0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A0                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A1                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A2                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A3                       ; DATAA         ; Untyped                                                                                 ;
; REPRESENTATION_A                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_A                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_A                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0         ; Untyped                                                                                 ;
; INPUT_REGISTER_B0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_B0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B0                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B1                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B2                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B3                       ; DATAB         ; Untyped                                                                                 ;
; REPRESENTATION_B                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_B                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_B                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER0                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR0                      ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER1                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR1                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER1_DIRECTION                 ; ADD           ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED  ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER2                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR2                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER3                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR3                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER3_DIRECTION                 ; UNUSED        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER01_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER01_SATURATION               ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_SATURATION               ; NO            ; Untyped                                                                                 ;
; ADDER1_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; ADDER3_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; PORT_MULT0_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT1_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT2_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT3_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; MULT01_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT23_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT01_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; MULT23_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; PORT_SIGNA                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; PORT_SIGNB                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; OUTPUT_REGISTER                       ; UNREGISTERED  ; Untyped                                                                                 ;
; OUTPUT_ACLR                           ; ACLR0         ; Untyped                                                                                 ;
; EXTRA_LATENCY                         ; 0             ; Untyped                                                                                 ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES           ; Untyped                                                                                 ;
; DSP_BLOCK_BALANCING                   ; AUTO          ; Untyped                                                                                 ;
; CBXI_PARAMETER                        ; mult_add_6cr2 ; Untyped                                                                                 ;
; DEVICE_FAMILY                         ; Cyclone II    ; Untyped                                                                                 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value                             ; Type                                                                                                                                                                             ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_ociram_default_contents.mif ; String                                                                                                                                                                           ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                             ; Type                                                                                                                                                                                   ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                 ; Untyped                                                                                                                                                                                ;
; AUTO_CARRY_CHAINS                  ; ON                                ; AUTO_CARRY                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS               ; OFF                               ; IGNORE_CARRY                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS                ; ON                                ; AUTO_CASCADE                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF                               ; IGNORE_CASCADE                                                                                                                                                                         ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT                   ; Untyped                                                                                                                                                                                ;
; WIDTH_A                            ; 32                                ; Integer                                                                                                                                                                                ;
; WIDTHAD_A                          ; 8                                 ; Integer                                                                                                                                                                                ;
; NUMWORDS_A                         ; 256                               ; Integer                                                                                                                                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                                ;
; ADDRESS_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; OUTDATA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; WRCONTROL_ACLR_A                   ; NONE                              ; Untyped                                                                                                                                                                                ;
; INDATA_ACLR_A                      ; NONE                              ; Untyped                                                                                                                                                                                ;
; BYTEENA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; WIDTH_B                            ; 32                                ; Integer                                                                                                                                                                                ;
; WIDTHAD_B                          ; 8                                 ; Integer                                                                                                                                                                                ;
; NUMWORDS_B                         ; 256                               ; Integer                                                                                                                                                                                ;
; INDATA_REG_B                       ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; RDCONTROL_REG_B                    ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; ADDRESS_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; OUTDATA_REG_B                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                                ;
; BYTEENA_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; INDATA_ACLR_B                      ; NONE                              ; Untyped                                                                                                                                                                                ;
; WRCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                                ;
; ADDRESS_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; OUTDATA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; RDCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                                ;
; BYTEENA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; WIDTH_BYTEENA_A                    ; 4                                 ; Integer                                                                                                                                                                                ;
; WIDTH_BYTEENA_B                    ; 1                                 ; Untyped                                                                                                                                                                                ;
; RAM_BLOCK_TYPE                     ; AUTO                              ; Untyped                                                                                                                                                                                ;
; BYTE_SIZE                          ; 8                                 ; Untyped                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                          ; Untyped                                                                                                                                                                                ;
; INIT_FILE                          ; cpu_0_ociram_default_contents.mif ; Untyped                                                                                                                                                                                ;
; INIT_FILE_LAYOUT                   ; PORT_A                            ; Untyped                                                                                                                                                                                ;
; MAXIMUM_DEPTH                      ; 0                                 ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; DEVICE_FAMILY                      ; Cyclone II                        ; Untyped                                                                                                                                                                                ;
; CBXI_PARAMETER                     ; altsyncram_c572                   ; Untyped                                                                                                                                                                                ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                            ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                                          ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                                                                                                                                                         ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                                                                                                                                                      ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                                                                                                                                                 ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                                                                                                                                               ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                                                                                                                                                      ;
; WIDTH_A                            ; 36              ; Integer                                                                                                                                                                                                      ;
; WIDTHAD_A                          ; 7               ; Integer                                                                                                                                                                                                      ;
; NUMWORDS_A                         ; 128             ; Integer                                                                                                                                                                                                      ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                                                                                                                                                      ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                                                                                                                                                      ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                                                                                                                                                      ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WIDTH_B                            ; 36              ; Integer                                                                                                                                                                                                      ;
; WIDTHAD_B                          ; 7               ; Integer                                                                                                                                                                                                      ;
; NUMWORDS_B                         ; 128             ; Integer                                                                                                                                                                                                      ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                                                                                                                                                      ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                                                                                                                                                      ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                                                                                                                                                      ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                                                                                                                                                      ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                                                                                                                                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                                                                                                                                                      ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                                                                                                                                                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA        ; Untyped                                                                                                                                                                                                      ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                                                                                                                                                                      ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                                                                                                                                                      ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                                                                                                                                                      ;
; CBXI_PARAMETER                     ; altsyncram_e502 ; Untyped                                                                                                                                                                                                      ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1 ;
+----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value     ; Type                                                                                                                                                                                                     ;
+----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SLD_NODE_INFO  ; 286279168 ; Integer                                                                                                                                                                                                  ;
+----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom ;
+------------------------------------+------------------------------+---------------------------------------------------------+
; Parameter Name                     ; Value                        ; Type                                                    ;
+------------------------------------+------------------------------+---------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY                                            ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE                                          ;
; OPERATION_MODE                     ; ROM                          ; Untyped                                                 ;
; WIDTH_A                            ; 32                           ; Integer                                                 ;
; WIDTHAD_A                          ; 7                            ; Integer                                                 ;
; NUMWORDS_A                         ; 128                          ; Integer                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped                                                 ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped                                                 ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped                                                 ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped                                                 ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped                                                 ;
; WIDTH_B                            ; 1                            ; Untyped                                                 ;
; WIDTHAD_B                          ; 1                            ; Untyped                                                 ;
; NUMWORDS_B                         ; 1                            ; Untyped                                                 ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped                                                 ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped                                                 ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped                                                 ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped                                                 ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped                                                 ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped                                                 ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped                                                 ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped                                                 ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped                                                 ;
; BYTE_SIZE                          ; 8                            ; Integer                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped                                                 ;
; INIT_FILE                          ; epcs_controller_boot_rom.hex ; Untyped                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped                                                 ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped                                                 ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped                                                 ;
; CBXI_PARAMETER                     ; altsyncram_lo31              ; Untyped                                                 ;
+------------------------------------+------------------------------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                    ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                              ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                            ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                          ;
; lpm_width               ; 8           ; Integer                                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Integer                                                                                                 ;
; LPM_WIDTHU              ; 6           ; Integer                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                 ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                 ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                 ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                 ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                 ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                 ;
; USE_EAB                 ; ON          ; Untyped                                                                                                 ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                 ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                                 ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                 ;
; CBXI_PARAMETER          ; scfifo_1n21 ; Untyped                                                                                                 ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                    ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                              ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                            ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                          ;
; lpm_width               ; 8           ; Integer                                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Integer                                                                                                 ;
; LPM_WIDTHU              ; 6           ; Integer                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                 ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                 ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                 ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                 ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                 ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                 ;
; USE_EAB                 ; ON          ; Untyped                                                                                                 ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                 ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                                 ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                 ;
; CBXI_PARAMETER          ; scfifo_1n21 ; Untyped                                                                                                 ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic ;
+-------------------+----------------------------------+-------------------------------------------------------------------------------+
; Parameter Name    ; Value                            ; Type                                                                          ;
+-------------------+----------------------------------+-------------------------------------------------------------------------------+
; INSTANCE_ID       ; 0                                ; Integer                                                                       ;
; SLD_NODE_INFO     ; 00001100000000000110111000000000 ; Binary                                                                        ;
; LOG2_TXFIFO_DEPTH ; 6                                ; Integer                                                                       ;
; LOG2_RXFIFO_DEPTH ; 6                                ; Integer                                                                       ;
; RESERVED          ; 0                                ; Integer                                                                       ;
; DATA_WIDTH        ; 8                                ; Integer                                                                       ;
; NODE_IR_WIDTH     ; 1                                ; Integer                                                                       ;
; SCAN_LENGTH       ; 11                               ; Integer                                                                       ;
+-------------------+----------------------------------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_AV_Config:u1 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; CLK_Freq       ; 50000000 ; Integer                           ;
; I2C_Freq       ; 20000    ; Integer                           ;
; LUT_SIZE       ; 51       ; Integer                           ;
; Dummy_DATA     ; 0        ; Integer                           ;
; SET_LIN_L      ; 1        ; Integer                           ;
; SET_LIN_R      ; 2        ; Integer                           ;
; SET_HEAD_L     ; 3        ; Integer                           ;
; SET_HEAD_R     ; 4        ; Integer                           ;
; A_PATH_CTRL    ; 5        ; Integer                           ;
; D_PATH_CTRL    ; 6        ; Integer                           ;
; POWER_ON       ; 7        ; Integer                           ;
; SET_FORMAT     ; 8        ; Integer                           ;
; SAMPLE_CTRL    ; 9        ; Integer                           ;
; SET_ACTIVE     ; 10       ; Integer                           ;
; SET_VIDEO      ; 11       ; Integer                           ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst                                 ;
+--------------------------+------------------------------------------------------------------+---------+
; Parameter Name           ; Value                                                            ; Type    ;
+--------------------------+------------------------------------------------------------------+---------+
; sld_hub_ip_version       ; 1                                                                ; Untyped ;
; sld_hub_ip_minor_version ; 3                                                                ; Untyped ;
; sld_common_ip_version    ; 0                                                                ; Untyped ;
; device_family            ; Cyclone II                                                       ; Untyped ;
; n_nodes                  ; 2                                                                ; Untyped ;
; n_sel_bits               ; 2                                                                ; Untyped ;
; n_node_ir_bits           ; 5                                                                ; Untyped ;
; node_info                ; 0000110000000000011011100000000000010001000100000100011000000000 ; Binary  ;
; compilation_mode         ; 0                                                                ; Untyped ;
+--------------------------+------------------------------------------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u1|altsyncram:Ram0_rtl_0 ;
+------------------------------------+------------------+---------------------------------+
; Parameter Name                     ; Value            ; Type                            ;
+------------------------------------+------------------+---------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                ; Untyped                         ;
; AUTO_CARRY_CHAINS                  ; ON               ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS               ; OFF              ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS                ; ON               ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF              ; IGNORE_CASCADE                  ;
; OPERATION_MODE                     ; ROM              ; Untyped                         ;
; WIDTH_A                            ; 16               ; Untyped                         ;
; WIDTHAD_A                          ; 6                ; Untyped                         ;
; NUMWORDS_A                         ; 64               ; Untyped                         ;
; OUTDATA_REG_A                      ; UNREGISTERED     ; Untyped                         ;
; ADDRESS_ACLR_A                     ; NONE             ; Untyped                         ;
; OUTDATA_ACLR_A                     ; NONE             ; Untyped                         ;
; WRCONTROL_ACLR_A                   ; NONE             ; Untyped                         ;
; INDATA_ACLR_A                      ; NONE             ; Untyped                         ;
; BYTEENA_ACLR_A                     ; NONE             ; Untyped                         ;
; WIDTH_B                            ; 1                ; Untyped                         ;
; WIDTHAD_B                          ; 1                ; Untyped                         ;
; NUMWORDS_B                         ; 1                ; Untyped                         ;
; INDATA_REG_B                       ; CLOCK1           ; Untyped                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1           ; Untyped                         ;
; RDCONTROL_REG_B                    ; CLOCK1           ; Untyped                         ;
; ADDRESS_REG_B                      ; CLOCK1           ; Untyped                         ;
; OUTDATA_REG_B                      ; UNREGISTERED     ; Untyped                         ;
; BYTEENA_REG_B                      ; CLOCK1           ; Untyped                         ;
; INDATA_ACLR_B                      ; NONE             ; Untyped                         ;
; WRCONTROL_ACLR_B                   ; NONE             ; Untyped                         ;
; ADDRESS_ACLR_B                     ; NONE             ; Untyped                         ;
; OUTDATA_ACLR_B                     ; NONE             ; Untyped                         ;
; RDCONTROL_ACLR_B                   ; NONE             ; Untyped                         ;
; BYTEENA_ACLR_B                     ; NONE             ; Untyped                         ;
; WIDTH_BYTEENA_A                    ; 1                ; Untyped                         ;
; WIDTH_BYTEENA_B                    ; 1                ; Untyped                         ;
; RAM_BLOCK_TYPE                     ; AUTO             ; Untyped                         ;
; BYTE_SIZE                          ; 8                ; Untyped                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE        ; Untyped                         ;
; INIT_FILE                          ; DE2_WEB0.rtl.mif ; Untyped                         ;
; INIT_FILE_LAYOUT                   ; PORT_A           ; Untyped                         ;
; MAXIMUM_DEPTH                      ; 0                ; Untyped                         ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL           ; Untyped                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL           ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL           ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL           ; Untyped                         ;
; DEVICE_FAMILY                      ; Cyclone II       ; Untyped                         ;
; CBXI_PARAMETER                     ; altsyncram_ocv   ; Untyped                         ;
+------------------------------------+------------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                                                                                          ;
+----------------------------+----------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                    ;
+----------------------------+----------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 1                                                                                                        ;
; Entity Instance            ; system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                                                                               ;
;     -- LPM_WIDTH           ; 16                                                                                                       ;
;     -- LPM_NUMWORDS        ; 256                                                                                                      ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                      ;
;     -- USE_EAB             ; ON                                                                                                       ;
+----------------------------+----------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                                    ;
+----------------------------+----------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                              ;
+----------------------------+----------------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                                  ;
; Entity Instance            ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                                       ;
;     -- lpm_width           ; 8                                                                                                  ;
;     -- LPM_NUMWORDS        ; 64                                                                                                 ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                ;
;     -- USE_EAB             ; ON                                                                                                 ;
; Entity Instance            ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                                       ;
;     -- lpm_width           ; 8                                                                                                  ;
;     -- LPM_NUMWORDS        ; 64                                                                                                 ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                ;
;     -- USE_EAB             ; ON                                                                                                 ;
+----------------------------+----------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; altmult_add Parameter Settings by Entity Instance                                                                                          ;
+---------------------------------------+----------------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                              ;
+---------------------------------------+----------------------------------------------------------------------------------------------------+
; Number of entity instances            ; 2                                                                                                  ;
; Entity Instance                       ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                  ;
;     -- WIDTH_A                        ; 16                                                                                                 ;
;     -- WIDTH_B                        ; 16                                                                                                 ;
;     -- WIDTH_RESULT                   ; 32                                                                                                 ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                           ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                           ;
;     -- PORT_SIGNA                     ; PORT_UNUSED                                                                                        ;
;     -- PORT_SIGNB                     ; PORT_UNUSED                                                                                        ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                ;
; Entity Instance                       ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                  ;
;     -- WIDTH_A                        ; 16                                                                                                 ;
;     -- WIDTH_B                        ; 16                                                                                                 ;
;     -- WIDTH_RESULT                   ; 16                                                                                                 ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                           ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                           ;
;     -- PORT_SIGNA                     ; PORT_UNUSED                                                                                        ;
;     -- PORT_SIGNB                     ; PORT_UNUSED                                                                                        ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                ;
+---------------------------------------+----------------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Jul 25 22:41:47 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_WEB -c DE2_WEB
Info: Found 1 design units, including 1 entities, in source file Audio_0.v
    Info: Found entity 1: Audio_0
Info: Found 1 design units, including 1 entities, in source file AUDIO_DAC_FIFO.v
    Info: Found entity 1: AUDIO_DAC_FIFO
Info: Found 1 design units, including 1 entities, in source file Audio_PLL.v
    Info: Found entity 1: Audio_PLL
Info: Found 1 design units, including 1 entities, in source file button_pio.v
    Info: Found entity 1: button_pio
Info: Found 29 design units, including 29 entities, in source file cpu_0.v
    Info: Found entity 1: cpu_0_ic_data_module
    Info: Found entity 2: cpu_0_ic_tag_module
    Info: Found entity 3: cpu_0_bht_module
    Info: Found entity 4: cpu_0_register_bank_a_module
    Info: Found entity 5: cpu_0_register_bank_b_module
    Info: Found entity 6: cpu_0_dc_tag_module
    Info: Found entity 7: cpu_0_dc_data_module
    Info: Found entity 8: cpu_0_nios2_oci_debug
    Info: Found entity 9: cpu_0_ociram_lpm_dram_bdp_component_module
    Info: Found entity 10: cpu_0_nios2_ocimem
    Info: Found entity 11: cpu_0_nios2_avalon_reg
    Info: Found entity 12: cpu_0_nios2_oci_break
    Info: Found entity 13: cpu_0_nios2_oci_xbrk
    Info: Found entity 14: cpu_0_nios2_oci_match_paired
    Info: Found entity 15: cpu_0_nios2_oci_match_single
    Info: Found entity 16: cpu_0_nios2_oci_dbrk
    Info: Found entity 17: cpu_0_nios2_oci_itrace
    Info: Found entity 18: cpu_0_nios2_oci_td_mode
    Info: Found entity 19: cpu_0_nios2_oci_dtrace
    Info: Found entity 20: cpu_0_nios2_oci_compute_tm_count
    Info: Found entity 21: cpu_0_nios2_oci_fifowp_inc
    Info: Found entity 22: cpu_0_nios2_oci_fifocount_inc
    Info: Found entity 23: cpu_0_nios2_oci_fifo
    Info: Found entity 24: cpu_0_nios2_oci_pib
    Info: Found entity 25: cpu_0_traceram_lpm_dram_bdp_component_module
    Info: Found entity 26: cpu_0_nios2_oci_im
    Info: Found entity 27: cpu_0_nios2_performance_monitors
    Info: Found entity 28: cpu_0_nios2_oci
    Info: Found entity 29: cpu_0
Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module.v
    Info: Found entity 1: cpu_0_jtag_debug_module
Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module_wrapper.v
    Info: Found entity 1: cpu_0_jtag_debug_module_wrapper
Info: Found 1 design units, including 1 entities, in source file cpu_0_mult_cell.v
    Info: Found entity 1: cpu_0_mult_cell
Info: Found 1 design units, including 1 entities, in source file cpu_0_test_bench.v
    Info: Found entity 1: cpu_0_test_bench
Info: Found 1 design units, including 1 entities, in source file DE2_WEB.v
    Info: Found entity 1: DE2_WEB
Info: Found 1 design units, including 1 entities, in source file DM9000A.v
    Info: Found entity 1: DM9000A
Info: Found 1 design units, including 1 entities, in source file DM9000A_IF.v
    Info: Found entity 1: DM9000A_IF
Info: Found 3 design units, including 3 entities, in source file epcs_controller.v
    Info: Found entity 1: epcs_controller_sub
    Info: Found entity 2: tornado_epcs_controller_atom
    Info: Found entity 3: epcs_controller
Info: Found 1 design units, including 1 entities, in source file FIFO_16_256.v
    Info: Found entity 1: FIFO_16_256
Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v
    Info: Found entity 1: I2C_AV_Config
Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Info: Found 1 design units, including 1 entities, in source file Img_RAM.v
    Info: Found entity 1: Img_RAM
Info: Found 1 design units, including 1 entities, in source file ISP1362.v
    Info: Found entity 1: ISP1362
Info: Found 1 design units, including 1 entities, in source file ISP1362_IF.v
    Info: Found entity 1: ISP1362_IF
Info: Found 7 design units, including 7 entities, in source file jtag_uart_0.v
    Info: Found entity 1: jtag_uart_0_log_module
    Info: Found entity 2: jtag_uart_0_sim_scfifo_w
    Info: Found entity 3: jtag_uart_0_scfifo_w
    Info: Found entity 4: jtag_uart_0_drom_module
    Info: Found entity 5: jtag_uart_0_sim_scfifo_r
    Info: Found entity 6: jtag_uart_0_scfifo_r
    Info: Found entity 7: jtag_uart_0
Info: Found 1 design units, including 1 entities, in source file lcd_16207_0.v
    Info: Found entity 1: lcd_16207_0
Info: Found 1 design units, including 1 entities, in source file led_green.v
    Info: Found entity 1: led_green
Info: Found 1 design units, including 1 entities, in source file led_red.v
    Info: Found entity 1: led_red
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Info: Found 1 design units, including 1 entities, in source file SD_CLK.v
    Info: Found entity 1: SD_CLK
Info: Found 1 design units, including 1 entities, in source file SD_CMD.v
    Info: Found entity 1: SD_CMD
Info: Found 1 design units, including 1 entities, in source file SD_DAT.v
    Info: Found entity 1: SD_DAT
Info: Found 2 design units, including 2 entities, in source file sdram_0.v
    Info: Found entity 1: sdram_0_input_efifo_module
    Info: Found entity 2: sdram_0
Info: Found 2 design units, including 2 entities, in source file sdram_0_test_component.v
    Info: Found entity 1: sdram_0_test_component_ram_module
    Info: Found entity 2: sdram_0_test_component
Info: Found 1 design units, including 1 entities, in source file SDRAM_PLL.v
    Info: Found entity 1: SDRAM_PLL
Info: Found 1 design units, including 1 entities, in source file SEG7_Display.v
    Info: Found entity 1: SEG7_Display
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
    Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v
    Info: Found entity 1: SEG7_LUT_8
Info: Found 1 design units, including 1 entities, in source file sram_0.v
    Info: Found entity 1: sram_0
Info: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.v
    Info: Found entity 1: SRAM_16Bit_512K
Info: Found 1 design units, including 1 entities, in source file switch_pio.v
    Info: Found entity 1: switch_pio
Info: Found 37 design units, including 37 entities, in source file system_0.v
    Info: Found entity 1: Audio_0_avalon_slave_0_arbitrator
    Info: Found entity 2: DM9000A_avalon_slave_0_arbitrator
    Info: Found entity 3: ISP1362_avalon_slave_0_arbitrator
    Info: Found entity 4: ISP1362_avalon_slave_1_arbitrator
    Info: Found entity 5: SD_CLK_s1_arbitrator
    Info: Found entity 6: SD_CMD_s1_arbitrator
    Info: Found entity 7: SD_DAT_s1_arbitrator
    Info: Found entity 8: SEG7_Display_avalon_slave_0_arbitrator
    Info: Found entity 9: VGA_0_avalon_slave_0_arbitrator
    Info: Found entity 10: button_pio_s1_arbitrator
    Info: Found entity 11: clock_0_in_arbitrator
    Info: Found entity 12: clock_0_out_arbitrator
    Info: Found entity 13: clock_1_in_arbitrator
    Info: Found entity 14: clock_1_out_arbitrator
    Info: Found entity 15: cpu_0_jtag_debug_module_arbitrator
    Info: Found entity 16: cpu_0_data_master_arbitrator
    Info: Found entity 17: cpu_0_instruction_master_arbitrator
    Info: Found entity 18: epcs_controller_epcs_control_port_arbitrator
    Info: Found entity 19: jtag_uart_0_avalon_jtag_slave_arbitrator
    Info: Found entity 20: lcd_16207_0_control_slave_arbitrator
    Info: Found entity 21: led_green_s1_arbitrator
    Info: Found entity 22: led_red_s1_arbitrator
    Info: Found entity 23: rdv_fifo_for_clock_0_out_to_sdram_0_s1_module
    Info: Found entity 24: rdv_fifo_for_clock_1_out_to_sdram_0_s1_module
    Info: Found entity 25: sdram_0_s1_arbitrator
    Info: Found entity 26: sram_0_avalon_slave_0_arbitrator
    Info: Found entity 27: switch_pio_s1_arbitrator
    Info: Found entity 28: timer_0_s1_arbitrator
    Info: Found entity 29: timer_1_s1_arbitrator
    Info: Found entity 30: tri_state_bridge_0_avalon_slave_arbitrator
    Info: Found entity 31: tri_state_bridge_0_bridge_arbitrator
    Info: Found entity 32: uart_0_s1_arbitrator
    Info: Found entity 33: system_0_reset_clk_domain_synch_module
    Info: Found entity 34: system_0_reset_clk_50_domain_synch_module
    Info: Found entity 35: system_0
    Info: Found entity 36: cfi_flash_0_lane0_module
    Info: Found entity 37: cfi_flash_0
Info: Found 1 design units, including 1 entities, in source file timer_0.v
    Info: Found entity 1: timer_0
Info: Found 1 design units, including 1 entities, in source file timer_1.v
    Info: Found entity 1: timer_1
Info: Found 7 design units, including 7 entities, in source file uart_0.v
    Info: Found entity 1: uart_0_log_module
    Info: Found entity 2: uart_0_tx
    Info: Found entity 3: uart_0_rx_stimulus_source_character_source_rom_module
    Info: Found entity 4: uart_0_rx_stimulus_source
    Info: Found entity 5: uart_0_rx
    Info: Found entity 6: uart_0_regs
    Info: Found entity 7: uart_0
Info: Found 1 design units, including 1 entities, in source file VGA_0.v
    Info: Found entity 1: VGA_0
Info: Found 1 design units, including 1 entities, in source file VGA_Controller.v
    Info: Found entity 1: VGA_Controller
Info: Found 1 design units, including 1 entities, in source file VGA_NIOS_CTRL.v
    Info: Found entity 1: VGA_NIOS_CTRL
Info: Found 1 design units, including 1 entities, in source file VGA_OSD_RAM.v
    Info: Found entity 1: VGA_OSD_RAM
Info: Elaborating entity "DE2_WEB" for the top level hierarchy
Warning (10034): Output port "IRDA_TXD" at DE2_WEB.v(196) has no driver
Warning (10034): Output port "OTG_DACK0_N" at DE2_WEB.v(239) has no driver
Warning (10034): Output port "OTG_DACK1_N" at DE2_WEB.v(240) has no driver
Warning (10034): Output port "TDO" at DE2_WEB.v(263) has no driver
Warning (10665): Bidirectional port "AUD_DACLRCK" at DE2_WEB.v(285) has a one-way connection to bidirectional port "AUD_ADCLRCK"
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:delay1"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(18): truncated value with size 32 to match size of target (24)
Info: Elaborating entity "SDRAM_PLL" for hierarchy "SDRAM_PLL:PLL1"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "SDRAM_PLL:PLL1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "SDRAM_PLL:PLL1|altpll:altpll_component"
Info: Elaborating entity "Audio_PLL" for hierarchy "Audio_PLL:PLL2"
Info: Elaborating entity "altpll" for hierarchy "Audio_PLL:PLL2|altpll:altpll_component"
Info: Elaborated megafunction instantiation "Audio_PLL:PLL2|altpll:altpll_component"
Info: Elaborating entity "system_0" for hierarchy "system_0:u0"
Info: Elaborating entity "Audio_0_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|Audio_0_avalon_slave_0_arbitrator:the_Audio_0_avalon_slave_0"
Info: Elaborating entity "Audio_0" for hierarchy "system_0:u0|Audio_0:the_Audio_0"
Info: Elaborating entity "AUDIO_DAC_FIFO" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO"
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(67): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(90): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(98): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_FIFO.v(147): truncated value with size 32 to match size of target (4)
Warning (10034): Output port "oDATA[15]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[14]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[13]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[12]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[11]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[10]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[9]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[8]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[7]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[6]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[5]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[4]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[3]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[2]" at AUDIO_DAC_FIFO.v(22) has no driver
Warning (10034): Output port "oDATA[1]" at AUDIO_DAC_FIFO.v(22) has no driver
Info: Elaborating entity "FIFO_16_256" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/dcfifo.tdf
    Info: Found entity 1: dcfifo
Info: Elaborating entity "dcfifo" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component"
Info: Elaborated megafunction instantiation "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_e6c1.tdf
    Info: Found entity 1: dcfifo_e6c1
Info: Elaborating entity "dcfifo_e6c1" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_g86.tdf
    Info: Found entity 1: a_graycounter_g86
Info: Elaborating entity "a_graycounter_g86" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|a_graycounter_g86:rdptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_b17.tdf
    Info: Found entity 1: a_graycounter_b17
Info: Elaborating entity "a_graycounter_b17" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|a_graycounter_b17:wrptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_a17.tdf
    Info: Found entity 1: a_graycounter_a17
Info: Elaborating entity "a_graycounter_a17" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|a_graycounter_a17:wrptr_gp"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1731.tdf
    Info: Found entity 1: altsyncram_1731
Info: Elaborating entity "altsyncram_1731" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_brg1.tdf
    Info: Found entity 1: altsyncram_brg1
Info: Elaborating entity "altsyncram_brg1" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|altsyncram_1731:fifo_ram|altsyncram_brg1:altsyncram4"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_nc8.tdf
    Info: Found entity 1: alt_synch_pipe_nc8
Info: Elaborating entity "alt_synch_pipe_nc8" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf
    Info: Found entity 1: dffpipe_hd9
Info: Elaborating entity "dffpipe_hd9" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_nc8:rs_dgwp|dffpipe_hd9:dffpipe6"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_hn7.tdf
    Info: Found entity 1: alt_synch_pipe_hn7
Info: Elaborating entity "alt_synch_pipe_hn7" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_hn7:wrempty_reg"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_bo8.tdf
    Info: Found entity 1: dffpipe_bo8
Info: Elaborating entity "dffpipe_bo8" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_hn7:wrempty_reg|dffpipe_bo8:dffpipe9"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_oc8.tdf
    Info: Found entity 1: alt_synch_pipe_oc8
Info: Elaborating entity "alt_synch_pipe_oc8" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf
    Info: Found entity 1: dffpipe_id9
Info: Elaborating entity "dffpipe_id9" for hierarchy "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|alt_synch_pipe_oc8:ws_dgrp|dffpipe_id9:dffpipe11"
Info: Elaborating entity "DM9000A_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|DM9000A_avalon_slave_0_arbitrator:the_DM9000A_avalon_slave_0"
Info: Elaborating entity "DM9000A" for hierarchy "system_0:u0|DM9000A:the_DM9000A"
Info: Elaborating entity "DM9000A_IF" for hierarchy "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF"
Info: Elaborating entity "ISP1362_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|ISP1362_avalon_slave_0_arbitrator:the_ISP1362_avalon_slave_0"
Info: Elaborating entity "ISP1362_avalon_slave_1_arbitrator" for hierarchy "system_0:u0|ISP1362_avalon_slave_1_arbitrator:the_ISP1362_avalon_slave_1"
Info: Elaborating entity "ISP1362" for hierarchy "system_0:u0|ISP1362:the_ISP1362"
Info: Elaborating entity "ISP1362_IF" for hierarchy "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF"
Info: Elaborating entity "SD_CLK_s1_arbitrator" for hierarchy "system_0:u0|SD_CLK_s1_arbitrator:the_SD_CLK_s1"
Info: Elaborating entity "SD_CLK" for hierarchy "system_0:u0|SD_CLK:the_SD_CLK"
Info: Elaborating entity "SD_CMD_s1_arbitrator" for hierarchy "system_0:u0|SD_CMD_s1_arbitrator:the_SD_CMD_s1"
Info: Elaborating entity "SD_CMD" for hierarchy "system_0:u0|SD_CMD:the_SD_CMD"
Info: Elaborating entity "SD_DAT_s1_arbitrator" for hierarchy "system_0:u0|SD_DAT_s1_arbitrator:the_SD_DAT_s1"
Info: Elaborating entity "SD_DAT" for hierarchy "system_0:u0|SD_DAT:the_SD_DAT"
Info: Elaborating entity "SEG7_Display_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|SEG7_Display_avalon_slave_0_arbitrator:the_SEG7_Display_avalon_slave_0"
Info: Elaborating entity "SEG7_Display" for hierarchy "system_0:u0|SEG7_Display:the_SEG7_Display"
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8"
Info: Elaborating entity "SEG7_LUT" for hierarchy "system_0:u0|SEG7_Display:the_SEG7_Display|SEG7_LUT_8:the_SEG7_LUT_8|SEG7_LUT:u0"
Info: Elaborating entity "VGA_0_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|VGA_0_avalon_slave_0_arbitrator:the_VGA_0_avalon_slave_0"
Info: Elaborating entity "VGA_0" for hierarchy "system_0:u0|VGA_0:the_VGA_0"
Info: Elaborating entity "VGA_NIOS_CTRL" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL"
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(83): truncated value with size 16 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(84): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(85): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(86): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(87): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(88): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(89): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(90): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(91): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(92): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(93): truncated value with size 16 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_NIOS_CTRL.v(94): truncated value with size 16 to match size of target (10)
Info: Elaborating entity "VGA_Controller" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0"
Warning (10036): Verilog HDL or VHDL warning at VGA_Param.h(5): object "H_SYNC_FRONT" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at VGA_Param.h(11): object "V_SYNC_FRONT" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(79): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(82): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(100): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(101): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(102): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(161): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(187): truncated value with size 32 to match size of target (10)
Info: Elaborating entity "VGA_OSD_RAM" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1"
Info: Elaborating entity "Img_RAM" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q7o1.tdf
    Info: Found entity 1: altsyncram_q7o1
Info: Elaborating entity "altsyncram_q7o1" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_p132.tdf
    Info: Found entity 1: altsyncram_p132
Info: Elaborating entity "altsyncram_p132" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1"
Warning: Variable or input pin "clocken1" is defined but never used
Info: Found 1 design units, including 1 entities, in source file db/decode_1qa.tdf
    Info: Found entity 1: decode_1qa
Info: Elaborating entity "decode_1qa" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode3"
Info: Elaborating entity "decode_1qa" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|decode_1qa:decode_a"
Info: Found 1 design units, including 1 entities, in source file db/mux_hkb.tdf
    Info: Found entity 1: mux_hkb
Info: Elaborating entity "mux_hkb" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|mux_hkb:mux5"
Info: Found 1 design units, including 1 entities, in source file db/mux_akb.tdf
    Info: Found entity 1: mux_akb
Info: Elaborating entity "mux_akb" for hierarchy "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_OSD_RAM:u1|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|mux_akb:mux6"
Info: Elaborating entity "button_pio_s1_arbitrator" for hierarchy "system_0:u0|button_pio_s1_arbitrator:the_button_pio_s1"
Info: Elaborating entity "button_pio" for hierarchy "system_0:u0|button_pio:the_button_pio"
Info: Elaborating entity "clock_0_in_arbitrator" for hierarchy "system_0:u0|clock_0_in_arbitrator:the_clock_0_in"
Info: Elaborating entity "clock_0_out_arbitrator" for hierarchy "system_0:u0|clock_0_out_arbitrator:the_clock_0_out"
Warning: Using design file clock_0.v, which is not specified as a design file for the current project, but contains definitions for 9 design units and 9 entities in project
    Info: Found entity 1: clock_0_master_read_done_sync_module
    Info: Found entity 2: clock_0_master_write_done_sync_module
    Info: Found entity 3: clock_0_edge_to_pulse
    Info: Found entity 4: clock_0_slave_FSM
    Info: Found entity 5: clock_0_slave_read_request_sync_module
    Info: Found entity 6: clock_0_slave_write_request_sync_module
    Info: Found entity 7: clock_0_master_FSM
    Info: Found entity 8: clock_0_bit_pipe
    Info: Found entity 9: clock_0
Info: Elaborating entity "clock_0" for hierarchy "system_0:u0|clock_0:the_clock_0"
Info: Elaborating entity "clock_0_master_read_done_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync"
Info: Elaborating entity "clock_0_master_write_done_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync"
Info: Elaborating entity "clock_0_edge_to_pulse" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "clock_0_slave_FSM" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM"
Info: Elaborating entity "clock_0_slave_read_request_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync"
Info: Elaborating entity "clock_0_slave_write_request_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync"
Info: Elaborating entity "clock_0_master_FSM" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM"
Info: Elaborating entity "clock_0_bit_pipe" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "clock_1_in_arbitrator" for hierarchy "system_0:u0|clock_1_in_arbitrator:the_clock_1_in"
Info: Elaborating entity "clock_1_out_arbitrator" for hierarchy "system_0:u0|clock_1_out_arbitrator:the_clock_1_out"
Warning: Using design file clock_1.v, which is not specified as a design file for the current project, but contains definitions for 9 design units and 9 entities in project
    Info: Found entity 1: clock_1_master_read_done_sync_module
    Info: Found entity 2: clock_1_master_write_done_sync_module
    Info: Found entity 3: clock_1_edge_to_pulse
    Info: Found entity 4: clock_1_slave_FSM
    Info: Found entity 5: clock_1_slave_read_request_sync_module
    Info: Found entity 6: clock_1_slave_write_request_sync_module
    Info: Found entity 7: clock_1_master_FSM
    Info: Found entity 8: clock_1_bit_pipe
    Info: Found entity 9: clock_1
Info: Elaborating entity "clock_1" for hierarchy "system_0:u0|clock_1:the_clock_1"
Info: Elaborating entity "clock_1_master_read_done_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync"
Info: Elaborating entity "clock_1_master_write_done_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync"
Info: Elaborating entity "clock_1_edge_to_pulse" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "clock_1_slave_FSM" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM"
Info: Elaborating entity "clock_1_slave_read_request_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync"
Info: Elaborating entity "clock_1_slave_write_request_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync"
Info: Elaborating entity "clock_1_master_FSM" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM"
Info: Elaborating entity "clock_1_bit_pipe" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "cpu_0_jtag_debug_module_arbitrator" for hierarchy "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module"
Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master"
Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master"
Info: Elaborating entity "cpu_0" for hierarchy "system_0:u0|cpu_0:the_cpu_0"
Info: Elaborating entity "cpu_0_test_bench" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
Info: Elaborating entity "cpu_0_ic_data_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cub1.tdf
    Info: Found entity 1: altsyncram_cub1
Info: Elaborating entity "altsyncram_cub1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_k1l1.tdf
    Info: Found entity 1: altsyncram_k1l1
Info: Elaborating entity "altsyncram_k1l1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1"
Info: Elaborating entity "cpu_0_ic_tag_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tke1.tdf
    Info: Found entity 1: altsyncram_tke1
Info: Elaborating entity "altsyncram_tke1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated"
Info: Elaborating entity "cpu_0_bht_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q8e1.tdf
    Info: Found entity 1: altsyncram_q8e1
Info: Elaborating entity "altsyncram_q8e1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pfn1.tdf
    Info: Found entity 1: altsyncram_pfn1
Info: Elaborating entity "altsyncram_pfn1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1"
Info: Elaborating entity "cpu_0_register_bank_a_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4be1.tdf
    Info: Found entity 1: altsyncram_4be1
Info: Elaborating entity "altsyncram_4be1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated"
Info: Elaborating entity "cpu_0_register_bank_b_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5be1.tdf
    Info: Found entity 1: altsyncram_5be1
Info: Elaborating entity "altsyncram_5be1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated"
Info: Elaborating entity "cpu_0_dc_tag_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vf22.tdf
    Info: Found entity 1: altsyncram_vf22
Info: Elaborating entity "altsyncram_vf22" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated"
Info: Elaborating entity "cpu_0_dc_data_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_a422.tdf
    Info: Found entity 1: altsyncram_a422
Info: Elaborating entity "altsyncram_a422" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated"
Info: Elaborating entity "cpu_0_mult_cell" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Elaborating entity "altmult_add" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_4cr2.tdf
    Info: Found entity 1: mult_add_4cr2
Info: Elaborating entity "mult_add_4cr2" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_2o81.tdf
    Info: Found entity 1: ded_mult_2o81
Info: Elaborating entity "ded_mult_2o81" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf
    Info: Found entity 1: dffpipe_93c
Info: Elaborating entity "dffpipe_93c" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result"
Info: Elaborating entity "altmult_add" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_6cr2.tdf
    Info: Found entity 1: mult_add_6cr2
Info: Elaborating entity "mult_add_6cr2" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated"
Info: Elaborating entity "cpu_0_nios2_oci" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci"
Info: Elaborating entity "cpu_0_nios2_oci_debug" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug"
Info: Elaborating entity "cpu_0_nios2_ocimem" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem"
Info: Elaborating entity "cpu_0_ociram_lpm_dram_bdp_component_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c572.tdf
    Info: Found entity 1: altsyncram_c572
Info: Elaborating entity "altsyncram_c572" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated"
Info: Elaborating entity "cpu_0_nios2_avalon_reg" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg"
Info: Elaborating entity "cpu_0_nios2_oci_break" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break"
Info: Elaborating entity "cpu_0_nios2_oci_xbrk" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk"
Info: Elaborating entity "cpu_0_nios2_oci_dbrk" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk"
Info: Elaborating entity "cpu_0_nios2_oci_match_paired" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired"
Info: Elaborating entity "cpu_0_nios2_oci_match_single" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single"
Info: Elaborating entity "cpu_0_nios2_oci_itrace" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace"
Info: Elaborating entity "cpu_0_nios2_oci_dtrace" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace"
Info: Elaborating entity "cpu_0_nios2_oci_td_mode" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode"
Info: Elaborating entity "cpu_0_nios2_oci_fifo" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo"
Info: Elaborating entity "cpu_0_nios2_oci_compute_tm_count" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count"
Info: Elaborating entity "cpu_0_nios2_oci_fifowp_inc" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp"
Info: Elaborating entity "cpu_0_nios2_oci_fifocount_inc" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount"
Info: Elaborating entity "cpu_0_nios2_oci_pib" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib"
Info: Elaborating entity "cpu_0_nios2_oci_im" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im"
Info: Elaborating entity "cpu_0_traceram_lpm_dram_bdp_component_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e502.tdf
    Info: Found entity 1: altsyncram_e502
Info: Elaborating entity "altsyncram_e502" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated"
Info: Elaborating entity "cpu_0_jtag_debug_module_wrapper" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper"
Info: Elaborating entity "cpu_0_jtag_debug_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1"
Info: Elaborating entity "epcs_controller_epcs_control_port_arbitrator" for hierarchy "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port"
Info: Elaborating entity "epcs_controller" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller"
Info: Elaborating entity "epcs_controller_sub" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|epcs_controller_sub:the_epcs_controller_sub"
Info: Elaborating entity "tornado_epcs_controller_atom" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|tornado_epcs_controller_atom:the_tornado_epcs_controller_atom"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom"
Info: Elaborated megafunction instantiation "system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lo31.tdf
    Info: Found entity 1: altsyncram_lo31
Info: Elaborating entity "altsyncram_lo31" for hierarchy "system_0:u0|epcs_controller:the_epcs_controller|altsyncram:the_boot_copier_rom|altsyncram_lo31:auto_generated"
Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_arbitrator" for hierarchy "system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"
Info: Elaborating entity "jtag_uart_0" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0"
Info: Elaborating entity "jtag_uart_0_scfifo_w" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_1n21.tdf
    Info: Found entity 1: scfifo_1n21
Info: Elaborating entity "scfifo_1n21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_8t21.tdf
    Info: Found entity 1: a_dpfifo_8t21
Info: Elaborating entity "a_dpfifo_8t21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_rj7.tdf
    Info: Found entity 1: cntr_rj7
Info: Elaborating entity "cntr_rj7" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_5h21.tdf
    Info: Found entity 1: dpram_5h21
Info: Elaborating entity "dpram_5h21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9tl1.tdf
    Info: Found entity 1: altsyncram_9tl1
Info: Elaborating entity "altsyncram_9tl1" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_dl8.tdf
    Info: Found entity 1: cntr_dl8
Info: Elaborating entity "cntr_dl8" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count"
Info: Elaborating entity "jtag_uart_0_scfifo_r" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v
    Info: Found entity 1: alt_jtag_atlantic
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborating entity "lcd_16207_0_control_slave_arbitrator" for hierarchy "system_0:u0|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave"
Info: Elaborating entity "lcd_16207_0" for hierarchy "system_0:u0|lcd_16207_0:the_lcd_16207_0"
Info: Elaborating entity "led_green_s1_arbitrator" for hierarchy "system_0:u0|led_green_s1_arbitrator:the_led_green_s1"
Info: Elaborating entity "led_green" for hierarchy "system_0:u0|led_green:the_led_green"
Info: Elaborating entity "led_red_s1_arbitrator" for hierarchy "system_0:u0|led_red_s1_arbitrator:the_led_red_s1"
Info: Elaborating entity "led_red" for hierarchy "system_0:u0|led_red:the_led_red"
Info: Elaborating entity "sdram_0_s1_arbitrator" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_clock_0_out_to_sdram_0_s1_module" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_clock_1_out_to_sdram_0_s1_module" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1"
Info: Elaborating entity "sdram_0" for hierarchy "system_0:u0|sdram_0:the_sdram_0"
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(352): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "sdram_0_input_efifo_module" for hierarchy "system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(67): ignoring full_case attribute on case statement with explicit default
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(93): ignoring full_case attribute on case statement with explicit default
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(129): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "sram_0_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0"
Info: Elaborating entity "sram_0" for hierarchy "system_0:u0|sram_0:the_sram_0"
Info: Elaborating entity "SRAM_16Bit_512K" for hierarchy "system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K"
Info: Elaborating entity "switch_pio_s1_arbitrator" for hierarchy "system_0:u0|switch_pio_s1_arbitrator:the_switch_pio_s1"
Info: Elaborating entity "switch_pio" for hierarchy "system_0:u0|switch_pio:the_switch_pio"
Info: Elaborating entity "timer_0_s1_arbitrator" for hierarchy "system_0:u0|timer_0_s1_arbitrator:the_timer_0_s1"
Info: Elaborating entity "timer_0" for hierarchy "system_0:u0|timer_0:the_timer_0"
Info: Elaborating entity "timer_1_s1_arbitrator" for hierarchy "system_0:u0|timer_1_s1_arbitrator:the_timer_1_s1"
Info: Elaborating entity "timer_1" for hierarchy "system_0:u0|timer_1:the_timer_1"
Info: Elaborating entity "tri_state_bridge_0_avalon_slave_arbitrator" for hierarchy "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave"
Info: Elaborating entity "uart_0_s1_arbitrator" for hierarchy "system_0:u0|uart_0_s1_arbitrator:the_uart_0_s1"
Info: Elaborating entity "uart_0" for hierarchy "system_0:u0|uart_0:the_uart_0"
Info: Elaborating entity "uart_0_tx" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_tx:the_uart_0_tx"
Info: Elaborating entity "uart_0_rx" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx"
Info: Elaborating entity "uart_0_rx_stimulus_source" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|uart_0_rx_stimulus_source:the_uart_0_rx_stimulus_source"
Info: Elaborating entity "uart_0_regs" for hierarchy "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs"
Info: Elaborating entity "system_0_reset_clk_domain_synch_module" for hierarchy "system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch"
Info: Elaborating entity "system_0_reset_clk_50_domain_synch_module" for hierarchy "system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u1"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(106): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u1|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Warning: Port "address_b" on the entity instantiation of "cpu_0_traceram_lpm_dram_bdp_component" is connected to a signal of width 17. The formal width of the signal in the module is 7.  Extra bits will be driven by GND.
Warning: Port "jdo" on the entity instantiation of "the_cpu_0_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit3_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit1_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "oci_ienable" on the entity instantiation of "the_cpu_0_nios2_oci" is connected to a signal of width 9. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic.
Warning: Port "iWR_DATA" on the entity instantiation of "u1" is connected to a signal of width 16. The formal width of the signal in the module is 1.  Extra bits will be driven by GND.
Warning: Port "oAddress" on the entity instantiation of "u0" is connected to a signal of width 19. The formal width of the signal in the module is 20.  Extra bits will be left dangling without any fanout logic.
Info: Found 6 design units, including 2 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_decode:instruction_decoder", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file db/decode_aoi.tdf
    Info: Found entity 1: decode_aoi
Info: Found 2 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:RESET", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRSR", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRF_ENA", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 2 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|uart_0:the_uart_0|uart_0_regs:the_uart_0_regs|readdata[15]" with stuck data_in port to stuck value GND
Info: Power-up level of register "system_0:u0|sdram_0:the_sdram_0|i_addr[5]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|i_addr[5]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|sdram_0:the_sdram_0|i_addr[4]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|i_addr[4]" with stuck data_in port to stuck value VCC
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[27]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[26]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[25]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[24]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[22]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[21]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[20]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[18]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|tracemem_tw" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break_pulse" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto0" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto1" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit1" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit2" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit3" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|E_xbrk_goto0" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|E_xbrk_goto1" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit0_latch" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit1_latch" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit2_latch" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit3_latch" with stuck data_in port to stuck value GND
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]" with stuck data_in port to stuck value VCC
Warning: Reduced register "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|oDATA[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_break" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|M_xbrk_goto0" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|M_xbrk_goto1" with stuck data_in port to stuck value GND
Warning: No clock transition on "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_write_request" register due to stuck clock or clock enable
Warning: Reduced register "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_write_request" with stuck clock_enable port to stuck value GND
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[0]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[1]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[2]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[3]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[4]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[5]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[6]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[7]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[8]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[9]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[10]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[11]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[12]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[13]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[14]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[15]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[16]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[17]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[18]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[19]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[20]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[21]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[22]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[23]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[24]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[25]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[26]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[27]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[28]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[29]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[30]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[31]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[32]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[33]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[34]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[35]"
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|delayed_unxsync_rxdxx2" merged to single register "system_0:u0|uart_0:the_uart_0|uart_0_rx:the_uart_0_rx|delayed_unxsync_rxdxx1"
    Info: Duplicate register "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_tri_state_bridge_0_avalon_slave_end_xfer" merged to single register "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|d1_sram_0_avalon_slave_0_end_xfer" merged to single register "system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[10]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[9]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[8]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[7]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[6]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[3]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[2]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[1]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[0]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_epcs_controller_epcs_control_port_end_xfer" merged to single register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_cpu_0_jtag_debug_module_end_xfer" merged to single register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|OTG_ADDR[1]" merged to single register "system_0:u0|clock_1:the_clock_1|slave_address_d1[3]"
    Info: Duplicate register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|OTG_ADDR[0]" merged to single register "system_0:u0|clock_1:the_clock_1|slave_address_d1[2]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|ENET_CMD" merged to single register "system_0:u0|clock_1:the_clock_1|slave_address_d1[2]"
    Info: Duplicate register "system_0:u0|VGA_0_avalon_slave_0_arbitrator:the_VGA_0_avalon_slave_0|d1_VGA_0_avalon_slave_0_end_xfer" merged to single register "system_0:u0|VGA_0_avalon_slave_0_arbitrator:the_VGA_0_avalon_slave_0|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[14]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[14]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[13]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[13]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[12]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[12]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[11]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[11]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[10]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[10]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[9]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[9]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[8]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[8]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[7]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[7]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[6]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[6]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[5]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[5]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[4]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[4]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[3]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[3]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[2]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[2]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[1]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[1]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[0]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[0]"
    Info: Duplicate register "system_0:u0|DM9000A:the_DM9000A|DM9000A_IF:the_DM9000A_IF|TMP_DATA[15]" merged to single register "system_0:u0|ISP1362:the_ISP1362|ISP1362_IF:the_ISP1362_IF|TMP_DATA[15]"
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigger_state" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_6" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_6"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_5" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_5"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_4" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_4"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_3" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_3"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_2" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_2"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_1" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_1"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_0" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_0"
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigbrktype" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "I2C_AV_Config:u1|mI2C_DATA[21]" merged to single register "I2C_AV_Config:u1|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|mI2C_DATA[20]" merged to single register "I2C_AV_Config:u1|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|mI2C_DATA[18]" merged to single register "I2C_AV_Config:u1|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|I2C_Controller:u0|SD[21]" merged to single register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|I2C_Controller:u0|SD[20]" merged to single register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|I2C_Controller:u0|SD[18]" merged to single register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_jmp_direct" merged to single register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_a_not_src"
    Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_is_dst" merged to single register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_not_src"
Warning: Reduced register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_arb_share_counter[2]" with stuck data_in port to stuck value GND
Info: State machine "|DE2_WEB|I2C_AV_Config:u1|mSetup_ST" contains 3 states
Info: State machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state" contains 6 states
Info: State machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next" contains 4 states
Info: State machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state" contains 9 states
Info: State machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next" contains 4 states
Info: State machine "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state" contains 3 states
Info: State machine "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state" contains 3 states
Info: State machine "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state" contains 3 states
Info: State machine "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|I2C_AV_Config:u1|mSetup_ST"
Info: Encoding result for state machine "|DE2_WEB|I2C_AV_Config:u1|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.0000"
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.0010"
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.0001"
    Info: State "|DE2_WEB|I2C_AV_Config:u1|mSetup_ST.0000" uses code string "000"
    Info: State "|DE2_WEB|I2C_AV_Config:u1|mSetup_ST.0001" uses code string "101"
    Info: State "|DE2_WEB|I2C_AV_Config:u1|mSetup_ST.0010" uses code string "110"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.101"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.111"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.001"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.011"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.010"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.000"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state.000" uses code string "000000"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state.010" uses code string "000011"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state.011" uses code string "000101"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state.001" uses code string "001001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state.111" uses code string "010001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_state.101" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.101"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.010"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.111"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.000"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next.000" uses code string "0000"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next.111" uses code string "0011"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next.010" uses code string "0101"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|i_next.101" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state"
    Info: Completed encoding using 9 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.100000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.010000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.001000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000100000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000010000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000001000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000100"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000010"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.000000001" uses code string "000000000"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.000100000" uses code string "000100001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.000010000" uses code string "000010001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.000001000" uses code string "000001001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.100000000" uses code string "100000001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.000000100" uses code string "000000101"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.000000010" uses code string "000000011"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.001000000" uses code string "001000001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_state.010000000" uses code string "010000001"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.010000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000010000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000001000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000000001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next.000000001" uses code string "0000"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next.000001000" uses code string "0011"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next.010000000" uses code string "1001"
    Info: State "|DE2_WEB|system_0:u0|sdram_0:the_sdram_0|m_next.000010000" uses code string "0101"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.100"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.010"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.001"
    Info: State "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.001" uses code string "000"
    Info: State "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.100" uses code string "101"
    Info: State "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.010" uses code string "011"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.100"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.010"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.001"
    Info: State "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.001" uses code string "000"
    Info: State "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.010" uses code string "011"
    Info: State "|DE2_WEB|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.100" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.100"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.010"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.001"
    Info: State "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.001" uses code string "000"
    Info: State "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.100" uses code string "101"
    Info: State "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.010" uses code string "011"
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.010"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.001"
    Info: State "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.001" uses code string "000"
    Info: State "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.010" uses code string "011"
    Info: State "|DE2_WEB|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100" uses code string "101"
Warning: Reduced register "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|epcs_controller_epcs_control_port_arbitrator:the_epcs_controller_epcs_control_port|epcs_controller_epcs_control_port_slavearbiterlockenable" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable" with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=64, WIDTH_A=16) from the following design logic: "I2C_AV_Config:u1|Ram0~37"
Info: State machine "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize"
Info: Encoding result for state machine "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.101"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000"
    Info: State "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000" uses code string "000000"
    Info: State "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" uses code string "000011"
    Info: State "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010" uses code string "000101"
    Info: State "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.101" uses code string "001001"
    Info: State "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100" uses code string "010001"
    Info: State "|DE2_WEB|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" uses code string "100001"
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" with stuck data_in port to stuck value GND
Info: Elaborated megafunction instantiation "I2C_AV_Config:u1|altsyncram:Ram0_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ocv.tdf
    Info: Found entity 1: altsyncram_ocv
Warning: Replaced VCC or GND feeding tri-state bus SD_DAT3~0 with an always-enabled tri-state buffer
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_DACLRCK~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_BCLK~0 that it feeds
Warning: Removed fan-in from always-disabled I/O buffer SD_DAT~4 to tri-state bus SD_DAT~1
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "AUD_DACLRCK" is moved to its source
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir" converted into equivalent circuit using register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~$emulated" and latch "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~7"
    Info: Register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr" converted into equivalent circuit using register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~$emulated" and latch "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~8"
Info: Duplicate registers merged to single register
    Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|reset_d1" merged to single register "system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[1]", power-up level changed
Warning: Reduced register "system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|BCK_DIV[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|m_count[2]" with stuck data_in port to stuck value GND
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "SD_DAT3~1"
    Warning: Node "AUD_ADCLRCK~2"
    Warning: Node "AUD_DACLRCK~1"
    Warning: Node "AUD_BCLK~1"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "IRDA_TXD" stuck at GND
    Warning: Pin "DRAM_CKE" stuck at VCC
    Warning: Pin "FL_RST_N" stuck at VCC
    Warning: Pin "OTG_DACK0_N" stuck at GND
    Warning: Pin "OTG_DACK1_N" stuck at GND
    Warning: Pin "LCD_ON" stuck at VCC
    Warning: Pin "LCD_BLON" stuck at VCC
    Warning: Pin "TDO" stuck at GND
    Warning: Pin "VGA_SYNC" stuck at GND
    Warning: Pin "TD_RESET" stuck at VCC
Warning: Design contains 20 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "EXT_CLOCK"
    Warning: No output dependent on input pin "IRDA_RXD"
    Warning: No output dependent on input pin "OTG_DREQ0"
    Warning: No output dependent on input pin "OTG_DREQ1"
    Warning: No output dependent on input pin "TDI"
    Warning: No output dependent on input pin "TCK"
    Warning: No output dependent on input pin "TCS"
    Warning: No output dependent on input pin "PS2_DAT"
    Warning: No output dependent on input pin "PS2_CLK"
    Warning: No output dependent on input pin "AUD_ADCDAT"
    Warning: No output dependent on input pin "TD_DATA[0]"
    Warning: No output dependent on input pin "TD_DATA[1]"
    Warning: No output dependent on input pin "TD_DATA[2]"
    Warning: No output dependent on input pin "TD_DATA[3]"
    Warning: No output dependent on input pin "TD_DATA[4]"
    Warning: No output dependent on input pin "TD_DATA[5]"
    Warning: No output dependent on input pin "TD_DATA[6]"
    Warning: No output dependent on input pin "TD_DATA[7]"
    Warning: No output dependent on input pin "TD_HS"
    Warning: No output dependent on input pin "TD_VS"
Info: Implemented 7994 device resources after synthesis - the final resource count might be different
    Info: Implemented 51 input pins
    Info: Implemented 219 output pins
    Info: Implemented 159 bidirectional pins
    Info: Implemented 7205 logic cells
    Info: Implemented 352 RAM segments
    Info: Implemented 2 ClockLock PLLs
    Info: Implemented 4 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 256 warnings
    Info: Processing ended: Tue Jul 25 22:47:24 2006
    Info: Elapsed time: 00:05:39


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/DE2/DE2_WEB/DE2_WEB.map.smsg.


