Analysis & Synthesis report for DE2_synthesizer
Thu Nov 16 09:02:07 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |DE2_synthesizer|LCD_TEST:u5|mLCD_ST
  9. State Machine - |DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST
 10. State Machine - |DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST
 11. User-Specified and Inferred Latches
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated
 16. Parameter Settings for User Entity Instance: I2C_AV_Config:u7
 17. Parameter Settings for User Entity Instance: VGA_Audio_PLL:u1|altpll:altpll_component
 18. Parameter Settings for User Entity Instance: adio_codec:ad1
 19. Parameter Settings for User Entity Instance: LCD_TEST:u5
 20. Parameter Settings for User Entity Instance: LCD_TEST:u5|LCD_Controller:u0
 21. Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u7|altsyncram:Ram0_rtl_0
 22. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Nov 16 09:02:07 2006         ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE2_synthesizer                               ;
; Top-level Entity Name              ; DE2_synthesizer                               ;
; Family                             ; Cyclone II                                    ;
; Total logic elements               ; 1494                                          ;
; Total registers                    ; 358                                           ;
; Total pins                         ; 423                                           ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 1,024                                         ;
; Embedded Multiplier 9-bit elements ; 0                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_synthesizer    ; DE2_synthesizer    ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                  ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                        ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------+
; DE2_synthesizer.v                ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/DE2_synthesizer.v      ;
; SEG7_LUT_8.v                     ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/SEG7_LUT_8.v           ;
; SEG7_LUT.v                       ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/SEG7_LUT.v             ;
; I2C_AV_Config.v                  ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/I2C_AV_Config.v        ;
; I2C_Controller.v                 ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/I2C_Controller.v       ;
; VGA_Audio_PLL.v                  ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/VGA_Audio_PLL.v        ;
; altpll.tdf                       ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf                              ;
; aglobal60.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc                           ;
; stratix_pll.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc                         ;
; stratixii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc                       ;
; cycloneii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc                       ;
; demo_sound1.v                    ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/demo_sound1.v          ;
; demo_sound2.v                    ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/demo_sound2.v          ;
; PS2_KEYBOARD.v                   ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/PS2_KEYBOARD.v         ;
; staff.v                          ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/staff.v                ;
; vga_time_generator.v             ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/vga_time_generator.v   ;
; bar_white.v                      ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/bar_white.v            ;
; bar_big.v                        ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/bar_big.v              ;
; bar_blank.v                      ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/bar_blank.v            ;
; adio_codec.v                     ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/adio_codec.v           ;
; wave_gen_string.v                ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/wave_gen_string.v      ;
; wave_gen_brass.v                 ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/wave_gen_brass.v       ;
; LCD_TEST.v                       ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/LCD_TEST.v             ;
; LCD_Controller.v                 ; yes             ; Other                        ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/LCD_Controller.v       ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf                          ;
; stratix_ram_block.inc            ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc                   ;
; lpm_mux.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc                             ;
; lpm_decode.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc                          ;
; altsyncram.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altsyncram.inc                          ;
; a_rdenreg.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc                           ;
; altrom.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altrom.inc                              ;
; altram.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altram.inc                              ;
; altdpram.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altdpram.inc                            ;
; altqpram.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altqpram.inc                            ;
; db/altsyncram_2901.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/db/altsyncram_2901.tdf ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 1,494 ;
; Total combinational functions               ; 1494  ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 878   ;
;     -- 3 input functions                    ; 277   ;
;     -- <=2 input functions                  ; 339   ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 1211  ;
;     -- arithmetic mode                      ; 283   ;
; Total registers                             ; 358   ;
; I/O pins                                    ; 423   ;
; Total memory bits                           ; 1024  ;
; Total PLLs                                  ; 1     ;
; Maximum fan-out node                        ; SW[0] ;
; Maximum fan-out                             ; 210   ;
; Total fan-out                               ; 6421  ;
; Average fan-out                             ; 2.80  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                   ;
+-------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                    ;
+-------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+
; |DE2_synthesizer                          ; 1494 (62)         ; 358 (19)     ; 1024        ; 0    ; 0            ; 0       ; 0         ; 423  ; 0            ; |DE2_synthesizer                                                                       ;
;    |I2C_AV_Config:u7|                     ; 88 (40)           ; 58 (29)      ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|I2C_AV_Config:u7                                                      ;
;       |I2C_Controller:u0|                 ; 48 (48)           ; 29 (29)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|I2C_AV_Config:u7|I2C_Controller:u0                                    ;
;       |altsyncram:Ram0_rtl_0|             ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|I2C_AV_Config:u7|altsyncram:Ram0_rtl_0                                ;
;          |altsyncram_2901:auto_generated| ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated ;
;    |LCD_TEST:u5|                          ; 85 (66)           ; 51 (38)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|LCD_TEST:u5                                                           ;
;       |LCD_Controller:u0|                 ; 19 (19)           ; 13 (13)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0                                         ;
;    |PS2_KEYBOARD:keyboard|                ; 86 (86)           ; 54 (54)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|PS2_KEYBOARD:keyboard                                                 ;
;    |VGA_Audio_PLL:u1|                     ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|VGA_Audio_PLL:u1                                                      ;
;       |altpll:altpll_component|           ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|VGA_Audio_PLL:u1|altpll:altpll_component                              ;
;    |adio_codec:ad1|                       ; 442 (440)         ; 50 (50)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|adio_codec:ad1                                                        ;
;       |wave_gen_brass:s1|                 ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|adio_codec:ad1|wave_gen_brass:s1                                      ;
;       |wave_gen_brass:s2|                 ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|adio_codec:ad1|wave_gen_brass:s2                                      ;
;    |demo_sound1:dd1|                      ; 183 (183)         ; 37 (37)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|demo_sound1:dd1                                                       ;
;    |demo_sound2:dd2|                      ; 188 (188)         ; 37 (37)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|demo_sound2:dd2                                                       ;
;    |staff:st1|                            ; 360 (237)         ; 52 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|staff:st1                                                             ;
;       |bar_big:b0|                        ; 8 (8)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|staff:st1|bar_big:b0                                                  ;
;       |bar_big:b2|                        ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|staff:st1|bar_big:b2                                                  ;
;       |bar_blank:bar_blank1|              ; 14 (14)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|staff:st1|bar_blank:bar_blank1                                        ;
;       |bar_white:bar1|                    ; 17 (17)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|staff:st1|bar_white:bar1                                              ;
;       |vga_time_generator:vga0|           ; 81 (81)           ; 52 (52)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_synthesizer|staff:st1|vga_time_generator:vga0                                     ;
+-------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                             ;
+----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------------------+
; Name                                                                             ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                      ;
+----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------------------+
; I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 64           ; 16           ; --           ; --           ; 1024 ; DE2_synthesizer0.rtl.mif ;
+----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------------------+


+------------------------------------------------------------------------------------+
; State Machine - |DE2_synthesizer|LCD_TEST:u5|mLCD_ST                               ;
+----------------+----------------+----------------+----------------+----------------+
; Name           ; mLCD_ST.000011 ; mLCD_ST.000001 ; mLCD_ST.000010 ; mLCD_ST.000000 ;
+----------------+----------------+----------------+----------------+----------------+
; mLCD_ST.000000 ; 0              ; 0              ; 0              ; 0              ;
; mLCD_ST.000010 ; 0              ; 0              ; 1              ; 1              ;
; mLCD_ST.000001 ; 0              ; 1              ; 0              ; 1              ;
; mLCD_ST.000011 ; 1              ; 0              ; 0              ; 1              ;
+----------------+----------------+----------------+----------------+----------------+


+-------------------------------------------------------------------+
; State Machine - |DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST ;
+-------+-------+-------+-------+-----------------------------------+
; Name  ; ST.11 ; ST.01 ; ST.10 ; ST.00                             ;
+-------+-------+-------+-------+-----------------------------------+
; ST.00 ; 0     ; 0     ; 0     ; 0                                 ;
; ST.10 ; 0     ; 0     ; 1     ; 1                                 ;
; ST.01 ; 0     ; 1     ; 0     ; 1                                 ;
; ST.11 ; 1     ; 0     ; 0     ; 1                                 ;
+-------+-------+-------+-------+-----------------------------------+


+-------------------------------------------------------------------+
; State Machine - |DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST       ;
+----------------+----------------+----------------+----------------+
; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ;
+----------------+----------------+----------------+----------------+
; mSetup_ST.0000 ; 0              ; 0              ; 0              ;
; mSetup_ST.0001 ; 1              ; 0              ; 1              ;
; mSetup_ST.0010 ; 1              ; 1              ; 0              ;
+----------------+----------------+----------------+----------------+


+---------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                     ;
+-----------------------------------------------------+--------------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal      ; Free of Timing Hazards ;
+-----------------------------------------------------+--------------------------+------------------------+
; demo_sound1:dd1|TT[3]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[7]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[4]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[6]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[5]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[2]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[0]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound1:dd1|TT[1]                               ; demo_sound1:dd1|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[3]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[7]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[4]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[6]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[5]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[2]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[0]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; demo_sound2:dd2|TT[1]                               ; demo_sound2:dd2|WideNor0 ; yes                    ;
; Number of user-specified and inferred latches = 16  ;                          ;                        ;
+-----------------------------------------------------+--------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 358   ;
; Number of registers using Synchronous Clear  ; 131   ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 252   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 158   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------+
; Inverted Register Statistics                               ;
+--------------------------------------------------+---------+
; Inverted Register                                ; Fan out ;
+--------------------------------------------------+---------+
; PS2_KEYBOARD:keyboard|key1_code[4]               ; 2       ;
; PS2_KEYBOARD:keyboard|key1_code[5]               ; 2       ;
; PS2_KEYBOARD:keyboard|key1_code[7]               ; 2       ;
; PS2_KEYBOARD:keyboard|key1_code[6]               ; 2       ;
; PS2_KEYBOARD:keyboard|key2_code[4]               ; 2       ;
; PS2_KEYBOARD:keyboard|key2_code[5]               ; 2       ;
; PS2_KEYBOARD:keyboard|key2_code[7]               ; 2       ;
; PS2_KEYBOARD:keyboard|key2_code[6]               ; 2       ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[0] ; 19      ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[2] ; 15      ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[3] ; 21      ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[1] ; 16      ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[4] ; 11      ;
; I2C_AV_Config:u7|I2C_Controller:u0|SD_COUNTER[5] ; 12      ;
; I2C_AV_Config:u7|I2C_Controller:u0|SCLK          ; 2       ;
; I2C_AV_Config:u7|I2C_Controller:u0|END           ; 5       ;
; I2C_AV_Config:u7|I2C_Controller:u0|SDO           ; 4       ;
; Total number of inverted registers = 17          ;         ;
+--------------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|mStart ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |DE2_synthesizer|PS2_KEYBOARD:keyboard|key1_code[2]   ;
; 33:1               ; 5 bits    ; 110 LEs       ; 105 LEs              ; 5 LEs                  ; Yes        ; |DE2_synthesizer|demo_sound1:dd1|st[5]                ;
; 33:1               ; 5 bits    ; 110 LEs       ; 105 LEs              ; 5 LEs                  ; Yes        ; |DE2_synthesizer|demo_sound2:dd2|st[1]                ;
; 7:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |DE2_synthesizer|PS2_KEYBOARD:keyboard|key2_code[0]   ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |DE2_synthesizer|PS2_KEYBOARD:keyboard|key1_code[5]   ;
; 7:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |DE2_synthesizer|PS2_KEYBOARD:keyboard|key2_code[7]   ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE2_synthesizer|demo_sound1:dd1|tmpa[6]              ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE2_synthesizer|demo_sound2:dd2|tmpa[5]              ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_synthesizer|sound_code1[5]                       ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_synthesizer|sound_code2[5]                       ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |DE2_synthesizer|LCD_TEST:u5|mLCD_ST~11               ;
; 9:1                ; 3 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|sound_code1[2]                       ;
; 9:1                ; 3 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|sound_code2[4]                       ;
; 9:1                ; 2 bits    ; 12 LEs        ; 2 LEs                ; 10 LEs                 ; No         ; |DE2_synthesizer|staff:st1|blank_x[2]                 ;
; 10:1               ; 2 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|staff:st1|by_org[5]                  ;
; 13:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |DE2_synthesizer|staff:st1|sound1[9]                  ;
; 13:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |DE2_synthesizer|staff:st1|sound2[9]                  ;
; 14:1               ; 2 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|staff:st1|y_org[6]                   ;
; 15:1               ; 2 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|staff:st1|sound1[1]                  ;
; 15:1               ; 2 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|staff:st1|sound2[1]                  ;
; 16:1               ; 3 bits    ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|staff:st1|sound1[7]                  ;
; 16:1               ; 3 bits    ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; No         ; |DE2_synthesizer|staff:st1|sound2[2]                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for I2C_AV_Config:u7|altsyncram:Ram0_rtl_0|altsyncram_2901:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------+
; Assignment                      ; Value              ; From ; To                             ;
+---------------------------------+--------------------+------+--------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                              ;
+---------------------------------+--------------------+------+--------------------------------+


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_AV_Config:u7 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; CLK_Freq       ; 50000000 ; Integer                           ;
; I2C_Freq       ; 20000    ; Integer                           ;
; LUT_SIZE       ; 50       ; Integer                           ;
; SET_LIN_L      ; 0        ; Integer                           ;
; SET_LIN_R      ; 1        ; Integer                           ;
; SET_HEAD_L     ; 2        ; Integer                           ;
; SET_HEAD_R     ; 3        ; Integer                           ;
; A_PATH_CTRL    ; 4        ; Integer                           ;
; D_PATH_CTRL    ; 5        ; Integer                           ;
; POWER_ON       ; 6        ; Integer                           ;
; SET_FORMAT     ; 7        ; Integer                           ;
; SAMPLE_CTRL    ; 8        ; Integer                           ;
; SET_ACTIVE     ; 9        ; Integer                           ;
; SET_VIDEO      ; 10       ; Integer                           ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_Audio_PLL:u1|altpll:altpll_component ;
+-------------------------------+-------------------+-----------------------------------+
; Parameter Name                ; Value             ; Type                              ;
+-------------------------------+-------------------+-----------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                           ;
; PLL_TYPE                      ; FAST              ; Untyped                           ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                           ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                           ;
; SCAN_CHAIN                    ; LONG              ; Untyped                           ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                           ;
; INCLK0_INPUT_FREQUENCY        ; 37037             ; Integer                           ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                           ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                           ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                           ;
; LOCK_HIGH                     ; 1                 ; Untyped                           ;
; LOCK_LOW                      ; 1                 ; Untyped                           ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                           ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                           ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                           ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                           ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                           ;
; SKIP_VCO                      ; OFF               ; Untyped                           ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                           ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                           ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                           ;
; BANDWIDTH                     ; 0                 ; Untyped                           ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                           ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                           ;
; DOWN_SPREAD                   ; 0                 ; Untyped                           ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                           ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK2_MULTIPLY_BY              ; 14                ; Integer                           ;
; CLK1_MULTIPLY_BY              ; 2                 ; Integer                           ;
; CLK0_MULTIPLY_BY              ; 14                ; Integer                           ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK2_DIVIDE_BY                ; 15                ; Integer                           ;
; CLK1_DIVIDE_BY                ; 3                 ; Integer                           ;
; CLK0_DIVIDE_BY                ; 15                ; Integer                           ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK2_PHASE_SHIFT              ; -9921             ; Untyped                           ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK2_DUTY_CYCLE               ; 50                ; Integer                           ;
; CLK1_DUTY_CYCLE               ; 50                ; Integer                           ;
; CLK0_DUTY_CYCLE               ; 50                ; Integer                           ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                           ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                           ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                           ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                           ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                           ;
; VCO_MIN                       ; 0                 ; Untyped                           ;
; VCO_MAX                       ; 0                 ; Untyped                           ;
; VCO_CENTER                    ; 0                 ; Untyped                           ;
; PFD_MIN                       ; 0                 ; Untyped                           ;
; PFD_MAX                       ; 0                 ; Untyped                           ;
; M_INITIAL                     ; 0                 ; Untyped                           ;
; M                             ; 0                 ; Untyped                           ;
; N                             ; 1                 ; Untyped                           ;
; M2                            ; 1                 ; Untyped                           ;
; N2                            ; 1                 ; Untyped                           ;
; SS                            ; 1                 ; Untyped                           ;
; C0_HIGH                       ; 0                 ; Untyped                           ;
; C1_HIGH                       ; 0                 ; Untyped                           ;
; C2_HIGH                       ; 0                 ; Untyped                           ;
; C3_HIGH                       ; 0                 ; Untyped                           ;
; C4_HIGH                       ; 0                 ; Untyped                           ;
; C5_HIGH                       ; 0                 ; Untyped                           ;
; C0_LOW                        ; 0                 ; Untyped                           ;
; C1_LOW                        ; 0                 ; Untyped                           ;
; C2_LOW                        ; 0                 ; Untyped                           ;
; C3_LOW                        ; 0                 ; Untyped                           ;
; C4_LOW                        ; 0                 ; Untyped                           ;
; C5_LOW                        ; 0                 ; Untyped                           ;
; C0_INITIAL                    ; 0                 ; Untyped                           ;
; C1_INITIAL                    ; 0                 ; Untyped                           ;
; C2_INITIAL                    ; 0                 ; Untyped                           ;
; C3_INITIAL                    ; 0                 ; Untyped                           ;
; C4_INITIAL                    ; 0                 ; Untyped                           ;
; C5_INITIAL                    ; 0                 ; Untyped                           ;
; C0_MODE                       ; BYPASS            ; Untyped                           ;
; C1_MODE                       ; BYPASS            ; Untyped                           ;
; C2_MODE                       ; BYPASS            ; Untyped                           ;
; C3_MODE                       ; BYPASS            ; Untyped                           ;
; C4_MODE                       ; BYPASS            ; Untyped                           ;
; C5_MODE                       ; BYPASS            ; Untyped                           ;
; C0_PH                         ; 0                 ; Untyped                           ;
; C1_PH                         ; 0                 ; Untyped                           ;
; C2_PH                         ; 0                 ; Untyped                           ;
; C3_PH                         ; 0                 ; Untyped                           ;
; C4_PH                         ; 0                 ; Untyped                           ;
; C5_PH                         ; 0                 ; Untyped                           ;
; L0_HIGH                       ; 1                 ; Untyped                           ;
; L1_HIGH                       ; 1                 ; Untyped                           ;
; G0_HIGH                       ; 1                 ; Untyped                           ;
; G1_HIGH                       ; 1                 ; Untyped                           ;
; G2_HIGH                       ; 1                 ; Untyped                           ;
; G3_HIGH                       ; 1                 ; Untyped                           ;
; E0_HIGH                       ; 1                 ; Untyped                           ;
; E1_HIGH                       ; 1                 ; Untyped                           ;
; E2_HIGH                       ; 1                 ; Untyped                           ;
; E3_HIGH                       ; 1                 ; Untyped                           ;
; L0_LOW                        ; 1                 ; Untyped                           ;
; L1_LOW                        ; 1                 ; Untyped                           ;
; G0_LOW                        ; 1                 ; Untyped                           ;
; G1_LOW                        ; 1                 ; Untyped                           ;
; G2_LOW                        ; 1                 ; Untyped                           ;
; G3_LOW                        ; 1                 ; Untyped                           ;
; E0_LOW                        ; 1                 ; Untyped                           ;
; E1_LOW                        ; 1                 ; Untyped                           ;
; E2_LOW                        ; 1                 ; Untyped                           ;
; E3_LOW                        ; 1                 ; Untyped                           ;
; L0_INITIAL                    ; 1                 ; Untyped                           ;
; L1_INITIAL                    ; 1                 ; Untyped                           ;
; G0_INITIAL                    ; 1                 ; Untyped                           ;
; G1_INITIAL                    ; 1                 ; Untyped                           ;
; G2_INITIAL                    ; 1                 ; Untyped                           ;
; G3_INITIAL                    ; 1                 ; Untyped                           ;
; E0_INITIAL                    ; 1                 ; Untyped                           ;
; E1_INITIAL                    ; 1                 ; Untyped                           ;
; E2_INITIAL                    ; 1                 ; Untyped                           ;
; E3_INITIAL                    ; 1                 ; Untyped                           ;
; L0_MODE                       ; BYPASS            ; Untyped                           ;
; L1_MODE                       ; BYPASS            ; Untyped                           ;
; G0_MODE                       ; BYPASS            ; Untyped                           ;
; G1_MODE                       ; BYPASS            ; Untyped                           ;
; G2_MODE                       ; BYPASS            ; Untyped                           ;
; G3_MODE                       ; BYPASS            ; Untyped                           ;
; E0_MODE                       ; BYPASS            ; Untyped                           ;
; E1_MODE                       ; BYPASS            ; Untyped                           ;
; E2_MODE                       ; BYPASS            ; Untyped                           ;
; E3_MODE                       ; BYPASS            ; Untyped                           ;
; L0_PH                         ; 0                 ; Untyped                           ;
; L1_PH                         ; 0                 ; Untyped                           ;
; G0_PH                         ; 0                 ; Untyped                           ;
; G1_PH                         ; 0                 ; Untyped                           ;
; G2_PH                         ; 0                 ; Untyped                           ;
; G3_PH                         ; 0                 ; Untyped                           ;
; E0_PH                         ; 0                 ; Untyped                           ;
; E1_PH                         ; 0                 ; Untyped                           ;
; E2_PH                         ; 0                 ; Untyped                           ;
; E3_PH                         ; 0                 ; Untyped                           ;
; M_PH                          ; 0                 ; Untyped                           ;
; C1_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C2_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C3_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C4_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C5_USE_CASC_IN                ; 0                 ; Untyped                           ;
; CLK0_COUNTER                  ; G0                ; Untyped                           ;
; CLK1_COUNTER                  ; G0                ; Untyped                           ;
; CLK2_COUNTER                  ; G0                ; Untyped                           ;
; CLK3_COUNTER                  ; G0                ; Untyped                           ;
; CLK4_COUNTER                  ; G0                ; Untyped                           ;
; CLK5_COUNTER                  ; G0                ; Untyped                           ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                           ;
; M_TIME_DELAY                  ; 0                 ; Untyped                           ;
; N_TIME_DELAY                  ; 0                 ; Untyped                           ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                           ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                           ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                           ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                           ;
; ENABLE0_COUNTER               ; L0                ; Untyped                           ;
; ENABLE1_COUNTER               ; L0                ; Untyped                           ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                           ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                           ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                           ;
; VCO_POST_SCALE                ; 0                 ; Untyped                           ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                           ;
; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK0                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK1                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK2                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK3                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK4                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_LOCKED                   ; PORT_CONNECTIVITY ; Untyped                           ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                           ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                           ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                           ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                    ;
+-------------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: adio_codec:ad1 ;
+-----------------+----------+--------------------------------+
; Parameter Name  ; Value    ; Type                           ;
+-----------------+----------+--------------------------------+
; REF_CLK         ; 18432000 ; Integer                        ;
; SAMPLE_RATE     ; 48000    ; Integer                        ;
; DATA_WIDTH      ; 16       ; Integer                        ;
; CHANNEL_NUM     ; 2        ; Integer                        ;
; SIN_SAMPLE_DATA ; 48       ; Integer                        ;
; SIN_SANPLE      ; 0        ; Integer                        ;
+-----------------+----------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: LCD_TEST:u5 ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type                            ;
+----------------+-------+---------------------------------+
; LCD_INTIAL     ; 0     ; Integer                         ;
; LCD_LINE1      ; 5     ; Integer                         ;
; LCD_CH_LINE    ; 21    ; Integer                         ;
; LCD_LINE2      ; 22    ; Integer                         ;
; LUT_SIZE       ; 38    ; Integer                         ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LCD_TEST:u5|LCD_Controller:u0 ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type                                              ;
+----------------+-------+---------------------------------------------------+
; CLK_Divide     ; 16    ; Integer                                           ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u7|altsyncram:Ram0_rtl_0 ;
+------------------------------------+--------------------------+-------------------------+
; Parameter Name                     ; Value                    ; Type                    ;
+------------------------------------+--------------------------+-------------------------+
; BYTE_SIZE_BLOCK                    ; 8                        ; Untyped                 ;
; AUTO_CARRY_CHAINS                  ; ON                       ; AUTO_CARRY              ;
; IGNORE_CARRY_BUFFERS               ; OFF                      ; IGNORE_CARRY            ;
; AUTO_CASCADE_CHAINS                ; ON                       ; AUTO_CASCADE            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                      ; IGNORE_CASCADE          ;
; OPERATION_MODE                     ; ROM                      ; Untyped                 ;
; WIDTH_A                            ; 16                       ; Untyped                 ;
; WIDTHAD_A                          ; 6                        ; Untyped                 ;
; NUMWORDS_A                         ; 64                       ; Untyped                 ;
; OUTDATA_REG_A                      ; UNREGISTERED             ; Untyped                 ;
; ADDRESS_ACLR_A                     ; NONE                     ; Untyped                 ;
; OUTDATA_ACLR_A                     ; NONE                     ; Untyped                 ;
; WRCONTROL_ACLR_A                   ; NONE                     ; Untyped                 ;
; INDATA_ACLR_A                      ; NONE                     ; Untyped                 ;
; BYTEENA_ACLR_A                     ; NONE                     ; Untyped                 ;
; WIDTH_B                            ; 1                        ; Untyped                 ;
; WIDTHAD_B                          ; 1                        ; Untyped                 ;
; NUMWORDS_B                         ; 1                        ; Untyped                 ;
; INDATA_REG_B                       ; CLOCK1                   ; Untyped                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                   ; Untyped                 ;
; RDCONTROL_REG_B                    ; CLOCK1                   ; Untyped                 ;
; ADDRESS_REG_B                      ; CLOCK1                   ; Untyped                 ;
; OUTDATA_REG_B                      ; UNREGISTERED             ; Untyped                 ;
; BYTEENA_REG_B                      ; CLOCK1                   ; Untyped                 ;
; INDATA_ACLR_B                      ; NONE                     ; Untyped                 ;
; WRCONTROL_ACLR_B                   ; NONE                     ; Untyped                 ;
; ADDRESS_ACLR_B                     ; NONE                     ; Untyped                 ;
; OUTDATA_ACLR_B                     ; NONE                     ; Untyped                 ;
; RDCONTROL_ACLR_B                   ; NONE                     ; Untyped                 ;
; BYTEENA_ACLR_B                     ; NONE                     ; Untyped                 ;
; WIDTH_BYTEENA_A                    ; 1                        ; Untyped                 ;
; WIDTH_BYTEENA_B                    ; 1                        ; Untyped                 ;
; RAM_BLOCK_TYPE                     ; AUTO                     ; Untyped                 ;
; BYTE_SIZE                          ; 8                        ; Untyped                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                ; Untyped                 ;
; INIT_FILE                          ; DE2_synthesizer0.rtl.mif ; Untyped                 ;
; INIT_FILE_LAYOUT                   ; PORT_A                   ; Untyped                 ;
; MAXIMUM_DEPTH                      ; 0                        ; Untyped                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                   ; Untyped                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                   ; Untyped                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                   ; Untyped                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                   ; Untyped                 ;
; DEVICE_FAMILY                      ; Cyclone II               ; Untyped                 ;
; CBXI_PARAMETER                     ; altsyncram_2901          ; Untyped                 ;
+------------------------------------+--------------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 16 09:01:28 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_synthesizer -c DE2_synthesizer
Warning: Using design file DE2_synthesizer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: DE2_synthesizer
Info: Elaborating entity "DE2_synthesizer" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at DE2_synthesizer.v(468): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at DE2_synthesizer.v(470): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at DE2_synthesizer.v(472): truncated value with size 32 to match size of target (10)
Warning (10034): Output port "LEDG[8]" at DE2_synthesizer.v(206) has no driver
Warning (10034): Output port "LEDR[17]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[16]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[15]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[14]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[13]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[12]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[11]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[10]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[5]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[4]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[3]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[2]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[1]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "LEDR[0]" at DE2_synthesizer.v(207) has no driver
Warning (10034): Output port "UART_TXD" at DE2_synthesizer.v(209) has no driver
Warning (10034): Output port "IRDA_TXD" at DE2_synthesizer.v(212) has no driver
Warning (10034): Output port "DRAM_ADDR[11]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[10]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[9]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[8]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[7]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[6]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[5]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[4]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[3]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[2]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[1]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_ADDR[0]" at DE2_synthesizer.v(216) has no driver
Warning (10034): Output port "DRAM_LDQM" at DE2_synthesizer.v(217) has no driver
Warning (10034): Output port "DRAM_UDQM" at DE2_synthesizer.v(218) has no driver
Warning (10034): Output port "DRAM_WE_N" at DE2_synthesizer.v(219) has no driver
Warning (10034): Output port "DRAM_CAS_N" at DE2_synthesizer.v(220) has no driver
Warning (10034): Output port "DRAM_RAS_N" at DE2_synthesizer.v(221) has no driver
Warning (10034): Output port "DRAM_CS_N" at DE2_synthesizer.v(222) has no driver
Warning (10034): Output port "DRAM_BA_0" at DE2_synthesizer.v(223) has no driver
Warning (10034): Output port "DRAM_BA_1" at DE2_synthesizer.v(224) has no driver
Warning (10034): Output port "DRAM_CLK" at DE2_synthesizer.v(225) has no driver
Warning (10034): Output port "DRAM_CKE" at DE2_synthesizer.v(226) has no driver
Warning (10034): Output port "FL_ADDR[19]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[18]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[17]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[16]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[15]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[14]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[13]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[12]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[11]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[10]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[9]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[8]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[7]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[6]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[5]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[4]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[3]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[2]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[1]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_ADDR[0]" at DE2_synthesizer.v(229) has no driver
Warning (10034): Output port "FL_WE_N" at DE2_synthesizer.v(230) has no driver
Warning (10034): Output port "FL_RST_N" at DE2_synthesizer.v(231) has no driver
Warning (10034): Output port "FL_OE_N" at DE2_synthesizer.v(232) has no driver
Warning (10034): Output port "FL_CE_N" at DE2_synthesizer.v(233) has no driver
Warning (10034): Output port "SRAM_ADDR[17]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[16]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[15]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[14]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[13]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[12]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[11]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[10]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[9]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[8]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[7]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[6]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[5]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[4]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[3]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[2]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[1]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_ADDR[0]" at DE2_synthesizer.v(236) has no driver
Warning (10034): Output port "SRAM_UB_N" at DE2_synthesizer.v(237) has no driver
Warning (10034): Output port "SRAM_LB_N" at DE2_synthesizer.v(238) has no driver
Warning (10034): Output port "SRAM_WE_N" at DE2_synthesizer.v(239) has no driver
Warning (10034): Output port "SRAM_CE_N" at DE2_synthesizer.v(240) has no driver
Warning (10034): Output port "SRAM_OE_N" at DE2_synthesizer.v(241) has no driver
Warning (10034): Output port "OTG_ADDR[1]" at DE2_synthesizer.v(244) has no driver
Warning (10034): Output port "OTG_ADDR[0]" at DE2_synthesizer.v(244) has no driver
Warning (10034): Output port "OTG_CS_N" at DE2_synthesizer.v(245) has no driver
Warning (10034): Output port "OTG_RD_N" at DE2_synthesizer.v(246) has no driver
Warning (10034): Output port "OTG_WR_N" at DE2_synthesizer.v(247) has no driver
Warning (10034): Output port "OTG_RST_N" at DE2_synthesizer.v(248) has no driver
Warning (10034): Output port "OTG_FSPEED" at DE2_synthesizer.v(249) has no driver
Warning (10034): Output port "OTG_LSPEED" at DE2_synthesizer.v(250) has no driver
Warning (10034): Output port "OTG_INT0" at DE2_synthesizer.v(251) has no driver
Warning (10034): Output port "OTG_INT1" at DE2_synthesizer.v(252) has no driver
Warning (10034): Output port "OTG_DREQ0" at DE2_synthesizer.v(253) has no driver
Warning (10034): Output port "OTG_DREQ1" at DE2_synthesizer.v(254) has no driver
Warning (10034): Output port "OTG_DACK0_N" at DE2_synthesizer.v(255) has no driver
Warning (10034): Output port "OTG_DACK1_N" at DE2_synthesizer.v(256) has no driver
Warning (10034): Output port "SD_CLK" at DE2_synthesizer.v(268) has no driver
Warning (10034): Output port "TDO" at DE2_synthesizer.v(279) has no driver
Warning (10034): Output port "ENET_CMD" at DE2_synthesizer.v(291) has no driver
Warning (10034): Output port "ENET_CS_N" at DE2_synthesizer.v(292) has no driver
Warning (10034): Output port "ENET_WR_N" at DE2_synthesizer.v(293) has no driver
Warning (10034): Output port "ENET_RD_N" at DE2_synthesizer.v(294) has no driver
Warning (10034): Output port "ENET_RST_N" at DE2_synthesizer.v(295) has no driver
Warning (10034): Output port "ENET_CLK" at DE2_synthesizer.v(297) has no driver
Warning (10665): Bidirectional port "AUD_DACLRCK" at DE2_synthesizer.v(300) has a one-way connection to bidirectional port "AUD_ADCLRCK"
Warning: Using design file SEG7_LUT_8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT_8
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "SEG7_LUT_8:u0"
Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_8:u0|SEG7_LUT:u0"
Warning: Using design file I2C_AV_Config.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: I2C_AV_Config
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u7"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(58): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(111): truncated value with size 32 to match size of target (6)
Warning: Using design file I2C_Controller.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: I2C_Controller
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u7|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Warning: Using design file VGA_Audio_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: VGA_Audio_PLL
Info: Elaborating entity "VGA_Audio_PLL" for hierarchy "VGA_Audio_PLL:u1"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "VGA_Audio_PLL:u1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "VGA_Audio_PLL:u1|altpll:altpll_component"
Warning: Using design file demo_sound1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: demo_sound1
Info: Elaborating entity "demo_sound1" for hierarchy "demo_sound1:dd1"
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(26): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(27): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(28): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(29): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(30): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(50): truncated value with size 32 to match size of target (16)
Warning (10270): Verilog HDL statement warning at demo_sound1.v(63): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at demo_sound1.v(62): inferring latch(es) for variable "TT", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[15]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[14]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[13]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[12]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[11]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[10]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[9]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(12): inferred latch for "TT[8]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[7]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[6]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[5]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[4]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[3]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[2]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[1]"
Info (10041): Verilog HDL or VHDL info at demo_sound1.v(63): inferred latch for "TT[0]"
Warning (10230): Verilog HDL assignment warning at demo_sound1.v(130): truncated value with size 32 to match size of target (16)
Warning: Using design file demo_sound2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: demo_sound2
Info: Elaborating entity "demo_sound2" for hierarchy "demo_sound2:dd2"
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(26): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(27): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(28): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(29): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(30): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(50): truncated value with size 32 to match size of target (16)
Warning (10270): Verilog HDL statement warning at demo_sound2.v(63): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at demo_sound2.v(62): inferring latch(es) for variable "TT", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[7]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[6]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[5]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[4]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[3]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[2]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[1]"
Info (10041): Verilog HDL or VHDL info at demo_sound2.v(63): inferred latch for "TT[0]"
Warning (10230): Verilog HDL assignment warning at demo_sound2.v(136): truncated value with size 32 to match size of target (16)
Warning: Using design file PS2_KEYBOARD.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: PS2_KEYBOARD
Info: Elaborating entity "PS2_KEYBOARD" for hierarchy "PS2_KEYBOARD:keyboard"
Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(19): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(31): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(92): truncated value with size 10 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(112): truncated value with size 10 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at PS2_KEYBOARD.v(115): truncated value with size 10 to match size of target (8)
Warning (10030): Tied undriven net "keycode_o[9]" at PS2_KEYBOARD.v(35) to 0
Warning (10030): Tied undriven net "keycode_o[8]" at PS2_KEYBOARD.v(35) to 0
Warning: Using design file staff.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: staff
Info: Elaborating entity "staff" for hierarchy "staff:st1"
Warning (10230): Verilog HDL assignment warning at staff.v(26): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at staff.v(27): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at staff.v(28): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at staff.v(29): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at staff.v(80): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at staff.v(132): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at staff.v(184): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at staff.v(236): truncated value with size 32 to match size of target (16)
Warning: Using design file vga_time_generator.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: vga_time_generator
Info: Elaborating entity "vga_time_generator" for hierarchy "staff:st1|vga_time_generator:vga0"
Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(32): truncated value with size 32 to match size of target (12)
Warning (10005): Verilog HDL or VHDL warning at vga_time_generator.v(36): overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness
Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(53): truncated value with size 32 to match size of target (12)
Warning (10005): Verilog HDL or VHDL warning at vga_time_generator.v(57): overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness
Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(72): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at vga_time_generator.v(77): truncated value with size 32 to match size of target (12)
Warning: Using design file bar_white.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: bar_white
Info: Elaborating entity "bar_white" for hierarchy "staff:st1|bar_white:bar1"
Warning (10230): Verilog HDL assignment warning at bar_white.v(23): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(24): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(25): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(26): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(27): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(28): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(29): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(30): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(31): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(32): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(33): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(34): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(35): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(36): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_white.v(37): truncated value with size 32 to match size of target (1)
Warning: Using design file bar_big.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: bar_big
Info: Elaborating entity "bar_big" for hierarchy "staff:st1|bar_big:b0"
Warning (10230): Verilog HDL assignment warning at bar_big.v(12): truncated value with size 32 to match size of target (1)
Warning: Using design file bar_blank.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: bar_blank
Info: Elaborating entity "bar_blank" for hierarchy "staff:st1|bar_blank:bar_blank1"
Warning (10230): Verilog HDL assignment warning at bar_blank.v(19): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(20): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(21): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(22): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(23): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(24): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(25): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(26): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(27): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(28): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at bar_blank.v(29): truncated value with size 32 to match size of target (1)
Warning: Using design file adio_codec.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: adio_codec
Info: Elaborating entity "adio_codec" for hierarchy "adio_codec:ad1"
Warning (10230): Verilog HDL assignment warning at adio_codec.v(63): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at adio_codec.v(88): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at adio_codec.v(96): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at adio_codec.v(104): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at adio_codec.v(117): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at adio_codec.v(144): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at adio_codec.v(146): truncated value with size 32 to match size of target (1)
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(53): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(54): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(55): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(56): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(57): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(58): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(59): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(60): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(61): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(62): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(63): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(64): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(65): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(66): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(67): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(68): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(69): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(70): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(71): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(72): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_string.v(73): truncated literal to match 16 bits
Warning: Using design file wave_gen_string.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: wave_gen_string
Info: Elaborating entity "wave_gen_string" for hierarchy "adio_codec:ad1|wave_gen_string:r1"
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(40): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(41): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(42): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(43): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(44): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(45): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(46): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(47): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(48): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(49): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(50): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(51): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(52): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(53): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(54): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(55): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(56): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(57): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(58): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(59): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(60): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(61): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(62): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(63): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(64): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(65): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(66): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(67): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(68): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(69): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(70): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(71): truncated literal to match 16 bits
Warning (10229): Verilog HDL Expression warning at wave_gen_brass.v(72): truncated literal to match 16 bits
Warning: Using design file wave_gen_brass.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: wave_gen_brass
Info: Elaborating entity "wave_gen_brass" for hierarchy "adio_codec:ad1|wave_gen_brass:s1"
Warning: Using design file LCD_TEST.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: LCD_TEST
Info: Elaborating entity "LCD_TEST" for hierarchy "LCD_TEST:u5"
Warning (10230): Verilog HDL assignment warning at LCD_TEST.v(57): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at LCD_TEST.v(65): truncated value with size 32 to match size of target (6)
Warning: Using design file LCD_Controller.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: LCD_Controller
Info: Elaborating entity "LCD_Controller" for hierarchy "LCD_TEST:u5|LCD_Controller:u0"
Warning (10230): Verilog HDL assignment warning at LCD_Controller.v(66): truncated value with size 32 to match size of target (5)
Warning: Port "org_x" on the entity instantiation of "b2" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "org_x" on the entity instantiation of "b0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "h_bporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "h_disp" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "h_fporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "h_sync" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "v_bporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "v_disp" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "v_fporch" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "v_sync" on the entity instantiation of "vga0" is connected to a signal of width 32. The formal width of the signal in the module is 12.  Extra bits will be driven by GND.
Warning: Port "#8" on the entity instantiation of "u0" is connected to a signal of width 31. The formal width of the signal in the module is 32.  Extra bits will be driven by GND.
Warning: Reduced register "adio_codec:ad1|ramp3[15]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[14]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[13]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[12]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[11]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[10]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[9]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[8]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[7]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[6]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[5]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[4]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[3]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[2]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[1]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp3[0]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[15]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[14]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[13]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[12]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[11]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[10]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[9]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[8]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[7]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[6]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[5]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[4]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[3]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[2]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[1]" with stuck clear port to stuck value GND
Warning: Reduced register "adio_codec:ad1|ramp4[0]" with stuck clear port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|mI2C_DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u7|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "demo_sound2:dd2|st[4]" merged to single register "demo_sound2:dd2|st[5]"
    Info: Duplicate register "demo_sound1:dd1|st[4]" merged to single register "demo_sound1:dd1|st[5]"
    Info: Duplicate register "I2C_AV_Config:u7|mI2C_DATA[21]" merged to single register "I2C_AV_Config:u7|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u7|mI2C_DATA[20]" merged to single register "I2C_AV_Config:u7|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u7|mI2C_DATA[18]" merged to single register "I2C_AV_Config:u7|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u7|I2C_Controller:u0|SD[21]" merged to single register "I2C_AV_Config:u7|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u7|I2C_Controller:u0|SD[20]" merged to single register "I2C_AV_Config:u7|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u7|I2C_Controller:u0|SD[18]" merged to single register "I2C_AV_Config:u7|I2C_Controller:u0|SD[22]", power-up level changed
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File C:/Documents and Settings/User/桌面/新資料夾/DE2_synthesizer/db/rom0_I2C_AV_Config_fe53227f.hdl.mif contains don't care values -- overwriting them with 0s
Warning: Reduced register "demo_sound1:dd1|st[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "demo_sound1:dd1|st[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "demo_sound2:dd2|st[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "demo_sound2:dd2|st[3]" with stuck data_in port to stuck value GND
Info: State machine "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST" contains 4 states
Info: State machine "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST" contains 4 states
Info: State machine "|DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST"
Info: Encoding result for state machine "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "LCD_TEST:u5|mLCD_ST.000011"
        Info: Encoded state bit "LCD_TEST:u5|mLCD_ST.000001"
        Info: Encoded state bit "LCD_TEST:u5|mLCD_ST.000010"
        Info: Encoded state bit "LCD_TEST:u5|mLCD_ST.000000"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST.000000" uses code string "0000"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST.000010" uses code string "0011"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST.000001" uses code string "0101"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|mLCD_ST.000011" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST"
Info: Encoding result for state machine "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "LCD_TEST:u5|LCD_Controller:u0|ST.11"
        Info: Encoded state bit "LCD_TEST:u5|LCD_Controller:u0|ST.01"
        Info: Encoded state bit "LCD_TEST:u5|LCD_Controller:u0|ST.10"
        Info: Encoded state bit "LCD_TEST:u5|LCD_Controller:u0|ST.00"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST.00" uses code string "0000"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST.10" uses code string "0011"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST.01" uses code string "0101"
    Info: State "|DE2_synthesizer|LCD_TEST:u5|LCD_Controller:u0|ST.11" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST"
Info: Encoding result for state machine "|DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_AV_Config:u7|mSetup_ST.0000"
        Info: Encoded state bit "I2C_AV_Config:u7|mSetup_ST.0010"
        Info: Encoded state bit "I2C_AV_Config:u7|mSetup_ST.0001"
    Info: State "|DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST.0000" uses code string "000"
    Info: State "|DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST.0001" uses code string "101"
    Info: State "|DE2_synthesizer|I2C_AV_Config:u7|mSetup_ST.0010" uses code string "110"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=64, WIDTH_A=16) from the following design logic: "I2C_AV_Config:u7|Ram0~37"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "I2C_AV_Config:u7|altsyncram:Ram0_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2901.tdf
    Info: Found entity 1: altsyncram_2901
Warning: The bidir "OTG_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[15]" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[0]~7 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[1]~6 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[2]~5 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[3]~4 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[4]~3 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[5]~2 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[6]~1 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus LCD_DATA[7]~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_DACLRCK~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus AUD_BCLK~0 that it feeds
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fan-out of permanently enabled tri-state buffer feeding bidir "AUD_DACLRCK" is moved to its source
Warning: Latch demo_sound1:dd1|TT[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound1:dd1|TT[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound1:dd1|step[0]
Warning: Latch demo_sound2:dd2|TT[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Warning: Latch demo_sound2:dd2|TT[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal demo_sound2:dd2|step[0]
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Reduced register "adio_codec:ad1|BCK_DIV[3]" with stuck data_in port to stuck value GND
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "LCD_DATA[0]~8"
    Warning: Node "LCD_DATA[1]~9"
    Warning: Node "LCD_DATA[2]~10"
    Warning: Node "LCD_DATA[3]~11"
    Warning: Node "LCD_DATA[4]~12"
    Warning: Node "LCD_DATA[5]~13"
    Warning: Node "LCD_DATA[6]~14"
    Warning: Node "LCD_DATA[7]~15"
    Warning: Node "AUD_ADCLRCK~2"
    Warning: Node "AUD_DACLRCK~1"
    Warning: Node "AUD_BCLK~1"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "HEX0[0]" stuck at GND
    Warning: Pin "HEX0[1]" stuck at GND
    Warning: Pin "HEX0[2]" stuck at VCC
    Warning: Pin "HEX0[3]" stuck at GND
    Warning: Pin "HEX0[4]" stuck at GND
    Warning: Pin "HEX0[5]" stuck at VCC
    Warning: Pin "HEX0[6]" stuck at GND
    Warning: Pin "HEX1[0]" stuck at VCC
    Warning: Pin "HEX1[1]" stuck at GND
    Warning: Pin "HEX1[2]" stuck at GND
    Warning: Pin "HEX1[3]" stuck at VCC
    Warning: Pin "HEX1[4]" stuck at VCC
    Warning: Pin "HEX1[5]" stuck at VCC
    Warning: Pin "HEX1[6]" stuck at VCC
    Warning: Pin "HEX2[0]" stuck at VCC
    Warning: Pin "HEX2[1]" stuck at GND
    Warning: Pin "HEX2[2]" stuck at GND
    Warning: Pin "HEX2[3]" stuck at VCC
    Warning: Pin "HEX2[4]" stuck at VCC
    Warning: Pin "HEX2[5]" stuck at VCC
    Warning: Pin "HEX2[6]" stuck at VCC
    Warning: Pin "HEX3[0]" stuck at VCC
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[3]" stuck at VCC
    Warning: Pin "HEX3[4]" stuck at VCC
    Warning: Pin "HEX3[5]" stuck at VCC
    Warning: Pin "HEX3[6]" stuck at VCC
    Warning: Pin "HEX4[0]" stuck at GND
    Warning: Pin "HEX4[1]" stuck at GND
    Warning: Pin "HEX4[2]" stuck at GND
    Warning: Pin "HEX4[3]" stuck at GND
    Warning: Pin "HEX4[4]" stuck at GND
    Warning: Pin "HEX4[5]" stuck at GND
    Warning: Pin "HEX4[6]" stuck at VCC
    Warning: Pin "HEX5[0]" stuck at GND
    Warning: Pin "HEX5[1]" stuck at GND
    Warning: Pin "HEX5[2]" stuck at GND
    Warning: Pin "HEX5[3]" stuck at GND
    Warning: Pin "HEX5[4]" stuck at GND
    Warning: Pin "HEX5[5]" stuck at GND
    Warning: Pin "HEX5[6]" stuck at VCC
    Warning: Pin "HEX6[0]" stuck at GND
    Warning: Pin "HEX6[1]" stuck at GND
    Warning: Pin "HEX6[2]" stuck at GND
    Warning: Pin "HEX6[3]" stuck at GND
    Warning: Pin "HEX6[4]" stuck at GND
    Warning: Pin "HEX6[5]" stuck at GND
    Warning: Pin "HEX6[6]" stuck at VCC
    Warning: Pin "HEX7[0]" stuck at GND
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[3]" stuck at GND
    Warning: Pin "HEX7[4]" stuck at GND
    Warning: Pin "HEX7[5]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at VCC
    Warning: Pin "LEDG[8]" stuck at GND
    Warning: Pin "LEDR[0]" stuck at GND
    Warning: Pin "LEDR[1]" stuck at GND
    Warning: Pin "LEDR[2]" stuck at GND
    Warning: Pin "LEDR[3]" stuck at GND
    Warning: Pin "LEDR[4]" stuck at GND
    Warning: Pin "LEDR[5]" stuck at GND
    Warning: Pin "LEDR[8]" stuck at GND
    Warning: Pin "LEDR[9]" stuck at GND
    Warning: Pin "LEDR[10]" stuck at GND
    Warning: Pin "LEDR[11]" stuck at GND
    Warning: Pin "LEDR[12]" stuck at GND
    Warning: Pin "LEDR[13]" stuck at GND
    Warning: Pin "LEDR[14]" stuck at GND
    Warning: Pin "LEDR[15]" stuck at GND
    Warning: Pin "LEDR[16]" stuck at GND
    Warning: Pin "LEDR[17]" stuck at GND
    Warning: Pin "UART_TXD" stuck at GND
    Warning: Pin "IRDA_TXD" stuck at GND
    Warning: Pin "DRAM_ADDR[0]" stuck at GND
    Warning: Pin "DRAM_ADDR[1]" stuck at GND
    Warning: Pin "DRAM_ADDR[2]" stuck at GND
    Warning: Pin "DRAM_ADDR[3]" stuck at GND
    Warning: Pin "DRAM_ADDR[4]" stuck at GND
    Warning: Pin "DRAM_ADDR[5]" stuck at GND
    Warning: Pin "DRAM_ADDR[6]" stuck at GND
    Warning: Pin "DRAM_ADDR[7]" stuck at GND
    Warning: Pin "DRAM_ADDR[8]" stuck at GND
    Warning: Pin "DRAM_ADDR[9]" stuck at GND
    Warning: Pin "DRAM_ADDR[10]" stuck at GND
    Warning: Pin "DRAM_ADDR[11]" stuck at GND
    Warning: Pin "DRAM_LDQM" stuck at GND
    Warning: Pin "DRAM_UDQM" stuck at GND
    Warning: Pin "DRAM_WE_N" stuck at GND
    Warning: Pin "DRAM_CAS_N" stuck at GND
    Warning: Pin "DRAM_RAS_N" stuck at GND
    Warning: Pin "DRAM_CS_N" stuck at GND
    Warning: Pin "DRAM_BA_0" stuck at GND
    Warning: Pin "DRAM_BA_1" stuck at GND
    Warning: Pin "DRAM_CLK" stuck at GND
    Warning: Pin "DRAM_CKE" stuck at GND
    Warning: Pin "FL_ADDR[0]" stuck at GND
    Warning: Pin "FL_ADDR[1]" stuck at GND
    Warning: Pin "FL_ADDR[2]" stuck at GND
    Warning: Pin "FL_ADDR[3]" stuck at GND
    Warning: Pin "FL_ADDR[4]" stuck at GND
    Warning: Pin "FL_ADDR[5]" stuck at GND
    Warning: Pin "FL_ADDR[6]" stuck at GND
    Warning: Pin "FL_ADDR[7]" stuck at GND
    Warning: Pin "FL_ADDR[8]" stuck at GND
    Warning: Pin "FL_ADDR[9]" stuck at GND
    Warning: Pin "FL_ADDR[10]" stuck at GND
    Warning: Pin "FL_ADDR[11]" stuck at GND
    Warning: Pin "FL_ADDR[12]" stuck at GND
    Warning: Pin "FL_ADDR[13]" stuck at GND
    Warning: Pin "FL_ADDR[14]" stuck at GND
    Warning: Pin "FL_ADDR[15]" stuck at GND
    Warning: Pin "FL_ADDR[16]" stuck at GND
    Warning: Pin "FL_ADDR[17]" stuck at GND
    Warning: Pin "FL_ADDR[18]" stuck at GND
    Warning: Pin "FL_ADDR[19]" stuck at GND
    Warning: Pin "FL_WE_N" stuck at GND
    Warning: Pin "FL_RST_N" stuck at GND
    Warning: Pin "FL_OE_N" stuck at GND
    Warning: Pin "FL_CE_N" stuck at GND
    Warning: Pin "SRAM_ADDR[0]" stuck at GND
    Warning: Pin "SRAM_ADDR[1]" stuck at GND
    Warning: Pin "SRAM_ADDR[2]" stuck at GND
    Warning: Pin "SRAM_ADDR[3]" stuck at GND
    Warning: Pin "SRAM_ADDR[4]" stuck at GND
    Warning: Pin "SRAM_ADDR[5]" stuck at GND
    Warning: Pin "SRAM_ADDR[6]" stuck at GND
    Warning: Pin "SRAM_ADDR[7]" stuck at GND
    Warning: Pin "SRAM_ADDR[8]" stuck at GND
    Warning: Pin "SRAM_ADDR[9]" stuck at GND
    Warning: Pin "SRAM_ADDR[10]" stuck at GND
    Warning: Pin "SRAM_ADDR[11]" stuck at GND
    Warning: Pin "SRAM_ADDR[12]" stuck at GND
    Warning: Pin "SRAM_ADDR[13]" stuck at GND
    Warning: Pin "SRAM_ADDR[14]" stuck at GND
    Warning: Pin "SRAM_ADDR[15]" stuck at GND
    Warning: Pin "SRAM_ADDR[16]" stuck at GND
    Warning: Pin "SRAM_ADDR[17]" stuck at GND
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
    Warning: Pin "SRAM_WE_N" stuck at GND
    Warning: Pin "SRAM_CE_N" stuck at GND
    Warning: Pin "SRAM_OE_N" stuck at GND
    Warning: Pin "OTG_ADDR[0]" stuck at GND
    Warning: Pin "OTG_ADDR[1]" stuck at GND
    Warning: Pin "OTG_CS_N" stuck at GND
    Warning: Pin "OTG_RD_N" stuck at GND
    Warning: Pin "OTG_WR_N" stuck at GND
    Warning: Pin "OTG_RST_N" stuck at GND
    Warning: Pin "OTG_FSPEED" stuck at GND
    Warning: Pin "OTG_LSPEED" stuck at GND
    Warning: Pin "OTG_INT0" stuck at GND
    Warning: Pin "OTG_INT1" stuck at GND
    Warning: Pin "OTG_DREQ0" stuck at GND
    Warning: Pin "OTG_DREQ1" stuck at GND
    Warning: Pin "OTG_DACK0_N" stuck at GND
    Warning: Pin "OTG_DACK1_N" stuck at GND
    Warning: Pin "LCD_ON" stuck at VCC
    Warning: Pin "LCD_BLON" stuck at VCC
    Warning: Pin "LCD_RW" stuck at GND
    Warning: Pin "SD_CLK" stuck at GND
    Warning: Pin "TDO" stuck at GND
    Warning: Pin "VGA_SYNC" stuck at VCC
    Warning: Pin "VGA_R[0]" stuck at GND
    Warning: Pin "VGA_R[1]" stuck at GND
    Warning: Pin "VGA_R[2]" stuck at GND
    Warning: Pin "VGA_R[3]" stuck at GND
    Warning: Pin "VGA_G[0]" stuck at GND
    Warning: Pin "VGA_G[1]" stuck at GND
    Warning: Pin "VGA_G[2]" stuck at GND
    Warning: Pin "VGA_G[3]" stuck at GND
    Warning: Pin "VGA_B[0]" stuck at GND
    Warning: Pin "VGA_B[1]" stuck at GND
    Warning: Pin "VGA_B[2]" stuck at GND
    Warning: Pin "VGA_B[3]" stuck at GND
    Warning: Pin "ENET_CMD" stuck at GND
    Warning: Pin "ENET_CS_N" stuck at GND
    Warning: Pin "ENET_WR_N" stuck at GND
    Warning: Pin "ENET_RD_N" stuck at GND
    Warning: Pin "ENET_RST_N" stuck at GND
    Warning: Pin "ENET_CLK" stuck at GND
    Warning: Pin "TD_RESET" stuck at VCC
Warning: Design contains 32 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "EXT_CLOCK"
    Warning: No output dependent on input pin "SW[3]"
    Warning: No output dependent on input pin "SW[4]"
    Warning: No output dependent on input pin "SW[5]"
    Warning: No output dependent on input pin "SW[6]"
    Warning: No output dependent on input pin "SW[7]"
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[11]"
    Warning: No output dependent on input pin "SW[12]"
    Warning: No output dependent on input pin "SW[13]"
    Warning: No output dependent on input pin "SW[14]"
    Warning: No output dependent on input pin "SW[15]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "SW[17]"
    Warning: No output dependent on input pin "UART_RXD"
    Warning: No output dependent on input pin "IRDA_RXD"
    Warning: No output dependent on input pin "TDI"
    Warning: No output dependent on input pin "TCK"
    Warning: No output dependent on input pin "TCS"
    Warning: No output dependent on input pin "ENET_INT"
    Warning: No output dependent on input pin "AUD_ADCDAT"
    Warning: No output dependent on input pin "TD_DATA[0]"
    Warning: No output dependent on input pin "TD_DATA[1]"
    Warning: No output dependent on input pin "TD_DATA[2]"
    Warning: No output dependent on input pin "TD_DATA[3]"
    Warning: No output dependent on input pin "TD_DATA[4]"
    Warning: No output dependent on input pin "TD_DATA[5]"
    Warning: No output dependent on input pin "TD_DATA[6]"
    Warning: No output dependent on input pin "TD_DATA[7]"
    Warning: No output dependent on input pin "TD_HS"
    Warning: No output dependent on input pin "TD_VS"
Info: Implemented 1977 device resources after synthesis - the final resource count might be different
    Info: Implemented 43 input pins
    Info: Implemented 220 output pins
    Info: Implemented 160 bidirectional pins
    Info: Implemented 1537 logic cells
    Info: Implemented 16 RAM segments
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 626 warnings
    Info: Processing ended: Thu Nov 16 09:02:07 2006
    Info: Elapsed time: 00:00:39


