Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u5 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u4 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|cntr_b |
3 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
58 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo|dcfifo_mixed_widths_component|auto_generated |
37 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_read_fifo |
37 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|cntr_b |
3 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
16 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16 |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13 |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rs_bwp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rs_brp |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
30 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo|dcfifo_mixed_widths_component|auto_generated |
13 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_write_fifo |
13 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_command |
34 |
0 |
1 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_control |
30 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u1|u_sdram_pll|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1|u_sdram_pll |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1 |
126 |
112 |
0 |
112 |
33 |
112 |
112 |
112 |
32 |
0 |
0 |
0 |
0 |
pll_27_inst |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |