DE2_115_SOPC | DE2_115_SOPC
1.0 |
2011.08.03.19:43:37 | Generation Report |
Output Directory | D:/FPGA/DE2_115/myfirst_niosii/ | ||||||||||||||||||||||||||||||||||||||||||
Files | D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/DE2_115_SOPC.v (250930 bytes VERILOG)
D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_demultiplexer_df2lfcdb.sv (6043 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_slave_agent.sv (17576 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10395 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_multiplexer_3c7awoxe.sv (11040 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_sysid_qsys_exz7b53s.v (1457 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_jtag_uart_2pkhqydp.v (24787 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_jtag_uart_2pkhqydp_input_mutex.dat (3 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_jtag_uart_2pkhqydp_input_stream.dat (10 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_jtag_uart_2pkhqydp_output_stream.dat (0 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_onchip_memory2_4y7nc2pu.hex (691291 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_onchip_memory2_4y7nc2pu.v (4124 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_master_agent.sv (8679 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_demultiplexer_hg7hfhzw.sv (4132 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_reset_controller.v (3595 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_reset_synchronizer.v (3092 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm.do (8157 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm.ocp (864 bytes unknown type) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm.sdc (4569 bytes SDC) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm.v (442328 bytes VERILOG_ENCRYPT) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_bht_ram.dat (773 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_bht_ram.hex (3870 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_bht_ram.mif (2392 bytes MIF) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_dc_tag_ram.dat (325 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_dc_tag_ram.hex (1118 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_dc_tag_ram.mif (792 bytes MIF) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_ic_tag_ram.dat (773 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_ic_tag_ram.hex (2206 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_ic_tag_ram.mif (1625 bytes MIF) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_jtag_debug_module_sysclk.v (7278 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_jtag_debug_module_tck.v (8732 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_jtag_debug_module_wrapper.v (10574 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_mult_cell.v (6312 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_ociram_default_contents.dat (2378 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_ociram_default_contents.hex (5148 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_ociram_default_contents.mif (5878 bytes MIF) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_oci_test_bench.v (1489 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_rf_ram_a.dat (325 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_rf_ram_a.hex (702 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_rf_ram_a.mif (600 bytes MIF) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_rf_ram_b.dat (325 bytes OTHER) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_rf_ram_b.hex (702 bytes HEX) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_rf_ram_b.mif (600 bytes MIF) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_nios2_qsys_mwb6kynm_test_bench.v (32416 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_slave_translator.sv (15732 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_pio_brhxffyx.v (2342 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_router_n7fb7pom.sv (5544 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_multiplexer_g3s67hmf.sv (14803 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_master_translator.sv (16023 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_irq_mapper_5w6io5ur.sv (1745 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_router_nnir6szq.sv (5171 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_traffic_limiter.sv (13741 bytes SYSTEM_VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG) D:/FPGA/DE2_115/myfirst_niosii/DE2_115_SOPC/synthesis/submodules/altera_merlin_router_rpnjn2bj.sv (6333 bytes SYSTEM_VERILOG) |
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Instantiations |
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