cpu_system cpu_system
1.0
2011.08.09.12:13:12 Generation Report
Output Directory D:/Home/User/My Documents/Memtest/Memtest/systems/
Files D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/cpu_system.v (247537 bytes VERILOG)

D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv (5195 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_router_ieor7irj.sv (5170 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_irq_mapper_2ia6qhff.sv (1742 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_demultiplexer_2hdz7hhu.sv (4131 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_mm_bridge.v (11535 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_slave_translator.sv (15731 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_traffic_limiter.sv (13743 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_dc_fifo.v (23502 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v (1434 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_dc_fifo.sdc (759 bytes SDC)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_slave_agent.sv (17578 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10397 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_multiplexer_7t5ew22p.sv (11042 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_demultiplexer_4sitf4to.sv (5395 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus.do (4125 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus.sdc (4569 bytes SDC)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus.v (197063 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_jtag_debug_module_sysclk.v (7278 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_jtag_debug_module_tck.v (8732 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_jtag_debug_module_wrapper.v (10574 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_ociram_default_contents.dat (2378 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_ociram_default_contents.hex (5148 bytes HEX)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_ociram_default_contents.mif (5878 bytes MIF)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_oci_test_bench.v (1489 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_rf_ram_a.dat (325 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_rf_ram_a.hex (702 bytes HEX)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_rf_ram_a.mif (600 bytes MIF)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_rf_ram_b.dat (325 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_rf_ram_b.hex (702 bytes HEX)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_rf_ram_b.mif (600 bytes MIF)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_nios2_qsys_be44pvus_test_bench.v (30927 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_onchip_memory2_mejd6mmm.hex (688141 bytes HEX)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_onchip_memory2_mejd6mmm.v (4124 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_master_translator.sv (15813 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_master_agent.sv (8681 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_jtag_uart_nbmdwotd.v (24797 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_jtag_uart_nbmdwotd_input_mutex.dat (3 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_jtag_uart_nbmdwotd_input_stream.dat (10 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_jtag_uart_nbmdwotd_output_stream.dat (0 bytes OTHER)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_reset_controller.v (3594 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_reset_synchronizer.v (3091 bytes VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_multiplexer_cuej2q2z.sv (13957 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_router_kzjlm7w5.sv (5525 bytes SYSTEM_VERILOG)
D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_router_afjukysr.sv (6057 bytes SYSTEM_VERILOG)
Instantiations
cpu_system
cpu_system v1.0
altera_avalon_sc_fifo as cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, onchip_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, pipeline_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo, pipeline_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo
altera_avalon_st_pipeline_stage as limiter_pipeline, limiter_pipeline_001, limiter_pipeline_002, limiter_pipeline_003
altera_merlin_router_ieor7irj as id_router, id_router_001, id_router_002, id_router_003
altera_irq_mapper_2ia6qhff as irq_mapper
altera_merlin_demultiplexer_2hdz7hhu as rsp_xbar_demux, rsp_xbar_demux_001, rsp_xbar_demux_002, rsp_xbar_demux_003
altera_avalon_mm_bridge as pipeline_bridge
altera_merlin_slave_translator as cpu_jtag_debug_module_translator, onchip_ram_s1_translator, jtag_uart_avalon_jtag_slave_translator, pipeline_bridge_s0_translator
altera_merlin_traffic_limiter as limiter, limiter_001
altera_avalon_dc_fifo as async_fifo, async_fifo_001, async_fifo_002, async_fifo_003
altera_merlin_slave_agent as cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, onchip_ram_s1_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent, pipeline_bridge_s0_translator_avalon_universal_slave_0_agent
altera_merlin_multiplexer_7t5ew22p as cmd_xbar_mux, cmd_xbar_mux_001, cmd_xbar_mux_002, cmd_xbar_mux_003
altera_merlin_demultiplexer_4sitf4to as cmd_xbar_demux, cmd_xbar_demux_001
altera_nios2_qsys_be44pvus as cpu
altera_avalon_onchip_memory2_mejd6mmm as onchip_ram
altera_merlin_master_translator as cpu_instruction_master_translator, cpu_data_master_translator
altera_merlin_master_agent as cpu_instruction_master_translator_avalon_universal_master_0_agent, cpu_data_master_translator_avalon_universal_master_0_agent
altera_avalon_jtag_uart_nbmdwotd as jtag_uart
altera_reset_controller as rst_controller, rst_controller_001
altera_merlin_multiplexer_cuej2q2z as rsp_xbar_mux, rsp_xbar_mux_001
altera_merlin_router_kzjlm7w5 as addr_router
altera_merlin_router_afjukysr as addr_router_001
altera_avalon_onchip_memory2_mejd6mmm
altera_avalon_onchip_memory2 v10.1
altera_avalon_jtag_uart_nbmdwotd
altera_avalon_jtag_uart v10.1
altera_nios2_qsys_be44pvus
altera_nios2_qsys v10.1
altera_avalon_mm_bridge
altera_avalon_mm_bridge v10.1
altera_merlin_master_translator
altera_merlin_master_translator v10.1
altera_merlin_slave_translator
altera_merlin_slave_translator v10.1
altera_merlin_master_agent
altera_merlin_master_agent v10.1
altera_merlin_slave_agent
altera_merlin_slave_agent v10.1
altera_avalon_sc_fifo
altera_avalon_sc_fifo v10.1
altera_merlin_router_kzjlm7w5
altera_merlin_router v10.1
altera_merlin_router_afjukysr
altera_merlin_router v10.1
altera_merlin_router_ieor7irj
altera_merlin_router v10.1
altera_merlin_traffic_limiter
altera_merlin_traffic_limiter v10.1
altera_reset_controller
altera_reset_controller v10.1
altera_merlin_demultiplexer_4sitf4to
altera_merlin_demultiplexer v10.1
altera_merlin_multiplexer_7t5ew22p
altera_merlin_multiplexer v10.1
altera_merlin_demultiplexer_2hdz7hhu
altera_merlin_demultiplexer v10.1
altera_merlin_multiplexer_cuej2q2z
altera_merlin_multiplexer v10.1
altera_avalon_dc_fifo
altera_avalon_dc_fifo v10.1
altera_avalon_st_pipeline_stage
altera_avalon_st_pipeline_stage v10.1
altera_irq_mapper_2ia6qhff
altera_irq_mapper v10.1
Generation Messages
2011.08.09.12:12:44 [Debug] cpu_system.cpu: Timing: VAL:1/0.032s ELA:1/0.000s 2011.08.09.12:12:44 [Debug] cpu_system.pipeline_bridge: Timing: ELA:1/0.000s 2011.08.09.12:12:44 [Info] cpu_system: Generating cpu_system "cpu_system" for QUARTUS_SYNTH 2011.08.09.12:12:44 [Debug] cpu_system: queue size: 0 starting:cpu_system "cpu_system" 2011.08.09.12:12:44 [Debug] Transform: PipelineBridgeSwap 2011.08.09.12:12:44 [Debug] Transform: ClockCrossingBridgeSwap 2011.08.09.12:12:44 [Debug] Transform: QsysBetaIPSwap 2011.08.09.12:12:44 [Debug] Transform: CustomInstructionTransform 2011.08.09.12:12:44 [Info] No custom instruction connections, skipping transform 2011.08.09.12:12:44 [Debug] Transform: TristateConduitUpgradeTransform 2011.08.09.12:12:44 [Debug] Transform: TranslatorTransform 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Debug] Transform: DomainTransform 2011.08.09.12:12:44 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 2011.08.09.12:12:44 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Progress] min: 0 2011.08.09.12:12:44 [Progress] max: 1 2011.08.09.12:12:44 [Progress] current: 1 2011.08.09.12:12:44 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module 2011.08.09.12:12:44 [Debug] Transform merlin_domain_transform not run on matched interfaces onchip_ram_s1_translator.avalon_anti_slave_0 and onchip_ram.s1 2011.08.09.12:12:44 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave 2011.08.09.12:12:44 [Debug] Transform merlin_domain_transform not run on matched interfaces pipeline_bridge_s0_translator.avalon_anti_slave_0 and pipeline_bridge.s0 2011.08.09.12:12:44 [Debug] Transform: RouterTransform 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Debug] Transform: TrafficLimiterTransform 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Debug] Transform: BurstTransform 2011.08.09.12:12:45 [Debug] Transform: ResetUpgradeTransform 2011.08.09.12:12:45 [Debug] Transform: ResetAdaptation 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:45 [Debug] Transform: NetworkToSwitchTransform 2011.08.09.12:12:45 [Progress] min: 0 2011.08.09.12:12:45 [Progress] max: 1 2011.08.09.12:12:45 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Debug] Transform: WidthTransform 2011.08.09.12:12:46 [Debug] Transform: RouterTableTransform 2011.08.09.12:12:46 [Debug] Transform: ClockCrossingTransform 2011.08.09.12:12:46 [Info] Inserting clock-crossing logic between cmd_xbar_demux.src3 and cmd_xbar_mux_003.sink0 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src3 and cmd_xbar_mux_003.sink1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Info] Inserting clock-crossing logic between rsp_xbar_demux_003.src0 and rsp_xbar_mux.sink3 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Info] Inserting clock-crossing logic between rsp_xbar_demux_003.src1 and rsp_xbar_mux_001.sink3 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Debug] Transform: PipelineTransform 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Progress] min: 0 2011.08.09.12:12:46 [Progress] max: 1 2011.08.09.12:12:46 [Progress] current: 1 2011.08.09.12:12:46 [Debug] Transform: TrafficLimiterUpdateTransform 2011.08.09.12:12:47 [Debug] Transform: InterruptMapperTransform 2011.08.09.12:12:47 [Progress] min: 0 2011.08.09.12:12:47 [Progress] max: 1 2011.08.09.12:12:47 [Progress] current: 1 2011.08.09.12:12:47 [Debug] Transform: InterruptSyncTransform 2011.08.09.12:12:47 [Debug] Transform: InterruptFanoutTransform 2011.08.09.12:12:48 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)" 2011.08.09.12:12:48 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_onchip_memory2 "submodules/altera_avalon_onchip_memory2_mejd6mmm" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_jtag_uart "submodules/altera_avalon_jtag_uart_nbmdwotd" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_nios2_qsys "submodules/altera_nios2_qsys_be44pvus" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_mm_bridge "submodules/altera_avalon_mm_bridge" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_router "submodules/altera_merlin_router_kzjlm7w5" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_router "submodules/altera_merlin_router_afjukysr" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_router "submodules/altera_merlin_router_ieor7irj" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_router "submodules/altera_merlin_router_ieor7irj" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_router "submodules/altera_merlin_router_ieor7irj" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_router "submodules/altera_merlin_router_ieor7irj" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_4sitf4to" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_4sitf4to" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_7t5ew22p" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_7t5ew22p" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_7t5ew22p" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_7t5ew22p" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_2hdz7hhu" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_2hdz7hhu" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_2hdz7hhu" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_2hdz7hhu" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_cuej2q2z" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_cuej2q2z" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_dc_fifo "submodules/altera_avalon_dc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_dc_fifo "submodules/altera_avalon_dc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_dc_fifo "submodules/altera_avalon_dc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_dc_fifo "submodules/altera_avalon_dc_fifo" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_st_pipeline_stage "submodules/altera_avalon_st_pipeline_stage" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_st_pipeline_stage "submodules/altera_avalon_st_pipeline_stage" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_st_pipeline_stage "submodules/altera_avalon_st_pipeline_stage" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_avalon_st_pipeline_stage "submodules/altera_avalon_st_pipeline_stage" 2011.08.09.12:12:48 [Debug] cpu_system: "cpu_system" reuses altera_irq_mapper "submodules/altera_irq_mapper_2ia6qhff" 2011.08.09.12:12:48 [Debug] cpu_system: queue size: 51 starting:altera_avalon_onchip_memory2 "submodules/altera_avalon_onchip_memory2_mejd6mmm" 2011.08.09.12:12:48 [Info] Starting PTF file elaboration. 2011.08.09.12:12:49 [Progress] "d:/altera/10.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "d:/altera/10.1/quartus/sopc_builder/bin/sopc_builder.jar;d:/altera/10.1/quartus/sopc_builder/bin/PinAssigner.jar;d:/altera/10.1/quartus/sopc_builder/bin/sopc_wizard.jar;d:/altera/10.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"d:/altera/10.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0014_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0014_sopclgen/yysystem.v --quartus_dir="d:/altera/10.1/quartus" --sopc_perl="d:/altera/10.1/quartus/bin/perl" --sopc_lib_path="++d:/altera/10.1/quartus/../ip/altera/sopc_builder_ip+d:/altera/10.1/quartus/../ip/altera/nios2_ip" 2011.08.09.12:12:51 [Info] Finished elaborating PTF file. 2011.08.09.12:12:51 [Progress] Executing: D:/altera/10.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0014_sopclgen/yysystem.ptf 2011.08.09.12:12:51 [Info] Starting generation... 2011.08.09.12:12:52 [Progress] "d:/altera/10.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "d:/altera/10.1/quartus/sopc_builder/bin/sopc_builder.jar;d:/altera/10.1/quartus/sopc_builder/bin/PinAssigner.jar;d:/altera/10.1/quartus/sopc_builder/bin/sopc_wizard.jar;d:/altera/10.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"d:/altera/10.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0014_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0014_sopclgen/yysystem.v --quartus_dir="d:/altera/10.1/quartus" --sopc_perl="d:/altera/10.1/quartus/bin/perl" --sopc_lib_path="++d:/altera/10.1/quartus/../ip/altera/sopc_builder_ip+d:/altera/10.1/quartus/../ip/altera/nios2_ip" 2011.08.09.12:12:53 [Progress] No .sopc_builder configuration file(!) 2011.08.09.12:12:53 [Progress] . 2011.08.09.12:12:55 [Progress] # 2011.08.09 12:12:55 (*) Success: sopc_builder finished. 2011.08.09.12:12:56 [Info] onchip_ram: "cpu_system" instantiated altera_avalon_onchip_memory2 "onchip_ram" 2011.08.09.12:12:56 [Debug] cpu_system: queue size: 50 starting:altera_avalon_jtag_uart "submodules/altera_avalon_jtag_uart_nbmdwotd" 2011.08.09.12:12:56 [Info] Starting PTF file elaboration. 2011.08.09.12:12:57 [Progress] "d:/altera/10.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "d:/altera/10.1/quartus/sopc_builder/bin/sopc_builder.jar;d:/altera/10.1/quartus/sopc_builder/bin/PinAssigner.jar;d:/altera/10.1/quartus/sopc_builder/bin/sopc_wizard.jar;d:/altera/10.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"d:/altera/10.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0015_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0015_sopclgen/yysystem.v --quartus_dir="d:/altera/10.1/quartus" --sopc_perl="d:/altera/10.1/quartus/bin/perl" --sopc_lib_path="++d:/altera/10.1/quartus/../ip/altera/sopc_builder_ip+d:/altera/10.1/quartus/../ip/altera/nios2_ip" 2011.08.09.12:12:58 [Info] Finished elaborating PTF file. 2011.08.09.12:12:58 [Progress] Executing: D:/altera/10.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0015_sopclgen/yysystem.ptf 2011.08.09.12:12:58 [Info] Starting generation... 2011.08.09.12:12:59 [Progress] "d:/altera/10.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "d:/altera/10.1/quartus/sopc_builder/bin/sopc_builder.jar;d:/altera/10.1/quartus/sopc_builder/bin/PinAssigner.jar;d:/altera/10.1/quartus/sopc_builder/bin/sopc_wizard.jar;d:/altera/10.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"d:/altera/10.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0015_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0015_sopclgen/yysystem.v --quartus_dir="d:/altera/10.1/quartus" --sopc_perl="d:/altera/10.1/quartus/bin/perl" --sopc_lib_path="++d:/altera/10.1/quartus/../ip/altera/sopc_builder_ip+d:/altera/10.1/quartus/../ip/altera/nios2_ip" 2011.08.09.12:13:01 [Progress] No .sopc_builder configuration file(!) 2011.08.09.12:13:01 [Progress] . 2011.08.09.12:13:02 [Progress] # 2011.08.09 12:13:02 (*) Success: sopc_builder finished. 2011.08.09.12:13:02 [Info] jtag_uart: "cpu_system" instantiated altera_avalon_jtag_uart "jtag_uart" 2011.08.09.12:13:02 [Debug] cpu_system: queue size: 49 starting:altera_nios2_qsys "submodules/altera_nios2_qsys_be44pvus" 2011.08.09.12:13:03 [Info] cpu: Starting RTL generation for module 'altera_nios2_qsys_be44pvus' 2011.08.09.12:13:03 [Info] cpu: Generation command is [exec D:/altera/10.1/ip/altera/nios2_ip/altera_nios2//eperl.exe -I D:/altera/10.1/quartus/common/ip/altera/common/perl/5.8.3 -I D:/altera/10.1/quartus/sopc_builder/bin/europa -I D:/altera/10.1/quartus/sopc_builder/bin/perl_lib -I D:/altera/10.1/quartus/sopc_builder/bin -I D:/altera/10.1/ip/altera/nios2_ip/altera_nios2//cpu_lib -I D:/altera/10.1/ip/altera/nios2_ip/altera_nios2//nios_lib -I D:/altera/10.1/ip/altera/nios2_ip/altera_nios2/ -I D:/altera/10.1/quartus/../ip/altera/nios2_ip/altera_nios2 -- D:/altera/10.1/ip/altera/nios2_ip/altera_nios2//generate_rtl.epl --name=altera_nios2_qsys_be44pvus --dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0016_sopcgen/ --quartus_dir=D:/altera/10.1/quartus --verilog --config=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0016_sopcgen//altera_nios2_qsys_be44pvus_processor_configuration.pl --do_build_sim=1 --sim_dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0016_sopcgen/ --bogus ] 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:03 (*) Starting Nios II generation 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:03 (*) No license required to generate encrypted Nios II/e. 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:03 (*) Elaborating CPU configuration settings 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:03 (*) Creating all objects for CPU 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:05 (*) Creating 'C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0016_sopcgen//altera_nios2_qsys_be44pvus.do' 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:05 (*) Generating RTL from CPU objects 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:05 (*) Creating plain-text RTL 2011.08.09.12:13:06 [Info] cpu: # 2011.08.09 12:13:06 (*) Done Nios II generation 2011.08.09.12:13:06 [Info] cpu: Done RTL generation for module 'altera_nios2_qsys_be44pvus' 2011.08.09.12:13:06 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.08.09.12:13:06 [Debug] Command: D:/altera/10.1/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0017_sopcqmap/not_a_project_setup.tcl 2011.08.09.12:13:06 [Debug] Command: D:/altera/10.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0016_sopcgen/altera_nios2_qsys_be44pvus.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0017_sopcqmap/ 2011.08.09.12:13:09 [Debug] Command took 2.297s 2011.08.09.12:13:11 [Debug] Command took 2.687s 2011.08.09.12:13:11 [Info] cpu: "cpu_system" instantiated altera_nios2_qsys "cpu" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 48 starting:altera_avalon_mm_bridge "submodules/altera_avalon_mm_bridge" 2011.08.09.12:13:11 [Info] pipeline_bridge: "cpu_system" instantiated altera_avalon_mm_bridge "pipeline_bridge" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 47 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.08.09.12:13:11 [Info] cpu_instruction_master_translator: "cpu_system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 45 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.08.09.12:13:11 [Info] cpu_jtag_debug_module_translator: "cpu_system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 41 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.08.09.12:13:11 [Info] cpu_instruction_master_translator_avalon_universal_master_0_agent: "cpu_system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 39 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.08.09.12:13:11 [Info] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "cpu_system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 38 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.08.09.12:13:11 [Info] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "cpu_system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 30 starting:altera_merlin_router "submodules/altera_merlin_router_kzjlm7w5" 2011.08.09.12:13:11 [Info] addr_router: "cpu_system" instantiated altera_merlin_router "addr_router" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 29 starting:altera_merlin_router "submodules/altera_merlin_router_afjukysr" 2011.08.09.12:13:11 [Info] addr_router_001: "cpu_system" instantiated altera_merlin_router "addr_router_001" 2011.08.09.12:13:11 [Debug] cpu_system: queue size: 28 starting:altera_merlin_router "submodules/altera_merlin_router_ieor7irj" 2011.08.09.12:13:12 [Info] id_router: "cpu_system" instantiated altera_merlin_router "id_router" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 24 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.08.09.12:13:12 [Info] limiter: "cpu_system" instantiated altera_merlin_traffic_limiter "limiter" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 22 starting:altera_reset_controller "submodules/altera_reset_controller" 2011.08.09.12:13:12 [Info] rst_controller: "cpu_system" instantiated altera_reset_controller "rst_controller" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 20 starting:altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_4sitf4to" 2011.08.09.12:13:12 [Info] cmd_xbar_demux: "cpu_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 18 starting:altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_7t5ew22p" 2011.08.09.12:13:12 [Info] cmd_xbar_mux: "cpu_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 14 starting:altera_merlin_demultiplexer "submodules/altera_merlin_demultiplexer_2hdz7hhu" 2011.08.09.12:13:12 [Info] rsp_xbar_demux: "cpu_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 10 starting:altera_merlin_multiplexer "submodules/altera_merlin_multiplexer_cuej2q2z" 2011.08.09.12:13:12 [Info] rsp_xbar_mux: "cpu_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" 2011.08.09.12:13:12 [Info] Reusing file D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_merlin_arbitrator.sv 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 8 starting:altera_avalon_dc_fifo "submodules/altera_avalon_dc_fifo" 2011.08.09.12:12:11 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.08.09.12:12:11 [Debug] Command: D:/altera/10.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/altera/10.1/ip/altera/sopc_builder_ip/altera_avalon_dc_fifo/altera_avalon_dc_fifo.v --source=D:/altera/10.1/ip/altera/sopc_builder_ip/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v --source=D:/altera/10.1/ip/altera/sopc_builder_ip/altera_avalon_dc_fifo/altera_avalon_dc_fifo.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5195_4366959288237815494.dir/0011_sopcqmap/ 2011.08.09.12:12:13 [Debug] Command took 2.703s 2011.08.09.12:13:12 [Info] async_fifo: "cpu_system" instantiated altera_avalon_dc_fifo "async_fifo" 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 4 starting:altera_avalon_st_pipeline_stage "submodules/altera_avalon_st_pipeline_stage" 2011.08.09.12:13:12 [Info] limiter_pipeline: "cpu_system" instantiated altera_avalon_st_pipeline_stage "limiter_pipeline" 2011.08.09.12:13:12 [Info] Reusing file D:/Home/User/My Documents/Memtest/Memtest/systems/cpu_system/synthesis/submodules/altera_avalon_st_pipeline_base.v 2011.08.09.12:13:12 [Debug] cpu_system: queue size: 0 starting:altera_irq_mapper "submodules/altera_irq_mapper_2ia6qhff" 2011.08.09.12:13:12 [Info] irq_mapper: "cpu_system" instantiated altera_irq_mapper "irq_mapper" 2011.08.09.12:13:12 [Info] cpu_system: Done cpu_system" with 22 modules, 49 files, 1477640 bytes