Quantum computing emulators are widely used for testing quantum algorithms prior to the execution on real quantum processors. Scientists are very active in developing emulators on FPGAs.

Dr. Agostino Giorgio’s  team (Polytechnic University of Bari-Italy ) leveraged the Terasic FPGA based development kits to develop a quantum gate simulator in the MATLAB^®  environment, and translated the simulator into an HDL design for FPGA implementation by using the MATLAB’s HDL Coder toolbox. With this new method, designers can leverage the useful and straightforward model-based design approach offered by MATLAB, as well as the highly optimized HDL code for configuring the FPGA as a quantum computing emulator. The procedure has been successfully applied and tested to create a single-qubit emulator and a two-qubit emulator, both implemented on Altera FPGAs.

Two implementation examples based on Altera FPGAs and the famous Terasic development kits DE1-SoC  and DE5a-Net DDR4 .

Hardware Implementation

The hardware implementation was carried out using Altera FPGAs, mounted on Terasic boards. The development environment used was Intel’s Quartus IDE.

	The single-qubit emulator was implemented on The Terasic DE1-SoC development kit  based on Altera Cyclone®  V FPGA.
	The two-qubit emulator requires larger resources. The Terasic DE5a-Net DDR4 accelerator card  based on Altera Arria®  10 GX family is the ideal platform for implementation.