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Terasic News Labs News Release of Teaching Materials for the Altera DE2 Board
 





Release of Teaching Materials for the Altera DE2 Board

We would like to inform you about some major new developments in the teaching materials provided for Altera's DE2 Development and Education board. We hope that you have had a chance to experiment with your DE2 board, or perhaps have gone ahead and established a teaching laboratory using this board at your school. Since we introduced the DE2 board earlier this year, DE2 teaching laboratories have been set up at more than 100 universities.

DIGITAL LOGIC TEACHING MATERIAL

In the summer of 2006 we released a comprehensive set of tutorials and laboratory experiments for use in digital logic courses. The tutorials have been written with a sophomore student in mind. They include step-by-step instructions and explain how to use Altera's Quartus II software with the DE2 board. The laboratory experiments span all of the important concepts in a digital logic course. They are designed to provide a strong learning experience that encourages students to create and test small circuits, and then use these proven designs to build larger, more interesting projects. We provide illustrative solutions, protected by passwords given only to registered instructors, in both VHDL and Verilog HDL for all of these experiments. To make it easy for instructors to combine Altera's teaching material with their own, we provide the source files of the text collate utf8_unicode_ci and figures used in the laboratory descriptions. This material can be found at

http://www.altera.com/education/univ/materials/manual/unv-lab-manual.html

COMPUTER ORGANIZATION and EMBEDDED SYSTEMS TEACHING MATERIAL

We have launched the first installment of our teaching material for computer organization and/or embedded systems courses, which makes use of the Nios II processor. We provide tutorials that introduce the Nios II instruction set architecture and show how to use the Quartus II software and its SOPC Builder tool to create embedded systems. We also provide the Altera Debug Client utility which allows students to easily compile, assemble, download and debug programs written in either the Nios II assembly language or in the C language. The Debug Client allows the user to explore how the programs are executed by the processor. It displays the contents of the processor registers and system memory, and includes features such as single-step execution, breakpoints and program trace. We have also released a set of five laboratory experiments (with more to be provided over the next three months) on the topics that include basic computer system concepts, program-controlled I/O (polling), subroutines and stacks, interrupts, and bus communication. Illustrative solutions to these experiments are available to instructors under password protection. We are confident that this teaching material will enhance the usefulness of the DE2 board in the teaching environment and make it easy to create a rewarding laboratory experience for the students. To learn more, please visit

http://www.altera.com/education/univ/materials/manual/unv-lab-manual.html

 EMBEDDED PERIPHERALS IP CORES

Over the next couple of months we will be completing the release of a library of SOPC Builder components (IP cores) for all of the I/O devices on the DE2 board. These components can be used as part of the SOPC Builder tool in the Quartus II software. They allow students to easily create Nios II systems that can access all of the I/O devices on the DE2 board. We will also provide associated software drivers that can be incorporated into an Altera Debug Client project (or an Altera Nios II IDE project), and will provide several example projects using the software. A detailed schedule for the release of these IP cores is shown at the end of this message.

The currently-available components in the library, and release notes for them, can be downloaded from

ftp://ftp.altera.com/up/pub/University_Program_IP_Cores/UP_IP_Library.exe

ftp://ftp.altera.com/up/pub/University_Program_IP_Cores/ReleaseNotes.txt

FINAL REMARKS

If you wish to request additional DE2 boards, please visit our Board Donation or Board Purchase web pages, which an be reached from

http://www.altera.com/education/univ/unv-index.html

 

Sincerely,

University Program Team: Prof. Stephen Brown, Blair Fort, Mike Phipps, Ralene Marcoccia, and Prof. Zvonko Vranesic

 


P.S. the SOPC Builder component release schedule is shown below.

** The IP library will be installed into the SOPC Builder's component directory. After the library is installed, you can find these IP cores in SOPC Builder in the component list under the “University Program DE2 Board” group. Documentation for the IP cores can be found in the Window’s START->Altera->Altera University Program IP Cores menu, or by right-clicking on the component in SOPC Builder and opening the “Data Sheet”.

Component Name

Description

Friday, November 3, 2006

Avalon to External Bus Bridge

Allow easy creation of slave peripherals for SOPC Builder Systems

External Bus to Avalon Bridge

Allow easy creation of masters peripherals for SOPC Builder Systems

DE2 PIO

General parallel input/output

SRAM

Controller for the SRAM chip

Friday, November 17, 2006

Character LCD

Controller for the Character LCD (16x2)

PS2 Port

Controller for both PS2 Keyboard and Mouse

SDRAM

Controller for the SDRAM chip

VGA

Drives the VGA DAC and contains frame buffer

Friday, December 1, 2006

RS232

UART Communication

IrDA

UART Communication

Audio In/Out

Drives the Audio ADC and DAC

Video In

Converts video input for processing

Audio/Video Configuration

Simplifies the configuration of the Audio and Video In Chips

Friday, December 22, 2006

Ethernet

Controller plus IP stack

USB

Handles USB communication

SD Card

Enables reads and writes to SD cards

Flash memory

Controller for the flash memory chip

 


 

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