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Terasic News Labs News Terasic Announces Its New DE4 Development Board
 





Terasic Announces Its New DE4 Development Board

Bringing focus on innovation and differentiation when designing with bandwidth-intensive applications

Terasic, world leading FPGA based products and service supplier, issued its newest DE4 development and educational platform, which addresses today's high performance and ultra high speed interconnecting requirements. Featuring an 8-lane PCI Express 2.0 interface, four Gigabit Ethernet ports and two HSMC connectors, the DE4 demonstrates the capability of a sustained throughput bandwidth up to 5GByte/sec when communicating with a host PC. With the help of precise pre-defined Hspice simulation and professional design, transceiver channels on HSMC and SATA II interfaces achieved speeds up to 10Gbps.

The DE4 is powered by an Altera Stratix IV GX series 40-nm FPGA chip directly coupled to abundant peripherals and interfaces. Two separate DDR2 SO-DIMM sockets provide maximum of 8GB RAM capacity and 100Gbps bandwidth. Two HSMC connectors provide additional functionality and connectivity via HSMC daughter cards, as well as deploying large-scale ASIC prototype development using multiple DE4/FPGA boards. Four Gigabit Ethernet ports offer solutions for networking over copper media with serial interfaces at 1.25Gbps per port. The onboard CFI Flash, ZBT SSRAM, USB OTG and power monitor functionalities make DE4 a hybrid, universal, and versatile FPGA based platform.

With the world's largest and fastest 40-nm FPGA, DE4 is an ideal choice for use in high-end digital applications including wireless, embedded industrial, military, broadcast, and consumer electronics. The DE4 takes advantage of key features within the Stratix IV GX device by utilizing the high-speed serial transceivers to fully compliant with PCI Express 2.0 specification. This will accelerate mainstream development of PCI Express-based applications enabling customers to deploy designs for a broad range of high-speed connectivity.

DE4 also meets the market demand for ASIC prototyping where developers can perform verification of their next generation ASIC or ASSP design and compute intensive applications such as machine vision & imaging and bio-information.
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