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A5GT

Altera Arria V GT FPGA Development Kit

Unit 1: Arria V GT FPGA: 5AGTFD7K3F40I3N

  • Memory
    • 1,152-MB x72 DDR3 SDRAM
    • 4.5-MB (1 Mb x 36) QDR II+ SRAM
    • 1-Gb sync flash (x16)
  • Communication ports
    • PCI Express® (PCIe® ) x8 edge connector
    • HSMC Port A (Eight transceiver channels)
    • USB 2.0
    • Gbps Ethernet
    • Chip-to-chip bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers
    • Two SFP+ channel
    • Bull's Eye connector (Three 10-Gbps transceiver channel)
    • SMA connector (One 10-Gbps transceiver channel)
  • Configuration
    • JTAG
    • Fast passive parallel (FPP) parallel flash loader (PFL)
  • Buttons, switches, LEDs, and displays
    • One CPU reset push button
    • Three user push buttons
    • Eight dual in-line package (DIP) switches
    • 16 user LEDs (eight bi-color diodes)
    • Three PCIe LEDs
    • Three HSMA Status LEDs
    • 16x2 character LCD

Unit 2: Arria V GT FPGA: 5AGTFD7K3F40I3N

  • Memory
    • x64 DDR3 SDRAM soft controller (or x32 hard intellectual property (IP) controller)
  • Communication ports
    • HSMC Port B (Four transceiver channels)
    • FMC Port (Ten transceiver channels)
    • Chip-to-chip bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers
    • One serial digital interface (SDI) channel
    • Bull's Eye connector (One 6-Gbps transceiver channel)
    • Bull's Eye connector (One 10-Gbps transceiver channel)
    • SMA connector (One 10-Gbps transceiver channel)
  • Configuration
    • JTAG
    • FPP PFL
  • Buttons, switches, LEDs, and displays
    • One CPU reset push button
    • Three user push buttons
    • Eight DIP switches
    • 16 user LEDs (eight bi-color diodes)

Miscellaneous

  • EPM2210GF324 system controller
  • EPM570GM100 on-board USB-Blaster II download cable

Clocking

  • 50 MHz and 148.5-MHz oscillator
  • 100 MHz and four 4 output programmable oscillators
  • SMA input (LVPECL)

Power

  • Laptop DC input
  • PCIe edge connector

System monitoring

  • Power (voltage, current, and wattage)—per unit per rail

Arria V GT FPGA Development Board Block Diagram

Arria V GT FPGA Development Board Block Diagram



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