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Peter Athanas - Professor, Virginia Tech, Dept of ECE
 





Peter Athanas - Professor, Virginia Tech, Dept of ECE

Peter Athanas

  • BSEE, University of Toledo
  • MSEE, Rensselaer Polytechnic Institute
  • ScM Applied Math, PhD EE, Brown University
  • Director of the Virginia Tech Configurable Computing Lab
  • Site Director, National Science Foundation Center for High-Performance Reconfigurable Computing (CHREC)
  • Renovated VT Computer Engineering to include FPGAs and digital design at low-level classes, and expanded senior/graduate courses.


In my evaluation, I developed/prototyped laboratory exercises that I ultimately crafted as assignments to a class I’m teaching this semester. The class is ECE4514 -- a seniorlevel elective in advanced digital design. At Virginia Tech, we introduce the students to the DE0-Nano their sophomore year where they start their HDL instruction. In their junior year, they take a required more advanced digital design course, where they do their first set of experiments on the DE1- SoC . After this core course, there are three other undergraduate courses that use either the DE1- SOC or the DE2-115 : hardware / software co-design, secure hardware design, and ECE4514 -- the course I'm teaching this semester. In addition, various graduate classes use the boards, depending on the instructor.


In my evaluation of the DE10, I used the assignments in ECE4514 as a means of Testing the board. The course focuses on performance issues in digital design (Designing for high throughput, designing for area, and designing for low power). This course had nine projects -- six of which were implemented on the DE1- SoC (and Prototyped on the DE10). Some of the assignments included: performance implementation of sin(x)/x, area efficient implementation of sin(x)/x, low power implementation of sin(x)/x, custom floating point implementation of sin(x)/x, and a fancy graphics-oriented project that did some simple object manipulations. Most of these projects were performance oriented and focused on refining coding skills, and didn't have a lot of I/O needs beyond memory and blinky lights. In many cases, the ARM was used to interrogate the students’ designs to verify functionality. Communications was performed via JTAG UART for both the DE1/DE10 platforms. In all of the early assignments, the hardware and software code that I had prototyped on VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY. An equal opportunity, affirmative action institution the DE10-Standard ported directly to the DE1- SoC .  I also tested AOCL on the DE10 platform, where I prototyped an OpenCL assignment that I gave to the students. This assignment also had limited I/O, yet exercised the deployment of multiple kernels (sin x/x again). Their final project pulls all of these things together, which I thought would be an aggressive test on the electrical infrastructure of the DE10 since we push the power and clock frequencies to the maximum. This semester's final project is a variant of the classic Mandelbrot problem, which additionally used the VGA interface. Students were evaluated on the speed and color depth of their implementation, and often came close to 100% usage of the chip resources.

As I mentioned, I had some initial trouble getting their final project operational on the DE10. To test the tools, I used Terasic’s SystemBuilder to generate the project files (for the other assignments, I had generated them by hand). It turns out that most of my difficulty resided in wrong assumptions I made in the SystemBuilder generated files. In the end, I concluded SystemBuilder works fine.

One item on my TODO list was to explore the new display on the DE10-- regretfully, I've still not had the time to do this. This will be a source of many interesting experiments for the students.

The most common failure we've seen on the DE1- SoC is the microUSB connector bending and breaking off due to repeated plug/unplug by the students. I was pleased to learn that you upgraded this to a stronger mini-USB connector for the DE10-Standard .

Overall, the DE10 is a solid design. It mirrors the DE1- SoC nicely, so that our faculty will not be shocked to learn a new platform. Transitioning to the DE10-Standard should not be burdensome. In many cases, the transition merely would involve the replacement of the project settings file (QSF) since both platforms share many of the same resources. The additional FPGA capacity of the DE10 FPGA will probably not be appreciated in the lower classes, but would be welcomed in the advanced courses. When it becomes available, I'll recommend that we transition to the DE10. We still have a large population of DE1- SoC platforms that we will continue to use, yet as they wear, we will replace them in class-size batches.

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