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母板 Stratix V TR5-Lite
 





TR5-Lite

TR5-Lite

The TR5-Lite Board

Altera Stratix® V GX FPGA (5SGXEA7N2F45C2)

  • JTAG header for FPGA programming
  • Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory

General user input / output:

  • 4 LEDs
  • 1 LED Array
  • 2 push-buttons
  • 2-position DIP switch

On-Board Clock

  • 50MHz Oscillator
  • Programmable oscillators Si570 and CDCM61004

Memory

  • 36MB 550MHZ ISSI
  • 2GB 933MHz DDR3 SDRAM
  • 256MB FLASH

Communication Ports

  • Two SFP+ connectors
  • One Serial ATA (SATA II) host port
  • PCI Express (PCIe) x8 edge connector
  • One RS422 transceiver with 1394 connector

System Monitor and Control

  • Temperature sensor
  • Fan control

Power

  • PCI Express 6-pin power connector, 12V DC Input
  • PCI Express edge connector power

Mechanical Specification

  • PCI Express low-profile and half-length

Connectivity

 連接示意圖

 

 

 

 

 

 

 

 



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