# TCL File Generated by Component Editor 10.0
# Wed Aug 11 09:28:05 CST 2010
# DO NOT MODIFY


# +-----------------------------------
# | 
# | VGA_NIOS_CTRL "Binary_VGA_Controller_IF" v1.0
# | David Wei 2010.08.11.09:28:05
# | 
# | 
# | E:/SVN/DE2_70_demonstrations/DE2_70_NIOS_HOST_MOUSE_VGA/ip/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v
# | 
# |    ./VGA_NIOS_CTRL.v syn
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.0
# | 
package require -exact sopc 10.0
# | 
# +-----------------------------------

# +-----------------------------------
# | module VGA_NIOS_CTRL
# | 
set_module_property DESCRIPTION ""
set_module_property NAME VGA_NIOS_CTRL
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP "Terasic Technologies Inc."
set_module_property AUTHOR "David Wei"
set_module_property DISPLAY_NAME Binary_VGA_Controller_IF
set_module_property TOP_LEVEL_HDL_FILE VGA_NIOS_CTRL.v
set_module_property TOP_LEVEL_HDL_MODULE VGA_NIOS_CTRL
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file VGA_NIOS_CTRL.v SYNTHESIS
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
add_parameter RAM_SIZE INTEGER 307200 ""
set_parameter_property RAM_SIZE DEFAULT_VALUE 307200
set_parameter_property RAM_SIZE DISPLAY_NAME RAM_SIZE
set_parameter_property RAM_SIZE TYPE INTEGER
set_parameter_property RAM_SIZE UNITS None
set_parameter_property RAM_SIZE ALLOWED_RANGES -2147483648:2147483647
set_parameter_property RAM_SIZE DESCRIPTION ""
set_parameter_property RAM_SIZE AFFECTS_GENERATION false
set_parameter_property RAM_SIZE HDL_PARAMETER true
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1_clock
# | 
add_interface s1_clock clock end

set_interface_property s1_clock ENABLED true

add_interface_port s1_clock avs_s1_clk_iCLK clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1_clock_reset
# | 
add_interface s1_clock_reset reset end
set_interface_property s1_clock_reset associatedClock s1_clock
set_interface_property s1_clock_reset synchronousEdges DEASSERT

set_interface_property s1_clock_reset ASSOCIATED_CLOCK s1_clock
set_interface_property s1_clock_reset ENABLED true

add_interface_port s1_clock_reset avs_s1_reset_n_iRST_N reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point global_signals_export
# | 
add_interface global_signals_export conduit end

set_interface_property global_signals_export ENABLED true

add_interface_port global_signals_export avs_s1_export_VGA_R export Output 10
add_interface_port global_signals_export avs_s1_export_VGA_G export Output 10
add_interface_port global_signals_export avs_s1_export_VGA_B export Output 10
add_interface_port global_signals_export avs_s1_export_VGA_HS export Output 1
add_interface_port global_signals_export avs_s1_export_VGA_VS export Output 1
add_interface_port global_signals_export avs_s1_export_VGA_SYNC export Output 1
add_interface_port global_signals_export avs_s1_export_VGA_BLANK export Output 1
add_interface_port global_signals_export avs_s1_export_VGA_CLK export Output 1
add_interface_port global_signals_export avs_s1_export_iCLK_25 export Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1
# | 
add_interface s1 avalon end
set_interface_property s1 addressAlignment NATIVE
set_interface_property s1 associatedClock s1_clock
set_interface_property s1 associatedReset s1_clock_reset
set_interface_property s1 burstOnBurstBoundariesOnly false
set_interface_property s1 explicitAddressSpan 0
set_interface_property s1 holdTime 0
set_interface_property s1 isMemoryDevice false
set_interface_property s1 isNonVolatileStorage false
set_interface_property s1 linewrapBursts false
set_interface_property s1 maximumPendingReadTransactions 0
set_interface_property s1 printableDevice false
set_interface_property s1 readLatency 0
set_interface_property s1 readWaitStates 0
set_interface_property s1 readWaitTime 0
set_interface_property s1 setupTime 0
set_interface_property s1 timingUnits Cycles
set_interface_property s1 writeWaitTime 0

set_interface_property s1 ASSOCIATED_CLOCK s1_clock
set_interface_property s1 ENABLED true

add_interface_port s1 avs_s1_writedata_iDATA writedata Input 16
add_interface_port s1 avs_s1_readdata_oDATA readdata Output 16
add_interface_port s1 avs_s1_address_iADDR address Input 19
add_interface_port s1 avs_s1_write_iWR write Input 1
add_interface_port s1 avs_s1_read_iRD read Input 1
add_interface_port s1 avs_s1_chipselect_iCS chipselect Input 1
# | 
# +-----------------------------------
