# TCL File Generated by Component Editor 10.0
# Wed Aug 11 09:27:45 CST 2010
# DO NOT MODIFY


# +-----------------------------------
# | 
# | ISP1362_IF "ISP1362_IF" v1.0
# | Richard Chang 2010.08.11.09:27:45
# | 
# | 
# | E:/SVN/DE2_70_demonstrations/DE2_70_NIOS_HOST_MOUSE_VGA/ip/TERASIC_ISP1362/hdl/ISP1362_IF.v
# | 
# |    ./ISP1362_IF.v syn
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.0
# | 
package require -exact sopc 10.0
# | 
# +-----------------------------------

# +-----------------------------------
# | module ISP1362_IF
# | 
set_module_property DESCRIPTION ""
set_module_property NAME ISP1362_IF
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP "Terasic Technologies Inc."
set_module_property AUTHOR "Richard Chang"
set_module_property DISPLAY_NAME ISP1362_IF
set_module_property TOP_LEVEL_HDL_FILE ISP1362_IF.v
set_module_property TOP_LEVEL_HDL_MODULE ISP1362_IF
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file ISP1362_IF.v SYNTHESIS
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point hc_clock
# | 
add_interface hc_clock clock end

set_interface_property hc_clock ENABLED true

add_interface_port hc_clock avs_hc_clk_iCLK clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point hc_clock_reset
# | 
add_interface hc_clock_reset reset end
set_interface_property hc_clock_reset associatedClock hc_clock
set_interface_property hc_clock_reset synchronousEdges DEASSERT

set_interface_property hc_clock_reset ASSOCIATED_CLOCK hc_clock
set_interface_property hc_clock_reset ENABLED true

add_interface_port hc_clock_reset avs_hc_reset_n_iRST_N reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point dc_clock
# | 
add_interface dc_clock clock end

set_interface_property dc_clock ENABLED true

add_interface_port dc_clock avs_dc_clk_iCLK clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point dc_clock_reset
# | 
add_interface dc_clock_reset reset end
set_interface_property dc_clock_reset associatedClock dc_clock
set_interface_property dc_clock_reset synchronousEdges DEASSERT

set_interface_property dc_clock_reset ASSOCIATED_CLOCK dc_clock
set_interface_property dc_clock_reset ENABLED true

add_interface_port dc_clock_reset avs_dc_reset_n_iRST_N reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point global_signals_export
# | 
add_interface global_signals_export conduit end

set_interface_property global_signals_export ENABLED true

add_interface_port global_signals_export avs_dc_export_OTG_INT1 export Input 1
add_interface_port global_signals_export avs_hc_export_OTG_DATA export Bidir 16
add_interface_port global_signals_export avs_hc_export_OTG_ADDR export Output 2
add_interface_port global_signals_export avs_hc_export_OTG_RD_N export Output 1
add_interface_port global_signals_export avs_hc_export_OTG_WR_N export Output 1
add_interface_port global_signals_export avs_hc_export_OTG_CS_N export Output 1
add_interface_port global_signals_export avs_hc_export_OTG_RST_N export Output 1
add_interface_port global_signals_export avs_hc_export_OTG_INT0 export Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point hc
# | 
add_interface hc avalon end
set_interface_property hc addressAlignment NATIVE
set_interface_property hc associatedClock hc_clock
set_interface_property hc associatedReset hc_clock_reset
set_interface_property hc burstOnBurstBoundariesOnly false
set_interface_property hc explicitAddressSpan 0
set_interface_property hc holdTime 140
set_interface_property hc isMemoryDevice false
set_interface_property hc isNonVolatileStorage false
set_interface_property hc linewrapBursts false
set_interface_property hc maximumPendingReadTransactions 0
set_interface_property hc printableDevice false
set_interface_property hc readLatency 0
set_interface_property hc readWaitStates 50
set_interface_property hc readWaitTime 50
set_interface_property hc setupTime 140
set_interface_property hc timingUnits Nanoseconds
set_interface_property hc writeWaitStates 50
set_interface_property hc writeWaitTime 50

set_interface_property hc ASSOCIATED_CLOCK hc_clock
set_interface_property hc ENABLED true

add_interface_port hc avs_hc_writedata_iDATA writedata Input 16
add_interface_port hc avs_hc_readdata_oDATA readdata Output 16
add_interface_port hc avs_hc_address_iADDR address Input 1
add_interface_port hc avs_hc_read_n_iRD_N read_n Input 1
add_interface_port hc avs_hc_write_n_iWR_N write_n Input 1
add_interface_port hc avs_hc_chipselect_n_iCS_N chipselect_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point hc_irq
# | 
add_interface hc_irq interrupt end
set_interface_property hc_irq associatedAddressablePoint hc
set_interface_property hc_irq associatedClock hc_clock
set_interface_property hc_irq associatedReset hc_clock_reset

set_interface_property hc_irq ASSOCIATED_CLOCK hc_clock
set_interface_property hc_irq ENABLED true

add_interface_port hc_irq avs_hc_irq_n_oINT0_N irq_n Output 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point dc
# | 
add_interface dc avalon end
set_interface_property dc addressAlignment NATIVE
set_interface_property dc associatedClock dc_clock
set_interface_property dc associatedReset dc_clock_reset
set_interface_property dc burstOnBurstBoundariesOnly false
set_interface_property dc explicitAddressSpan 0
set_interface_property dc holdTime 150
set_interface_property dc isMemoryDevice false
set_interface_property dc isNonVolatileStorage false
set_interface_property dc linewrapBursts false
set_interface_property dc maximumPendingReadTransactions 0
set_interface_property dc printableDevice false
set_interface_property dc readLatency 0
set_interface_property dc readWaitStates 150
set_interface_property dc readWaitTime 150
set_interface_property dc setupTime 150
set_interface_property dc timingUnits Nanoseconds
set_interface_property dc writeWaitStates 150
set_interface_property dc writeWaitTime 150

set_interface_property dc ASSOCIATED_CLOCK dc_clock
set_interface_property dc ENABLED true

add_interface_port dc avs_dc_writedata_iDATA writedata Input 16
add_interface_port dc avs_dc_readdata_oDATA readdata Output 16
add_interface_port dc avs_dc_address_iADDR address Input 1
add_interface_port dc avs_dc_read_n_iRD_N read_n Input 1
add_interface_port dc avs_dc_write_n_iWR_N write_n Input 1
add_interface_port dc avs_dc_chipselect_n_iCS_N chipselect_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point dc_irq
# | 
add_interface dc_irq interrupt end
set_interface_property dc_irq associatedAddressablePoint dc
set_interface_property dc_irq associatedClock dc_clock
set_interface_property dc_irq associatedReset dc_clock_reset

set_interface_property dc_irq ASSOCIATED_CLOCK dc_clock
set_interface_property dc_irq ENABLED true

add_interface_port dc_irq avs_dc_irq_n_oINT0_N irq_n Output 1
# | 
# +-----------------------------------
