# TCL File Generated by Component Editor 10.0
# Wed Aug 11 09:52:49 CST 2010
# DO NOT MODIFY


# +-----------------------------------
# | 
# | AUDIO_IF "AUDIO_IF" v1.0
# | Richard Chang 2010.08.11.09:52:49
# | 
# | 
# | E:/SVN/DE2_70_demonstrations/DE2_70_NIOS_HOST_MOUSE_VGA/ip/TERASIC_AUDIO/hdl/AUDIO_IF.v
# | 
# |    ./AUDIO_IF.v syn
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.0
# | 
package require -exact sopc 10.0
# | 
# +-----------------------------------

# +-----------------------------------
# | module AUDIO_IF
# | 
set_module_property DESCRIPTION ""
set_module_property NAME AUDIO_IF
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP "Terasic Technologies Inc."
set_module_property AUTHOR "Richard Chang"
set_module_property DISPLAY_NAME AUDIO_IF
set_module_property TOP_LEVEL_HDL_FILE AUDIO_IF.v
set_module_property TOP_LEVEL_HDL_MODULE AUDIO_IF
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file AUDIO_IF.v SYNTHESIS
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1_clock
# | 
add_interface s1_clock clock end

set_interface_property s1_clock ENABLED true

add_interface_port s1_clock avs_s1_clk clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1_clock_reset
# | 
add_interface s1_clock_reset reset end
set_interface_property s1_clock_reset associatedClock s1_clock
set_interface_property s1_clock_reset synchronousEdges DEASSERT

set_interface_property s1_clock_reset ASSOCIATED_CLOCK s1_clock
set_interface_property s1_clock_reset ENABLED true

add_interface_port s1_clock_reset avs_s1_reset reset Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1
# | 
add_interface s1 avalon end
set_interface_property s1 addressAlignment NATIVE
set_interface_property s1 associatedClock s1_clock
set_interface_property s1 associatedReset s1_clock_reset
set_interface_property s1 burstOnBurstBoundariesOnly false
set_interface_property s1 explicitAddressSpan 0
set_interface_property s1 holdTime 0
set_interface_property s1 isMemoryDevice false
set_interface_property s1 isNonVolatileStorage false
set_interface_property s1 linewrapBursts false
set_interface_property s1 maximumPendingReadTransactions 0
set_interface_property s1 printableDevice false
set_interface_property s1 readLatency 0
set_interface_property s1 readWaitStates 0
set_interface_property s1 readWaitTime 0
set_interface_property s1 setupTime 0
set_interface_property s1 timingUnits Cycles
set_interface_property s1 writeWaitTime 0

set_interface_property s1 ASSOCIATED_CLOCK s1_clock
set_interface_property s1 ENABLED true

add_interface_port s1 avs_s1_address address Input 4
add_interface_port s1 avs_s1_read read Input 1
add_interface_port s1 avs_s1_readdata readdata Output 32
add_interface_port s1 avs_s1_write write Input 1
add_interface_port s1 avs_s1_writedata writedata Input 32
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point s1_export
# | 
add_interface s1_export conduit end

set_interface_property s1_export ENABLED true

add_interface_port s1_export avs_s1_export_BCLK export Input 1
add_interface_port s1_export avs_s1_export_DACLRC export Input 1
add_interface_port s1_export avs_s1_export_DACDAT export Output 1
add_interface_port s1_export avs_s1_export_ADCLRC export Input 1
add_interface_port s1_export avs_s1_export_ADCDAT export Input 1
# | 
# +-----------------------------------
