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//use of Altera Corporation's design tools, logic functions and other
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//output files any of the foregoing (including device programming or
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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module i2c (
             // inputs:
              avs_s1_address,
              avs_s1_clk,
              avs_s1_read,
              avs_s1_reset,
              avs_s1_write,
              avs_s1_writedata,

             // outputs:
              avs_s1_export_i2c_clk,
              avs_s1_export_i2c_dat,
              avs_s1_readdata
           )
;

  output           avs_s1_export_i2c_clk;
  inout            avs_s1_export_i2c_dat;
  output  [  7: 0] avs_s1_readdata;
  input            avs_s1_address;
  input            avs_s1_clk;
  input            avs_s1_read;
  input            avs_s1_reset;
  input            avs_s1_write;
  input   [  7: 0] avs_s1_writedata;

  wire             avs_s1_export_i2c_clk;
  wire             avs_s1_export_i2c_dat;
  wire    [  7: 0] avs_s1_readdata;
  I2C_IF the_I2C_IF
    (
      .avs_s1_address        (avs_s1_address),
      .avs_s1_clk            (avs_s1_clk),
      .avs_s1_export_i2c_clk (avs_s1_export_i2c_clk),
      .avs_s1_export_i2c_dat (avs_s1_export_i2c_dat),
      .avs_s1_read           (avs_s1_read),
      .avs_s1_readdata       (avs_s1_readdata),
      .avs_s1_reset          (avs_s1_reset),
      .avs_s1_write          (avs_s1_write),
      .avs_s1_writedata      (avs_s1_writedata)
    );


endmodule

