DEII_70_SOPC |

2010.08.11.12:02:01 | Datasheet

Overview

clk_50 | DEII_70_SOPC
clk
| pio_led
| out_port
| in_port
| in_port
| lcd
| LCD_data
| LCD_E
| LCD_RS
| LCD_RW
| i2c_sclk
| out_port
| bidir_port
| rxd
| txd
| cts_n
| rts_n
| sdram_u1
| zs_addr
| zs_ba
| zs_cas_n
| zs_cke
| zs_cs_n
| zs_dq
| zs_dqm
| zs_ras_n
| zs_we_n
| zs_addr
| zs_ba
| zs_cas_n
| zs_cke
| zs_cs_n
| zs_dq
| zs_dqm
| zs_ras_n
| zs_we_n

Processor
cpu Nios II 10.0
All Components
cpu altera_nios2 10.0
onchip_mem altera_avalon_onchip_memory2 10.0
pio_led altera_avalon_pio 10.0
timer altera_avalon_timer 10.0
timer_stamp altera_avalon_timer 10.0
sysid altera_avalon_sysid 10.0
tristate_bridge_ssram altera_avalon_tri_state_bridge 10.0
jtag_uart altera_avalon_jtag_uart 10.0
seg7 SEG7_IF 1.0
pio_button altera_avalon_pio 10.0
pio_switch altera_avalon_pio 10.0
lcd altera_avalon_lcd_16207 10.0
i2c_sclk altera_avalon_pio 10.0
i2c_sdat altera_avalon_pio 10.0
uart altera_avalon_uart 10.0
sdram_u1 altera_avalon_new_sdram_controller 10.0
sdram_u2 altera_avalon_new_sdram_controller 10.0
tristate_bridge altera_avalon_tri_state_bridge 10.0
audio AUDIO_IF 2.0
pll altpll 10.0
Memory Map

| cpu
instruction_master | data_master
cpu |  |
jtag_debug_module | 0x09408800 | 0x09408800
onchip_mem |  |
s1 | 0x09404000 | 0x09404000
pio_led |  |
s1 |  | 0x094090a0
timer |  |
s1 |  | 0x09409000
timer_stamp |  |
s1 |  | 0x09409020
sysid |  |
control_slave |  | 0x09409110
ssram_2M |  |
s1 | 0x09200000 | 0x09200000
jtag_uart |  |
avalon_jtag_slave |  | 0x09409118
seg7 |  |
s1 |  | 0x09409040
pio_button |  |
s1 |  | 0x094090b0
pio_switch |  |
s1 |  | 0x094090c0
lcd |  |
control_slave |  | 0x094090d0
i2c_sclk |  |
s1 |  | 0x094090e0
i2c_sdat |  |
s1 |  | 0x094090f0
uart |  |
s1 |  | 0x09409060
sdram_u1 |  |
s1 | 0x04000000 | 0x04000000
sdram_u2 |  |
s1 | 0x06000000 | 0x06000000
cfi_flash |  |
s1 | 0x08800000 | 0x08800000
audio |  |
s1 |  | 0x09409080
pll |  |
pll_slave |  | 0x09409100

## clk_50

clock_source v10.0

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## cpu

altera_nios2 v10.0

pll | c0 | cpu
clk
|  | instruction_master | onchip_mem
|  | s1
|  | data_master
|  | s1
|  | data_master | pio_led
|  | s1
|  | data_master | timer
|  | s1
|  | d_irq
|  | irq
|  | data_master | timer_stamp
|  | s1
|  | d_irq
|  | irq
|  | data_master | sysid
|  | control_slave
|  | instruction_master | tristate_bridge_ssram
|  | avalon_slave
|  | data_master
|  | avalon_slave
|  | data_master | jtag_uart
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | seg7
|  | s1
|  | data_master | pio_button
|  | s1
|  | d_irq
|  | irq
|  | data_master | pio_switch
|  | s1
|  | data_master | lcd
|  | control_slave
|  | data_master | i2c_sclk
|  | s1
|  | data_master | i2c_sdat
|  | s1
|  | data_master | uart
|  | s1
|  | d_irq
|  | irq
|  | instruction_master | sdram_u1
|  | s1
|  | data_master
|  | s1
|  | instruction_master | sdram_u2
|  | s1
|  | data_master
|  | s1
|  | instruction_master | tristate_bridge
|  | avalon_slave
|  | data_master
|  | avalon_slave
|  | data_master | audio
|  | s1
|  | data_master | pll
|  | pll_slave

## Parameters

userDefinedSettings |
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Automatic
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | ssram_2M.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _2
mmu_udtlbNumEntries | _2
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _10
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
internalIrqMaskSystemInfo | 31
instSlaveMapParam | <address-map><slave name='sdram_u1.s1' start='0x4000000' end='0x6000000' /><slave name='sdram_u2.s1' start='0x6000000' end='0x8000000' /><slave name='cfi_flash.s1' start='0x8800000' end='0x9000000' /><slave name='ssram_2M.s1' start='0x9200000' end='0x9400000' /><slave name='onchip_mem.s1' start='0x9404000' end='0x9406800' /><slave name='cpu.jtag_debug_module' start='0x9408800' end='0x9409000' /></address-map>
instAddrWidth | 28
impl | Fast
icache_size | _4096
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | ssram_2M.s1
exceptionOffset | 32
deviceFeaturesSystemInfo | M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName | Cyclone II
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _32
dcache_bursts | false
dataSlaveMapParam | <address-map><slave name='sdram_u1.s1' start='0x4000000' end='0x6000000' /><slave name='sdram_u2.s1' start='0x6000000' end='0x8000000' /><slave name='cfi_flash.s1' start='0x8800000' end='0x9000000' /><slave name='ssram_2M.s1' start='0x9200000' end='0x9400000' /><slave name='onchip_mem.s1' start='0x9404000' end='0x9406800' /><slave name='cpu.jtag_debug_module' start='0x9408800' end='0x9409000' /><slave name='timer.s1' start='0x9409000' end='0x9409020' /><slave name='timer_stamp.s1' start='0x9409020' end='0x9409040' /><slave name='seg7.s1' start='0x9409040' end='0x9409060' /><slave name='uart.s1' start='0x9409060' end='0x9409080' /><slave name='audio.s1' start='0x9409080' end='0x94090A0' /><slave name='pio_led.s1' start='0x94090A0' end='0x94090B0' /><slave name='pio_button.s1' start='0x94090B0' end='0x94090C0' /><slave name='pio_switch.s1' start='0x94090C0' end='0x94090D0' /><slave name='lcd.control_slave' start='0x94090D0' end='0x94090E0' /><slave name='i2c_sclk.s1' start='0x94090E0' end='0x94090F0' /><slave name='i2c_sdat.s1' start='0x94090F0' end='0x9409100' /><slave name='pll.pll_slave' start='0x9409100' end='0x9409110' /><slave name='sysid.control_slave' start='0x9409110' end='0x9409118' /><slave name='jtag_uart.avalon_jtag_slave' start='0x9409118' end='0x9409120' /></address-map>
dataAddrWidth | 28
cpuReset | false
cpuID | 0
clockFrequency | 100000000
breakSlave | cpu.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

CPU_IMPLEMENTATION | "fast"
BIG_ENDIAN | 0
CPU_FREQ | 100000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
INITDA_SUPPORTED |
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x9200020
RESET_ADDR | 0x9200000
BREAK_ADDR | 0x9408820
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 28
DATA_ADDR_WIDTH | 28
NUM_OF_SHADOW_REG_SETS | 0

## onchip_mem

altera_avalon_onchip_memory2 v10.0

cpu | instruction_master | onchip_mem
s1
data_master
s1
pll | c0
clk1

## Parameters

allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
deviceFamily | Cyclone II
dualPort | false
initMemContent | true
initializationFileName | onchip_mem
instanceID | NONE
memorySize | 10240
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
generateLegacySim | false

## Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
INIT_CONTENTS_FILE | "onchip_mem"
NON_DEFAULT_INIT_FILE_ENABLED | 0
GUI_RAM_BLOCK_TYPE | "Automatic"
WRITABLE | 1
DUAL_PORT | 0
SIZE_VALUE | 10240u
SIZE_MULTIPLE | 1
CONTENTS_INFO | ""
RAM_BLOCK_TYPE | "Auto"
INIT_MEM_CONTENT | 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
INSTANCE_ID | "NONE"
READ_DURING_WRITE_MODE | "DONT_CARE"

## pio_led

altera_avalon_pio v10.0

cpu | data_master | pio_led
s1
pll | c0
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 26
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 26
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## timer

altera_avalon_timer v10.0

cpu | data_master | timer
s1
d_irq
irq
pll | c0
clk

## Parameters

alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1.0
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 100000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1.0
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 100000000u
LOAD_VALUE | 99999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## timer_stamp

altera_avalon_timer v10.0

cpu | data_master | timer_stamp
s1
d_irq
irq
pll | c0
clk

## Parameters

alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1.0
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 100000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1.0
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 100000000u
LOAD_VALUE | 99999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## sysid

altera_avalon_sysid v10.0

cpu | data_master | sysid
control_slave
pll | c0
clk

## Parameters

id | 1185241387
timestamp | 1281499285
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ID | 1185241387u
TIMESTAMP | 1281499285u

## ssram_2M

altera_avalon_cy7c1380_ssram v10.0

tristate_bridge_ssram | tristate_master | ssram_2M
s1
pll | c0
clk

## Parameters

readLatency | 2
sharedPorts | ,s1/data
simMakeModel | false
size | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

SRAM_MEMORY_SIZE | 2
SRAM_MEMORY_UNITS | 1048576
SSRAM_DATA_WIDTH | 32
SSRAM_READ_LATENCY | 2

## tristate_bridge_ssram

altera_avalon_tri_state_bridge v10.0

cpu | instruction_master | tristate_bridge_ssram
avalon_slave
data_master
avalon_slave
pll | c0
clk
|  | tristate_master | ssram_2M
|  | s1

## Parameters

registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## jtag_uart

altera_avalon_jtag_uart v10.0

cpu | data_master | jtag_uart
avalon_jtag_slave
d_irq
irq
pll | c0
clk

## Parameters

allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

WRITE_DEPTH | 64
READ_DEPTH | 64
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## clk

clock_source v10.0

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## seg7

SEG7_IF v1.0

cpu | data_master | seg7
s1
pll | c0
s1_clock

## Parameters

SEG7_NUM | 8
ADDR_WIDTH | 3
DEFAULT_ACTIVE | 1
LOW_ACTIVE | 1
AUTO_S1_CLOCK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pio_button

altera_avalon_pio v10.0

cpu | data_master | pio_button
s1
d_irq
irq
pll | c0
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## pio_switch

altera_avalon_pio v10.0

cpu | data_master | pio_switch
s1
pll | c0
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## lcd

altera_avalon_lcd_16207 v10.0

cpu | data_master | lcd
control_slave
pll | c0
clk

## Parameters

deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## i2c_sclk

altera_avalon_pio v10.0

cpu | data_master | i2c_sclk
s1
pll | c0
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## i2c_sdat

altera_avalon_pio v10.0

cpu | data_master | i2c_sdat
s1
pll | c0
clk

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## uart

altera_avalon_uart v10.0

cpu | data_master | uart
s1
d_irq
irq
pll | c0
clk

## Parameters

baud | 115200
baudError | 0.01
clockRate | 100000000
dataBits | 8
fixedBaud | true
parity | NONE
simCharStream |
simInteractiveInputEnable | false
simInteractiveOutputEnable | false
simTrueBaud | false
stopBits | 1
syncRegDepth | 2
useCtsRts | true
useEopRegister | false
useRelativePathForSimFile | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BAUD | 115200
DATA_BITS | 8
FIXED_BAUD | 1
PARITY | 'N'
STOP_BITS | 1
SYNC_REG_DEPTH | 2
USE_CTS_RTS | 1
USE_EOP_REGISTER | 0
SIM_TRUE_BAUD | 0
SIM_CHAR_STREAM | ""
FREQ | 100000000u

## sdram_u1

altera_avalon_new_sdram_controller v10.0

cpu | instruction_master | sdram_u1
s1
data_master
s1
pll | c0
clk

## Parameters

TAC | 5.5
TMRD | 3
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
clockRate | 100000000
columnWidth | 9
dataWidth | 16
generateSimulationModel | true
initNOPDelay | 0.0
initRefreshCommands | 2
masteredTristateBridgeSlave |
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 100.0
refreshPeriod | 15.625
registerDataIn | true
rowWidth | 13
size | 33554432
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

REGISTER_DATA_IN | 1
SIM_MODEL_BASE | 1
SDRAM_DATA_WIDTH | 16
SDRAM_ADDR_WIDTH | 24
SDRAM_ROW_WIDTH | 13
SDRAM_COL_WIDTH | 9
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_NUM_BANKS | 4
REFRESH_PERIOD | 15.625
POWERUP_DELAY | 100.0
CAS_LATENCY | 3
T_RFC | 70.0
T_RP | 20.0
T_MRD | 3
T_RCD | 20.0
T_AC | 5.5
T_WR | 14.0
INIT_REFRESH_COMMANDS | 2
INIT_NOP_DELAY | 0.0
SHARED_DATA | 0
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
IS_INITIALIZED | 1
SDRAM_BANK_WIDTH | 2
CONTENTS_INFO | ""

## sdram_u2

altera_avalon_new_sdram_controller v10.0

cpu | instruction_master | sdram_u2
s1
data_master
s1
pll | c0
clk

## Parameters

TAC | 5.5
TMRD | 3
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
clockRate | 100000000
columnWidth | 9
dataWidth | 16
generateSimulationModel | true
initNOPDelay | 0.0
initRefreshCommands | 2
masteredTristateBridgeSlave |
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 100.0
refreshPeriod | 15.625
registerDataIn | true
rowWidth | 13
size | 33554432
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

REGISTER_DATA_IN | 1
SIM_MODEL_BASE | 1
SDRAM_DATA_WIDTH | 16
SDRAM_ADDR_WIDTH | 24
SDRAM_ROW_WIDTH | 13
SDRAM_COL_WIDTH | 9
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_NUM_BANKS | 4
REFRESH_PERIOD | 15.625
POWERUP_DELAY | 100.0
CAS_LATENCY | 3
T_RFC | 70.0
T_RP | 20.0
T_MRD | 3
T_RCD | 20.0
T_AC | 5.5
T_WR | 14.0
INIT_REFRESH_COMMANDS | 2
INIT_NOP_DELAY | 0.0
SHARED_DATA | 0
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
IS_INITIALIZED | 1
SDRAM_BANK_WIDTH | 2
CONTENTS_INFO | ""

## cfi_flash

altera_avalon_cfi_flash v10.0

tristate_bridge | tristate_master | cfi_flash
s1
pll | c0
clk

## Parameters

actualHoldTime | 0.0
actualSetupTime | 0.0
actualWaitTime | 100.0
addressWidth | 22
clockRate | 100000000
corePreset | CUSTOM
dataWidth | 16
holdTime | 0
setupTime | 0
sharedPorts |
timingUnits | NS
waitTime | 100
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

SETUP_VALUE | 0
WAIT_VALUE | 100
HOLD_VALUE | 0
TIMING_UNITS | "ns"
SIZE | 8388608u

## tristate_bridge

altera_avalon_tri_state_bridge v10.0

cpu | instruction_master | tristate_bridge
avalon_slave
data_master
avalon_slave
pll | c0
clk
|  | tristate_master | cfi_flash
|  | s1

## Parameters

registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## audio

AUDIO_IF v2.0

cpu | data_master | audio
s1
pll | c0
s1_clock

## Parameters

AUTO_S1_CLOCK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pll

altpll v10.0

clk_50 | clk | pll
inclk_interface
cpu | data_master
pll_slave
|  | c0 | cpu
|  | clk
|  | c0 | onchip_mem
|  | clk1
|  | c0 | pio_led
|  | clk
|  | c0 | timer
|  | clk
|  | c0 | timer_stamp
|  | clk
|  | c0 | sysid
|  | clk
|  | c0 | ssram_2M
|  | clk
|  | c0 | tristate_bridge_ssram
|  | clk
|  | c0 | jtag_uart
|  | clk
|  | c0 | seg7
|  | s1_clock
|  | c0 | pio_button
|  | clk
|  | c0 | pio_switch
|  | clk
|  | c0 | lcd
|  | clk
|  | c0 | i2c_sclk
|  | clk
|  | c0 | i2c_sdat
|  | clk
|  | c0 | uart
|  | clk
|  | c0 | sdram_u1
|  | clk
|  | c0 | sdram_u2
|  | clk
|  | c0 | cfi_flash
|  | clk
|  | c0 | tristate_bridge
|  | clk
|  | c0 | audio
|  | s1_clock

## Parameters

HIDDEN_CUSTOM_ELABORATION | altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT | altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY | Cyclone II
WIDTH_CLOCK |
WIDTH_PHASECOUNTERSELECT |
PRIMARY_CLOCK |
INCLK0_INPUT_FREQUENCY | 20000
INCLK1_INPUT_FREQUENCY |
OPERATION_MODE | NORMAL
PLL_TYPE |
QUALIFY_CONF_DONE |
COMPENSATE_CLOCK | CLK0
SCAN_CHAIN |
GATE_LOCK_SIGNAL |
GATE_LOCK_COUNTER |
LOCK_HIGH |
LOCK_LOW |
VALID_LOCK_MULTIPLIER |
INVALID_LOCK_MULTIPLIER |
SWITCH_OVER_ON_LOSSCLK |
SWITCH_OVER_ON_GATED_LOCK |
ENABLE_SWITCH_OVER_COUNTER |
SKIP_VCO |
SWITCH_OVER_COUNTER |
SWITCH_OVER_TYPE |
FEEDBACK_SOURCE |
BANDWIDTH |
BANDWIDTH_TYPE |
SPREAD_FREQUENCY |
DOWN_SPREAD |
SELF_RESET_ON_GATED_LOSS_LOCK |
SELF_RESET_ON_LOSS_LOCK |
CLK0_MULTIPLY_BY | 2
CLK1_MULTIPLY_BY | 2
CLK2_MULTIPLY_BY | 1851
CLK3_MULTIPLY_BY |
CLK4_MULTIPLY_BY |
CLK5_MULTIPLY_BY |
CLK6_MULTIPLY_BY |
CLK7_MULTIPLY_BY |
CLK8_MULTIPLY_BY |
CLK9_MULTIPLY_BY |
EXTCLK0_MULTIPLY_BY |
EXTCLK1_MULTIPLY_BY |
EXTCLK2_MULTIPLY_BY |
EXTCLK3_MULTIPLY_BY |
CLK0_DIVIDE_BY | 1
CLK1_DIVIDE_BY | 1
CLK2_DIVIDE_BY | 5000
CLK3_DIVIDE_BY |
CLK4_DIVIDE_BY |
CLK5_DIVIDE_BY |
CLK6_DIVIDE_BY |
CLK7_DIVIDE_BY |
CLK8_DIVIDE_BY |
CLK9_DIVIDE_BY |
EXTCLK0_DIVIDE_BY |
EXTCLK1_DIVIDE_BY |
EXTCLK2_DIVIDE_BY |
EXTCLK3_DIVIDE_BY |
CLK0_PHASE_SHIFT | 0
CLK1_PHASE_SHIFT | -1806
CLK2_PHASE_SHIFT | 0
CLK3_PHASE_SHIFT |
CLK4_PHASE_SHIFT |
CLK5_PHASE_SHIFT |
CLK6_PHASE_SHIFT |
CLK7_PHASE_SHIFT |
CLK8_PHASE_SHIFT |
CLK9_PHASE_SHIFT |
EXTCLK0_PHASE_SHIFT |
EXTCLK1_PHASE_SHIFT |
EXTCLK2_PHASE_SHIFT |
EXTCLK3_PHASE_SHIFT |
CLK0_DUTY_CYCLE | 50
CLK1_DUTY_CYCLE | 50
CLK2_DUTY_CYCLE | 50
CLK3_DUTY_CYCLE |
CLK4_DUTY_CYCLE |
CLK5_DUTY_CYCLE |
CLK6_DUTY_CYCLE |
CLK7_DUTY_CYCLE |
CLK8_DUTY_CYCLE |
CLK9_DUTY_CYCLE |
EXTCLK0_DUTY_CYCLE |
EXTCLK1_DUTY_CYCLE |
EXTCLK2_DUTY_CYCLE |
EXTCLK3_DUTY_CYCLE |
PORT_clkena0 | PORT_UNUSED
PORT_clkena1 | PORT_UNUSED
PORT_clkena2 | PORT_UNUSED
PORT_clkena3 | PORT_UNUSED
PORT_clkena4 | PORT_UNUSED
PORT_clkena5 | PORT_UNUSED
PORT_extclkena0 |
PORT_extclkena1 |
PORT_extclkena2 |
PORT_extclkena3 |
PORT_extclk0 | PORT_UNUSED
PORT_extclk1 | PORT_UNUSED
PORT_extclk2 | PORT_UNUSED
PORT_extclk3 | PORT_UNUSED
PORT_CLKBAD0 | PORT_UNUSED
PORT_CLKBAD1 | PORT_UNUSED
PORT_clk0 | PORT_USED
PORT_clk1 | PORT_USED
PORT_clk2 | PORT_USED
PORT_clk3 | PORT_UNUSED
PORT_clk4 | PORT_UNUSED
PORT_clk5 | PORT_UNUSED
PORT_clk6 |
PORT_clk7 |
PORT_clk8 |
PORT_clk9 |
PORT_SCANDATA | PORT_UNUSED
PORT_SCANDATAOUT | PORT_UNUSED
PORT_SCANDONE | PORT_UNUSED
PORT_SCLKOUT1 |
PORT_SCLKOUT0 |
PORT_ACTIVECLOCK | PORT_UNUSED
PORT_CLKLOSS | PORT_UNUSED
PORT_INCLK1 | PORT_UNUSED
PORT_INCLK0 | PORT_USED
PORT_FBIN | PORT_UNUSED
PORT_PLLENA | PORT_UNUSED
PORT_CLKSWITCH | PORT_UNUSED
PORT_ARESET | PORT_UNUSED
PORT_PFDENA | PORT_UNUSED
PORT_SCANCLK | PORT_UNUSED
PORT_SCANACLR | PORT_UNUSED
PORT_SCANREAD | PORT_UNUSED
PORT_SCANWRITE | PORT_UNUSED
PORT_ENABLE0 |
PORT_ENABLE1 |
PORT_LOCKED | PORT_UNUSED
PORT_CONFIGUPDATE | PORT_UNUSED
PORT_FBOUT |
PORT_PHASEDONE | PORT_UNUSED
PORT_PHASESTEP | PORT_UNUSED
PORT_PHASEUPDOWN | PORT_UNUSED
PORT_SCANCLKENA | PORT_UNUSED
PORT_PHASECOUNTERSELECT | PORT_UNUSED
PORT_VCOOVERRANGE |
PORT_VCOUNDERRANGE |
DPA_MULTIPLY_BY |
DPA_DIVIDE_BY |
DPA_DIVIDER |
VCO_MULTIPLY_BY |
VCO_DIVIDE_BY |
SCLKOUT0_PHASE_SHIFT |
SCLKOUT1_PHASE_SHIFT |
VCO_FREQUENCY_CONTROL |
VCO_PHASE_SHIFT_STEP |
USING_FBMIMICBIDIR_PORT |
SCAN_CHAIN_MIF_FILE |
AVALON_USE_SEPARATE_SYSCLK | NO
HIDDEN_CONSTANTS | CT#CLK2_DIVIDE_BY 5000 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1806 CT#PORT_ARESET PORT_UNUSED CT#CLK2_MULTIPLY_BY 1851 CT#INTENDED_DEVICE_FAMILY {Cyclone II} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED
HIDDEN_PRIVATES | PT#GLOCKED_FEATURE_ENABLED 1 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 0 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 1 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 0 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_ENA_CHECK 0 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 0 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 18.51000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 -65.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#BANDWIDTH_USE_CUSTOM 0 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 18.510000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone II} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1281497733963098.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS | UP#c2 used UP#c1 used UP#c0 used UP#inclk0 used
HIDDEN_IS_NUMERIC | IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK2_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS | MF#clk 1 MF#inclk 1
HIDDEN_IF_PORTS | IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0}
HIDDEN_IS_FIRST_EDIT | 0
AUTO_INCLK_INTERFACE_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments

(none)

generation took 0.02 seconds | rendering took 0.30 seconds