# TCL File Generated by Component Editor 7.2 on:
# Fri Oct 05 17:46:02 CST 2007
# DO NOT MODIFY

set_source_file "ISP1362_IF.v"
set_module "ISP1362_IF"
set_module_description ""
set_module_property "author" "Richard Chang"
set_module_property "editable" "true"
set_module_property "group" "Terasic Technologies Inc."
set_module_property "instantiateInSystemModule" "true"
set_module_property "version" "1.0"

# Module parameters

# Interface hc_clock
add_interface "hc_clock" "clock" "sink" "asynchronous"
# Ports in interface hc_clock
add_port_to_interface "hc_clock" "avs_hc_clk_iCLK" "clk"
add_port_to_interface "hc_clock" "avs_hc_reset_n_iRST_N" "reset_n"

# Interface dc_clock
add_interface "dc_clock" "clock" "sink" "asynchronous"
# Ports in interface dc_clock
add_port_to_interface "dc_clock" "avs_dc_clk_iCLK" "clk"
add_port_to_interface "dc_clock" "avs_dc_reset_n_iRST_N" "reset_n"

# Interface global_signals_export
add_interface "global_signals_export" "conduit" "start" "asynchronous"
# Ports in interface global_signals_export
add_port_to_interface "global_signals_export" "avs_dc_export_OTG_INT1" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_DATA" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_ADDR" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_RD_N" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_WR_N" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_CS_N" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_RST_N" "export"
add_port_to_interface "global_signals_export" "avs_hc_export_OTG_INT0" "export"

# Interface hc
add_interface "hc" "avalon" "slave" "hc_clock"
set_interface_property "hc" "isNonVolatileStorage" "false"
set_interface_property "hc" "burstOnBurstBoundariesOnly" "false"
set_interface_property "hc" "readLatency" "0"
set_interface_property "hc" "readWaitStates" "50"
set_interface_property "hc" "holdTime" "140"
set_interface_property "hc" "printableDevice" "false"
set_interface_property "hc" "readWaitTime" "50"
set_interface_property "hc" "setupTime" "140"
set_interface_property "hc" "addressAlignment" "NATIVE"
set_interface_property "hc" "writeWaitTime" "50"
set_interface_property "hc" "timingUnits" "Nanoseconds"
set_interface_property "hc" "minimumUninterruptedRunLength" "1"
set_interface_property "hc" "isMemoryDevice" "false"
set_interface_property "hc" "linewrapBursts" "false"
set_interface_property "hc" "writeWaitStates" "50"
set_interface_property "hc" "maximumPendingReadTransactions" "0"
# Ports in interface hc
add_port_to_interface "hc" "avs_hc_writedata_iDATA" "writedata"
add_port_to_interface "hc" "avs_hc_readdata_oDATA" "readdata"
add_port_to_interface "hc" "avs_hc_address_iADDR" "address"
add_port_to_interface "hc" "avs_hc_read_n_iRD_N" "read_n"
add_port_to_interface "hc" "avs_hc_write_n_iWR_N" "write_n"
add_port_to_interface "hc" "avs_hc_chipselect_n_iCS_N" "chipselect_n"

# Interface hc_irq
add_interface "hc_irq" "interrupt" "sender" "hc_clock"
set_interface_property "hc_irq" "associatedAddressablePoint" "hc"
# Ports in interface hc_irq
add_port_to_interface "hc_irq" "avs_hc_irq_n_oINT0_N" "irq_n"

# Interface dc
add_interface "dc" "avalon" "slave" "dc_clock"
set_interface_property "dc" "isNonVolatileStorage" "false"
set_interface_property "dc" "burstOnBurstBoundariesOnly" "false"
set_interface_property "dc" "readLatency" "0"
set_interface_property "dc" "readWaitStates" "150"
set_interface_property "dc" "holdTime" "150"
set_interface_property "dc" "printableDevice" "false"
set_interface_property "dc" "readWaitTime" "150"
set_interface_property "dc" "setupTime" "150"
set_interface_property "dc" "addressAlignment" "NATIVE"
set_interface_property "dc" "writeWaitTime" "150"
set_interface_property "dc" "timingUnits" "Nanoseconds"
set_interface_property "dc" "minimumUninterruptedRunLength" "1"
set_interface_property "dc" "isMemoryDevice" "false"
set_interface_property "dc" "linewrapBursts" "false"
set_interface_property "dc" "writeWaitStates" "150"
set_interface_property "dc" "maximumPendingReadTransactions" "0"
# Ports in interface dc
add_port_to_interface "dc" "avs_dc_writedata_iDATA" "writedata"
add_port_to_interface "dc" "avs_dc_readdata_oDATA" "readdata"
add_port_to_interface "dc" "avs_dc_address_iADDR" "address"
add_port_to_interface "dc" "avs_dc_read_n_iRD_N" "read_n"
add_port_to_interface "dc" "avs_dc_write_n_iWR_N" "write_n"
add_port_to_interface "dc" "avs_dc_chipselect_n_iCS_N" "chipselect_n"

# Interface dc_irq
add_interface "dc_irq" "interrupt" "sender" "dc_clock"
set_interface_property "dc_irq" "associatedAddressablePoint" "dc"
# Ports in interface dc_irq
add_port_to_interface "dc_irq" "avs_dc_irq_n_oINT0_N" "irq_n"
