// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions:	DE2_70 Synthesizer 
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
//   V2.0 :| Perly HU          :| 08/12/2010:| Revision to Quartus II 10.0
						 													
// --------------------------------------------------------------------

module DE2_70_Synthesizer
	(
		////////////////////	Clock Input	 	////////////////////	 
		iCLK_28,							//  28.63636 MHz
		iCLK_50,							//	50 MHz
		iCLK_50_2,						//	50 MHz
		iCLK_50_3,						//	50 MHz
		iCLK_50_4,						//	50 MHz
		iEXT_CLOCK,						//	External Clock
		////////////////////	Push Button		////////////////////
		iKEY,								//	Pushbutton[3:0]
		////////////////////	DPDT Switch		////////////////////
		iSW,								//	Toggle Switch[17:0]
		////////////////////	7-SEG Dispaly	////////////////////
		oHEX0_D,							//	Seven Segment Digit 0
		oHEX0_DP,						//  Seven Segment Digit 0 decimal point
		oHEX1_D,							//	Seven Segment Digit 1
		oHEX1_DP,						//  Seven Segment Digit 1 decimal point
		oHEX2_D,							//	Seven Segment Digit 2
		oHEX2_DP,						//  Seven Segment Digit 2 decimal point
		oHEX3_D,							//	Seven Segment Digit 3
		oHEX3_DP,						//  Seven Segment Digit 3 decimal point
		oHEX4_D,							//	Seven Segment Digit 4
		oHEX4_DP,						//  Seven Segment Digit 4 decimal point
		oHEX5_D,							//	Seven Segment Digit 5
		oHEX5_DP,						//  Seven Segment Digit 5 decimal point
		oHEX6_D,							//	Seven Segment Digit 6
		oHEX6_DP,						//  Seven Segment Digit 6 decimal point
		oHEX7_D,							//	Seven Segment Digit 7
		oHEX7_DP,						//  Seven Segment Digit 7 decimal point
		////////////////////////	LED		////////////////////////
		oLEDG,							//	LED Green[8:0]
		oLEDR,							//	LED Red[17:0]
		////////////////////////	UART	////////////////////////
		oUART_TXD,						//	UART Transmitter
		iUART_RXD,						//	UART Receiver
		oUART_CTS,          			//	UART Clear To Send
		iUART_RTS,          			//	UART Requst To Send
		////////////////////////	IRDA	////////////////////////
		oIRDA_TXD,						//	IRDA Transmitter
		iIRDA_RXD,						//	IRDA Receiver
		/////////////////////	SDRAM Interface		////////////////
		DRAM_DQ,							//	SDRAM Data bus 32 Bits
		oDRAM0_A,						//	SDRAM0 Address bus 13 Bits
		oDRAM1_A,						//	SDRAM1 Address bus 13 Bits
		oDRAM0_LDQM0,					//	SDRAM0 Low-byte Data Mask 
		oDRAM1_LDQM0,					//	SDRAM1 Low-byte Data Mask 
		oDRAM0_UDQM1,					//	SDRAM0 High-byte Data Mask
		oDRAM1_UDQM1,					//	SDRAM1 High-byte Data Mask
		oDRAM0_WE_N,					//	SDRAM0 Write Enable
		oDRAM1_WE_N,					//	SDRAM1 Write Enable
		oDRAM0_CAS_N,					//	SDRAM0 Column Address Strobe
		oDRAM1_CAS_N,					//	SDRAM1 Column Address Strobe
		oDRAM0_RAS_N,					//	SDRAM0 Row Address Strobe
		oDRAM1_RAS_N,					//	SDRAM1 Row Address Strobe
		oDRAM0_CS_N,					//	SDRAM0 Chip Select
		oDRAM1_CS_N,					//	SDRAM1 Chip Select
		oDRAM0_BA,						//	SDRAM0 Bank Address
		oDRAM1_BA,	 					//	SDRAM1 Bank Address
		oDRAM0_CLK,						//	SDRAM0 Clock
		oDRAM1_CLK,						//	SDRAM1 Clock
		oDRAM0_CKE,						//	SDRAM0 Clock Enable
		oDRAM1_CKE,						//	SDRAM1 Clock Enable
		////////////////////	Flash Interface		////////////////
		FLASH_DQ,						//	FLASH Data bus 15 Bits (0 to 14)
		FLASH_DQ15_AM1,				//  FLASH Data bus Bit 15 or Address A-1
		oFLASH_A,						//	FLASH Address bus 26 Bits
		oFLASH_WE_N,					//	FLASH Write Enable
		oFLASH_RST_N,					//	FLASH Reset
		oFLASH_WP_N,					//	FLASH Write Protect /Programming Acceleration 
		iFLASH_RY_N,					//	FLASH Ready/Busy output 
		oFLASH_BYTE_N,					//	FLASH Byte/Word Mode Configuration
		oFLASH_OE_N,					//	FLASH Output Enable
		oFLASH_CE_N,					//	FLASH Chip Enable
		////////////////////	SRAM Interface		////////////////
		SRAM_DQ,							//	SRAM Data Bus 32 Bits
		SRAM_DPA, 						//  SRAM Parity Data Bus
		oSRAM_A,							//	SRAM Address bus 22 Bits
		oSRAM_ADSC_N,       			//	SRAM Controller Address Status 	
		oSRAM_ADSP_N,              //	SRAM Processor Address Status
		oSRAM_ADV_N,               //	SRAM Burst Address Advance
		oSRAM_BE_N,                //	SRAM Byte Write Enable
		oSRAM_CE1_N,        			//	SRAM Chip Enable
		oSRAM_CE2,          			//	SRAM Chip Enable
		oSRAM_CE3_N,        			//	SRAM Chip Enable
		oSRAM_CLK,                 //	SRAM Clock
		oSRAM_GW_N,         			//  SRAM Global Write Enable
		oSRAM_OE_N,         			//	SRAM Output Enable
		oSRAM_WE_N,         			//	SRAM Write Enable
		////////////////////	ISP1362 Interface	////////////////
		OTG_D,							//	ISP1362 Data bus 16 Bits
		oOTG_A,							//	ISP1362 Address 2 Bits
		oOTG_CS_N,						//	ISP1362 Chip Select
		oOTG_OE_N,						//	ISP1362 Read
		oOTG_WE_N,						//	ISP1362 Write
		oOTG_RESET_N,					//	ISP1362 Reset
		OTG_FSPEED,						//	USB Full Speed,	0 = Enable, Z = Disable
		OTG_LSPEED,						//	USB Low Speed, 	0 = Enable, Z = Disable
		iOTG_INT0,						//	ISP1362 Interrupt 0
		iOTG_INT1,						//	ISP1362 Interrupt 1
		iOTG_DREQ0,						//	ISP1362 DMA Request 0
		iOTG_DREQ1,						//	ISP1362 DMA Request 1
		oOTG_DACK0_N,					//	ISP1362 DMA Acknowledge 0
		oOTG_DACK1_N,					//	ISP1362 DMA Acknowledge 1
		////////////////////	LCD Module 16X2		////////////////
		oLCD_ON,							//	LCD Power ON/OFF
		oLCD_BLON,						//	LCD Back Light ON/OFF
		oLCD_RW,							//	LCD Read/Write Select, 0 = Write, 1 = Read
		oLCD_EN,							//	LCD Enable
		oLCD_RS,							//	LCD Command/Data Select, 0 = Command, 1 = Data
		LCD_D,							//	LCD Data bus 8 bits
		////////////////////	SD_Card Interface	////////////////
		SD_DAT,							//	SD Card Data
		SD_DAT3,							//	SD Card Data 3
		SD_CMD,							//	SD Card Command Signal
		oSD_CLK,							//	SD Card Clock
		////////////////////	I2C		////////////////////////////
		I2C_SDAT,						//	I2C Data
		oI2C_SCLK,						//	I2C Clock
		////////////////////	PS2		////////////////////////////
		PS2_KBDAT,						//	PS2 Keyboard Data
		PS2_KBCLK,						//	PS2 Keyboard Clock		
		PS2_MSDAT,						//	PS2 Mouse Data
		PS2_MSCLK,						//	PS2 Mouse Clock
		////////////////////	VGA		////////////////////////////
		oVGA_CLOCK,   					//	VGA Clock
		oVGA_HS,							//	VGA H_SYNC
		oVGA_VS,							//	VGA V_SYNC
		oVGA_BLANK_N,					//	VGA BLANK
		oVGA_SYNC_N,					//	VGA SYNC
		oVGA_R,   						//	VGA Red[9:0]
		oVGA_G,	 						//	VGA Green[9:0]
		oVGA_B,  						//	VGA Blue[9:0]
		////////////	Ethernet Interface	////////////////////////
		ENET_D,							//	DM9000A DATA bus 16Bits
		oENET_CMD,						//	DM9000A Command/Data Select, 0 = Command, 1 = Data
		oENET_CS_N,						//	DM9000A Chip Select
		oENET_IOW_N,					//	DM9000A Write
		oENET_IOR_N,					//	DM9000A Read
		oENET_RESET_N,					//	DM9000A Reset
		iENET_INT,						//	DM9000A Interrupt
		oENET_CLK,						//	DM9000A Clock 25 MHz
		////////////////	Audio CODEC		////////////////////////
		AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
		iAUD_ADCDAT,					//	Audio CODEC ADC Data
		AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
		oAUD_DACDAT,					//	Audio CODEC DAC Data
		AUD_BCLK,						//	Audio CODEC Bit-Stream Clock
		oAUD_XCK,						//	Audio CODEC Chip Clock
		////////////////	TV Decoder		////////////////////////
		iTD1_CLK27,						//	TV Decoder1 Line_Lock Output Clock 
		iTD1_D,    					    //	TV Decoder1 Data bus 8 bits
		iTD1_HS,							//	TV Decoder1 H_SYNC
		iTD1_VS,							//	TV Decoder1 V_SYNC
		oTD1_RESET_N,					//	TV Decoder1 Reset
		iTD2_CLK27,						//	TV Decoder2 Line_Lock Output Clock 		
		iTD2_D,    					    //	TV Decoder2 Data bus 8 bits
		iTD2_HS,							//	TV Decoder2 H_SYNC
		iTD2_VS,							//	TV Decoder2 V_SYNC
		oTD2_RESET_N,					//	TV Decoder2 Reset
		////////////////////	GPIO	////////////////////////////
		GPIO_0,							//	GPIO Connection 0 I/O
		GPIO_CLKIN_N0,     			//	GPIO Connection 0 Clock Input 0
		GPIO_CLKIN_P0,          	//	GPIO Connection 0 Clock Input 1
		GPIO_CLKOUT_N0,     			//	GPIO Connection 0 Clock Output 0
		GPIO_CLKOUT_P0,            //	GPIO Connection 0 Clock Output 1
		GPIO_1,							//	GPIO Connection 1 I/O
		GPIO_CLKIN_N1,             //	GPIO Connection 1 Clock Input 0
		GPIO_CLKIN_P1,             //	GPIO Connection 1 Clock Input 1
		GPIO_CLKOUT_N1,            //	GPIO Connection 1 Clock Output 0
		GPIO_CLKOUT_P1             //	GPIO Connection 1 Clock Output 1
	   
	);

//===========================================================================
// PARAMETER declarations
//===========================================================================


//===========================================================================
// PORT declarations
//===========================================================================
////////////////////////	Clock Input	 	////////////////////////
input				iCLK_28;					//  28.63636 MHz
input				iCLK_50;					//	50 MHz
input				iCLK_50_2;				//	50 MHz
input          iCLK_50_3;				//	50 MHz
input          iCLK_50_4;				//	50 MHz
input          iEXT_CLOCK;				//	External Clock
////////////////////////	Push Button		////////////////////////
input		[3:0]	iKEY;						//	Pushbutton[3:0]
////////////////////////	DPDT Switch		////////////////////////
input		[17:0]iSW;						//	Toggle Switch[17:0]
////////////////////////	7-SEG Dispaly	////////////////////////
output	[6:0]	oHEX0_D;					//	Seven Segment Digit 0
output			oHEX0_DP;				//  Seven Segment Digit 0 decimal point
output	[6:0]	oHEX1_D;					//	Seven Segment Digit 1
output			oHEX1_DP;				//  Seven Segment Digit 1 decimal point
output	[6:0]	oHEX2_D;					//	Seven Segment Digit 2
output			oHEX2_DP;				//  Seven Segment Digit 2 decimal point
output	[6:0]	oHEX3_D;					//	Seven Segment Digit 3
output			oHEX3_DP;				//  Seven Segment Digit 3 decimal point
output	[6:0]	oHEX4_D;					//	Seven Segment Digit 4
output			oHEX4_DP;				//  Seven Segment Digit 4 decimal point
output	[6:0]	oHEX5_D;					//	Seven Segment Digit 5
output			oHEX5_DP;				//  Seven Segment Digit 5 decimal point
output	[6:0]	oHEX6_D;					//	Seven Segment Digit 6
output			oHEX6_DP;				//  Seven Segment Digit 6 decimal point
output	[6:0]	oHEX7_D;					//	Seven Segment Digit 7
output			oHEX7_DP;				//  Seven Segment Digit 7 decimal point
////////////////////////////	LED		////////////////////////////
output	[8:0]	oLEDG;					//	LED Green[8:0]
output	[17:0]oLEDR;					//	LED Red[17:0]
////////////////////////////	UART	////////////////////////////
output			oUART_TXD;				//	UART Transmitter
input				iUART_RXD;				//	UART Receiver
output			oUART_CTS;          	//	UART Clear To Send
input				iUART_RTS;          	//	UART Requst To Send
////////////////////////////	IRDA	////////////////////////////
output			oIRDA_TXD;				//	IRDA Transmitter
input				iIRDA_RXD;				//	IRDA Receiver
///////////////////////		SDRAM Interface	////////////////////////
inout		[31:0]DRAM_DQ;					//	SDRAM Data bus 32 Bits
output	[12:0]oDRAM0_A;				//	SDRAM0 Address bus 13 Bits
output	[12:0]oDRAM1_A;				//	SDRAM1 Address bus 13 Bits
output			oDRAM0_LDQM0;			//	SDRAM0 Low-byte Data Mask 
output			oDRAM1_LDQM0;			//	SDRAM1 Low-byte Data Mask 
output			oDRAM0_UDQM1;			//	SDRAM0 High-byte Data Mask
output			oDRAM1_UDQM1;			//	SDRAM1 High-byte Data Mask
output			oDRAM0_WE_N;			//	SDRAM0 Write Enable
output			oDRAM1_WE_N;			//	SDRAM1 Write Enable
output			oDRAM0_CAS_N;			//	SDRAM0 Column Address Strobe
output			oDRAM1_CAS_N;			//	SDRAM1 Column Address Strobe
output			oDRAM0_RAS_N;			//	SDRAM0 Row Address Strobe
output			oDRAM1_RAS_N;			//	SDRAM1 Row Address Strobe
output			oDRAM0_CS_N;			//	SDRAM0 Chip Select
output			oDRAM1_CS_N;			//	SDRAM1 Chip Select
output	[1:0]	oDRAM0_BA;				//	SDRAM0 Bank Address
output	[1:0]	oDRAM1_BA;		 		//	SDRAM1 Bank Address
output			oDRAM0_CLK;				//	SDRAM0 Clock
output			oDRAM1_CLK;				//	SDRAM1 Clock
output			oDRAM0_CKE;				//	SDRAM0 Clock Enable
output			oDRAM1_CKE;				//	SDRAM1 Clock Enable
////////////////////////	Flash Interface	////////////////////////
inout		[14:0]FLASH_DQ;				//	FLASH Data bus 15 Bits (0 to 14)
inout			FLASH_DQ15_AM1;			//  FLASH Data bus Bit 15 or Address A-1
output	[21:0]oFLASH_A;				//	FLASH Address bus 22 Bits
output			oFLASH_WE_N;			//	FLASH Write Enable
output			oFLASH_RST_N;			//	FLASH Reset
output			oFLASH_WP_N;			//	FLASH Write Protect /Programming Acceleration 
input				iFLASH_RY_N;			//	FLASH Ready/Busy output 
output			oFLASH_BYTE_N;			//	FLASH Byte/Word Mode Configuration
output			oFLASH_OE_N;			//	FLASH Output Enable
output			oFLASH_CE_N;			//	FLASH Chip Enable
////////////////////////	SRAM Interface	////////////////////////
inout		[31:0]SRAM_DQ;					//	SRAM Data Bus 32 Bits
inout		[3:0]	SRAM_DPA; 				//  SRAM Parity Data Bus
output	[18:0]oSRAM_A;					//	SRAM Address bus 21 Bits
output			oSRAM_ADSC_N;       	//	SRAM Controller Address Status 	
output			oSRAM_ADSP_N;        //	SRAM Processor Address Status
output			oSRAM_ADV_N;         //	SRAM Burst Address Advance
output	[3:0]	oSRAM_BE_N;          //	SRAM Byte Write Enable
output			oSRAM_CE1_N;        	//	SRAM Chip Enable
output			oSRAM_CE2;          	//	SRAM Chip Enable
output			oSRAM_CE3_N;        	//	SRAM Chip Enable
output			oSRAM_CLK;           //	SRAM Clock
output			oSRAM_GW_N;         	//  SRAM Global Write Enable
output			oSRAM_OE_N;         	//	SRAM Output Enable
output			oSRAM_WE_N;         	//	SRAM Write Enable
////////////////////	ISP1362 Interface	////////////////////////
inout		[15:0]OTG_D;					//	ISP1362 Data bus 16 Bits
output	[1:0]	oOTG_A;					//	ISP1362 Address 2 Bits
output			oOTG_CS_N;				//	ISP1362 Chip Select
output			oOTG_OE_N;				//	ISP1362 Read
output			oOTG_WE_N;				//	ISP1362 Write
output			oOTG_RESET_N;			//	ISP1362 Reset
inout				OTG_FSPEED;				//	USB Full Speed,	0 = Enable, Z = Disable
inout				OTG_LSPEED;				//	USB Low Speed, 	0 = Enable, Z = Disable
input				iOTG_INT0;				//	ISP1362 Interrupt 0
input				iOTG_INT1;				//	ISP1362 Interrupt 1
input				iOTG_DREQ0;				//	ISP1362 DMA Request 0
input				iOTG_DREQ1;				//	ISP1362 DMA Request 1
output			oOTG_DACK0_N;			//	ISP1362 DMA Acknowledge 0
output			oOTG_DACK1_N;			//	ISP1362 DMA Acknowledge 1
////////////////////	LCD Module 16X2	////////////////////////////
inout		[7:0]	LCD_D;					//	LCD Data bus 8 bits
output			oLCD_ON;					//	LCD Power ON/OFF
output			oLCD_BLON;				//	LCD Back Light ON/OFF
output			oLCD_RW;					//	LCD Read/Write Select, 0 = Write, 1 = Read
output			oLCD_EN;					//	LCD Enable
output			oLCD_RS;					//	LCD Command/Data Select, 0 = Command, 1 = Data
////////////////////	SD Card Interface	////////////////////////
inout				SD_DAT;					//	SD Card Data
inout				SD_DAT3;					//	SD Card Data 3
inout				SD_CMD;					//	SD Card Command Signal
output			oSD_CLK;					//	SD Card Clock
////////////////////////	I2C		////////////////////////////////
inout				I2C_SDAT;				//	I2C Data
output			oI2C_SCLK;				//	I2C Clock
////////////////////////	PS2		////////////////////////////////
inout		 		PS2_KBDAT;				//	PS2 Keyboard Data
inout				PS2_KBCLK;				//	PS2 Keyboard Clock
inout		 		PS2_MSDAT;				//	PS2 Mouse Data
inout				PS2_MSCLK;				//	PS2 Mouse Clock
////////////////////////	VGA			////////////////////////////
output			oVGA_CLOCK;   			//	VGA Clock
output			oVGA_HS;					//	VGA H_SYNC
output			oVGA_VS;					//	VGA V_SYNC
output			oVGA_BLANK_N;			//	VGA BLANK
output			oVGA_SYNC_N;			//	VGA SYNC
output	[9:0]	oVGA_R;   				//	VGA Red[9:0]
output	[9:0]	oVGA_G;	 				//	VGA Green[9:0]
output	[9:0]	oVGA_B;   				//	VGA Blue[9:0]
////////////////	Ethernet Interface	////////////////////////////
inout		[15:0]ENET_D;					//	DM9000A DATA bus 16Bits
output			oENET_CMD;				//	DM9000A Command/Data Select, 0 = Command, 1 = Data
output			oENET_CS_N;				//	DM9000A Chip Select
output			oENET_IOW_N;			//	DM9000A Write
output			oENET_IOR_N;			//	DM9000A Read
output			oENET_RESET_N;			//	DM9000A Reset
input				iENET_INT;				//	DM9000A Interrupt
output			oENET_CLK;				//	DM9000A Clock 25 MHz
////////////////////	Audio CODEC		////////////////////////////
inout				AUD_ADCLRCK;			//	Audio CODEC ADC LR Clock
input				iAUD_ADCDAT;			//	Audio CODEC ADC Data
inout				AUD_DACLRCK;			//	Audio CODEC DAC LR Clock
output			oAUD_DACDAT;			//	Audio CODEC DAC Data
inout				AUD_BCLK;				//	Audio CODEC Bit-Stream Clock
output			oAUD_XCK;				//	Audio CODEC Chip Clock
////////////////////	TV Devoder		////////////////////////////
input				iTD1_CLK27;				//	TV Decoder1 Line_Lock Output Clock 
input		[7:0]	iTD1_D;    				//	TV Decoder1 Data bus 8 bits
input				iTD1_HS;					//	TV Decoder1 H_SYNC
input				iTD1_VS;					//	TV Decoder1 V_SYNC
output			oTD1_RESET_N;			//	TV Decoder1 Reset
input				iTD2_CLK27;				//	TV Decoder2 Line_Lock Output Clock 		
input		[7:0]	iTD2_D;    				//	TV Decoder2 Data bus 8 bits
input				iTD2_HS;					//	TV Decoder2 H_SYNC
input				iTD2_VS;					//	TV Decoder2 V_SYNC
output			oTD2_RESET_N;			//	TV Decoder2 Reset

////////////////////////	GPIO	////////////////////////////////
inout		[31:0]GPIO_0;					//	GPIO Connection 0 I/O
input			GPIO_CLKIN_N0;     		//	GPIO Connection 0 Clock Input 0
input			GPIO_CLKIN_P0;          //	GPIO Connection 0 Clock Input 1
inout			GPIO_CLKOUT_N0;     		//	GPIO Connection 0 Clock Output 0
inout			GPIO_CLKOUT_P0;         //	GPIO Connection 0 Clock Output 1
inout	[31:0]GPIO_1;						//	GPIO Connection 1 I/O
input			GPIO_CLKIN_N1;          //	GPIO Connection 1 Clock Input 0
input			GPIO_CLKIN_P1;          //	GPIO Connection 1 Clock Input 1
inout			GPIO_CLKOUT_N1;         //	GPIO Connection 1 Clock Output 0
inout			GPIO_CLKOUT_P1;         //	GPIO Connection 1 Clock Output 1
///////////////////////////////////////////////////////////////////
//=============================================================================
// REG/WIRE declarations
//=============================================================================

wire				I2C_END;
wire				AUD_CTRL_CLK;
reg		[31:0]GA_CLK_o;
wire   			keyboard_sysclk;
wire   			demo_clock ; 
wire		[7:0]	demo_code1;
wire 		[7:0]	scan_code;
wire 				get_gate;
wire 				key1_on;
wire 				key2_on;
wire 		[7:0]	key1_code;
wire 		[7:0]	key2_code;
wire   			VGA_R1,VGA_G1,VGA_B1;
wire   			VGA_R2,VGA_G2,VGA_B2;

reg		[18:0]VGA_CLK_o;

//=============================================================================
// Structural coding
//=============================================================================
	
assign PS2_MSDAT = 1'b1;	
assign PS2_MSCLK = 1'b1;
	
//  TV DECODER ENABLE 
	
	assign  oTD1_RESET_N    =   1;
	assign	oTD2_RESET_N    =   1;
	
//  7-SEG 
			
	SEG7_LUT_8 			u0	(	oHEX0_D,oHEX1_D,oHEX2_D,oHEX3_D,oHEX4_D,oHEX5_D,oHEX6_D,oHEX7_D,31'h00001112 );

//  I2C

	I2C_AV_Config 		u7	(	//	Host Side
								.iCLK		( iCLK_50 ),
								.iRST_N		( iKEY[0] ),
								.o_I2C_END	( I2C_END ),
								//	I2C Side
								.I2C_SCLK	( oI2C_SCLK ),
								.I2C_SDAT	( I2C_SDAT )	
		
								);


//	AUDIO SOUND

	assign	AUD_ADCLRCK	=	AUD_DACLRCK;
	assign	oAUD_XCK	=	AUD_CTRL_CLK;			

//  AUDIO PLL

	VGA_Audio_PLL 		u1	(	
								.areset ( ~I2C_END ),
								
								.inclk0 ( iTD1_CLK27 ),

								.c1		( AUD_CTRL_CLK )	
							
								);


// Music Synthesizer Block //

// TIME & CLOCK Generater //

	assign keyboard_sysclk = VGA_CLK_o[12];
	assign demo_clock      = VGA_CLK_o[18]; 
	assign oVGA_CLOCK      = VGA_CLK_o[0];

	always @( posedge iCLK_50 )
		begin
			VGA_CLK_o <= VGA_CLK_o + 1;
		end

// DEMO SOUND //

// DEMO Sound (CH1) //



	demo_sound1	dd1(
		.clock   ( demo_clock ),
		.key_code( demo_code1 ),
		.k_tr    ( iKEY[1] & iKEY[0] )
	);

// DEMO Sound (CH2) //

	wire [7:0]demo_code2;

	demo_sound2	dd2(
		.clock   ( demo_clock ),
		.key_code( demo_code2 ),
		.k_tr    ( iKEY[1] & iKEY[0] )
	);

// KeyBoard Scan //

	PS2_KEYBOARD keyboard(
	
		.ps2_dat  ( PS2_KBDAT ),		//ps2bus data  		
		.ps2_clk  ( PS2_KBCLK ),		//ps2bus clk      	
		.sys_clk  ( keyboard_sysclk ),  //system clock		
		.reset    ( iKEY[3] ), 		    //system reset		
    	.reset1   ( iKEY[2] ),			//keyboard reset	
    	.scandata ( scan_code ),		//scan code    		
    	.key1_on  ( key1_on ),			//key1 triger
    	.key2_on  ( key2_on ),			//key2 triger
    	.key1_code( key1_code ),		//key1 code
    	.key2_code( key2_code ) 		//key2 code
	);
	
////////////Sound Select/////////////	

	wire [15:0]sound1;

	wire [15:0]sound2;

	wire [15:0]sound3;

	wire [15:0]sound4;

	wire sound_off1;

	wire sound_off2;

	wire sound_off3;

	wire sound_off4;

	wire [7:0]sound_code1 = ( !iSW[9] )? demo_code1 : key1_code ; //SW[9]=0 is DEMO SOUND,otherwise key

	wire [7:0]sound_code2 = ( !iSW[9] )? demo_code2 : key2_code ; //SW[9]=0 is DEMO SOUND,otherwise key

	wire [7:0]sound_code3 = 8'hf0;

	wire [7:0]sound_code4 = 8'hf0;

// Staff Display & Sound Output //
	
	assign oVGA_R=( VGA_R1 )? 10'h3f0 : 0 ;
	
	assign oVGA_G=( VGA_G1 )? 10'h3f0 : 0 ;
	
	assign oVGA_B=( VGA_B1 )? 10'h3f0 : 0 ;

	staff st1(
		
		// VGA output //
		
		.VGA_CLK   		( oVGA_CLOCK ),   
		.vga_h_sync		( oVGA_HS ), 
		.vga_v_sync		( oVGA_VS ), 
		.vga_sync  		( oVGA_SYNC_N ),	
	    .inDisplayArea	( oVGA_BLANK_N ),
		.vga_R			( VGA_R1 ), 
		.vga_G			( VGA_G1 ), 
		.vga_B			( VGA_B1 ),
		
		// Key code-in //
		
		.scan_code1( sound_code1 ),
		.scan_code2( sound_code2 ),
		.scan_code3( sound_code3 ), // OFF
		.scan_code4( sound_code4 ), // OFF
		
		//Sound Output to Audio Generater//
		
		.sound1( sound1 ),
		.sound2( sound2 ),
		.sound3( sound3 ), // OFF
		.sound4( sound4 ), // OFF
		
		.sound_off1( sound_off1 ),
		.sound_off2( sound_off2 ),
		.sound_off3( sound_off3 ), //OFF
		.sound_off4( sound_off4 )	 //OFF
		
	);

///////LED Display////////

	assign oLEDR[9:6] = { sound_off4,sound_off3,sound_off2,sound_off1 };

	assign oLEDG[7:0] = scan_code;
						
// 2CH Audio Sound output -- Audio Generater //

	adio_codec ad1	(	
	        
		// AUDIO CODEC //
		
		.oAUD_BCK ( AUD_BCLK ),
		.oAUD_DATA( oAUD_DACDAT ),
		.oAUD_LRCK( AUD_DACLRCK ),																
		.iCLK_18_4( AUD_CTRL_CLK ),
		
		// KEY //
		
		.iRST_N( iKEY[0] ),							
		.iSrc_Select( 2'b00 ),

		// Sound Control //

		.key1_on( ~iSW[1] & sound_off1 ),//CH1 ON / OFF		
		.key2_on( ~iSW[2] & sound_off2 ),//CH2 ON / OFF
		.key3_on( 1'b0 ), // OFF
    	.key4_on( 1'b0 ), // OFF							
		.sound1( sound1 ),// CH1 Freq
		.sound2( sound2 ),// CH2 Freq
		.sound3( sound3 ),// OFF,CH3 Freq
		.sound4( sound4 ),// OFF,CH4 Freq							
		.instru( iSW[0] )  // Instruction Select
	);


//	LCD 

	assign	oLCD_ON		=	1'b1;
	
	assign	oLCD_BLON	=	1'b1;	
	
	LCD_TEST 			u5	(	
	
							//	Host Side
							
							.iCLK  	( iCLK_50 ),
							.iRST_N	( iKEY[0] & I2C_END ),
							
							//	LCD Side
							
							.LCD_DATA( LCD_D ),
							.LCD_RW  ( oLCD_RW ),
							.LCD_EN	 ( oLCD_EN ),
							.LCD_RS  ( oLCD_RS )	
							
							);



endmodule

