module decode_656 (
    iTD_VS,
	iTD_D,
	iCLOCK,
	oSTART,
	oField,
	oVS,
	oSTATUS,
	oSAVE
);
input iTD_VS;
input [7:0]	iTD_D;
input 		iCLOCK;
output 		oSTART;
output 		oField;
output 		oVS;
output [7:0]oSTATUS;
output      oSAVE;

	
reg 		oSTART;
reg  		oField;
reg  	 	oVS;
wire         oSAVE	;
reg [7:0] 	oSTATUS;

reg [7:0]   R3,R2,R1;

wire Y_check =( (R3==8'hff) && (R2==8'h00) && (R1==8'h00) )? 1 : 0;

always @(posedge iCLOCK) begin

	{ R3,R2,R1 }= {R2, R1, iTD_D };
	
    if ( Y_check ) begin
		
			{ oField ,oVS ,oSTART }= iTD_D[6:4];
			//oSAVE = ( iTD_D[6] ) ;
			oSTATUS[7:0]=iTD_D[7:0];
			
	end	
end
	
reg fd;	
always @(negedge oField  or  posedge oVS ) //pos
if (!oField)
  fd = 0;
  else
  fd = 1;

assign oSAVE = fd & oVS;

	
endmodule
