Generation Report - IP Compiler for PCI Express v15.0

Entity Name	altpcie_hip_pipen1b
Ordering Code	IP-PCIE/4
Variation Name	top
Variation HDL	Verilog HDL
Output Directory	/data/pmolson/source/depot/ip/pci_express/dev_kits/ip_for_pcie_hw_devkit/hip_s4gx_gen2_x4_64

File Summary

The MegaWizard interface is creating the following files in the output directory:

File	Description
top.v	This Verilog HDL file instantiates the parameterized MegaCore for PCI Express function and the logic required to support the specific PHY selected. It is used for both simulation and compilation in the Quartus II software.
top_core.v	This Verilog HDL file configures the MegaCore for PCI Express function with the parameters specified. It is used for compilation in the Quartus II software.
top_core.vo	This Verilog HDL file is the parameterized IP Functional Simulation model of the MegaCore function. It is used for simulation.
top_examples	This directory contains example design and testbench files.
top_examples \| chaining_dma	This directory contains the chaining DMA example design and testbench.
top_examples \| chaining_dma \| altpcie_dma_descriptor.v	This Verilog HDL file contains the altpcie_dma_descriptor module that retrieves DMA read or write descriptors from the root port memory and stores them in a descriptor FIFO. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| altpcie_dma_dt.v	This Verilog HDL file contains the altpcie_dma_dt module that arbitrates between PCI Express packets issued by the altpcie_dma_prg_reg, altpcie_read_dma_requester, altpcie_write_dma_requester and altpcie_dma_descriptor modules. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| altpcie_dma_prg_reg.v	This Verilog HDL file implements the descriptor header table registers. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| altpcie_rc_slave.v	This Verilog HDL file contains the altpcie_rc_slave module that is used by the host software application to retrieve the DMA Performance counter values and directly access the Endpoint memory. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| altpcie_read_dma_requester.v	This Verilog HDL file contains the altpcie_read_dma_requester module that manages DMA read data transfer from the Root Complex memory to the Endpoint memory. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| altpcie_write_dma_requester.v	This Verilog HDL file contains the altpcie_write_dma_requester module that manages DMA write data transfer from the Endpoint memory to the Root Complex memory. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| altpcierd_example_app_chaining.v	This Verilog HDL file contains the altpcierd_example_app_chaining module that is the top level application layer of the chaining DMA example design. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| init_ram.hex	This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in simulation.
top_examples \| chaining_dma \| init_ram.mif	This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in compilation in the Quartus II software.
top_examples \| chaining_dma \| testbench	This directory contains files required for simulation of the chaining DMA example design and testbench.
top_examples \| chaining_dma \| testbench \| altpcie_dma_dt_cst_sim.v	This Verilog HDL file contains constants used in the testbench for the chaining DMA example design. It is used in simulation.
top_examples \| chaining_dma \| testbench \| altpcietb_bfm_driver_chaining.v	This Verilog HDL file contains the altpcietb_bfm_driver_chaining module that drives the testing of the chaining DMA example design. This file is used in simulation.
top_examples \| chaining_dma \| testbench \| init_ram.hex	This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in simulation.
top_examples \| chaining_dma \| testbench \| init_ram.mif	This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in compilation in the Quartus II software.
top_examples \| chaining_dma \| testbench \| runtb.bat	This Windows batch file launches the simulation of the chaining DMA example design and testbench.
top_examples \| chaining_dma \| testbench \| runtb.do	This Modelsim simulator TCL script file launches the simulation of the chaining DMA example design and testbench.
top_examples \| chaining_dma \| testbench \| runtb.sh	This shell script file launches the simulation of the chaining DMA example design and testbench.
top_examples \| chaining_dma \| testbench \| sim_filelist	This file is used for simulation of the chaining DMA example design. It contains the list of all the files necessary for compilation in the simulator.
top_examples \| chaining_dma \| testbench \| top_chaining_testbench.v	This Verilog HDL file implements the top level of the testbench for the chaining DMA example design.
top_examples \| chaining_dma \| top_example_chaining_pipen1b.v	This Verilog HDL file instantiates the chaining DMA example application layer and the variation. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| top_plus.v	This Verilog HDL file instantiates the variation and the reset circuit. The ALTGX_RECONFIG megafunction is also added to this module when the device family requires transceiver offset cancellation. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| top_rs_hip.v	This Verilog file implements the HIP reset circuit. It is used for simulation and compilation in the Quartus II software.
top_examples \| chaining_dma \| top_example_chaining_top.qpf	This is the Quartus II project file used for compiling the chaining DMA example design.
top_examples \| chaining_dma \| top_example_chaining_top.qsf	This is the Quartus II settings file used for compiling the chaining DMA example design.
top.sdc	This is the Quartus II TimeQuest Timing Analyzer constraint file.
top_examples \| chaining_dma \| top_example_chaining_top.tcl	This is a Quartus II TCL script used for applying Classic Timing Analyzer timing constraints to the chaining DMA example design.
top_examples \| chaining_dma \| top_example_chaining_top.v	This Verilog HDL file instantiates the entire chaining DMA example design. It is used for compilation in the Quartus II software.
top_examples \| common	This directory contains files required for simulation..
top_examples \| common \| testbench	This directory contains files required for simulation. These files implement the common BFM and Testbench routines that are described in Chapter 5 of the User Guide.
top_examples \| incremental_compile_module	This directory contains files for the incremental compile module. These files are required for simulation and compilation of the simple DMA and chaining DMA example designs
top_examples \| incremental_compile_module \| altpcierd_icm_defines.v	This Verilog HDL file contains global defines used in the incremental_compile_module files and in the
top_examples \| incremental_compile_module \| altpcierd_icm_fifo.v	This Verilog HDL file contains the altpcierd_icm_fifo module. This is an altera FIFO which is used in the incremental compile module. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_fifo_lkahd.v	This Verilog HDL file contains the altpcierd_icm_fifo_lkahd module that provides a look-ahead FIFO which is used in the incremental compile module. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_msibridge.v	This Verilog HDL file contains the altpcierd_icm_msibridge module that implements bridging of the application's msi streaming interface to the core's msi interface . This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_npbypassctl.v	This Verilog HDL file contains the altpcierd_icm_npbypassctl module that implements the controls for bypassing of Non-Posted requests. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_rx.v	This Verilog HDL file contains the altpcierd_icm_rx module that instantiates an interface FIFO and the altpcierd_icm_rxbridge module. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_rxbridge.v	This Verilog HDL file contains the altpcierd_icm_rxbridge module that implements bridging of the application's rx streaming interface to the core's rx interface. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_sideband.v	This Verilog HDL file contains the altpcierd_icm_sideband module that contains boundary registers for the core's sideband signals. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_top.v	This Verilog HDL file contains the altpcierd_icm_top module. This is the top level module for the incremental compile module. It contains the altpcierd_icm_rx, altpcierd_tx, altpcierd_sideband modules. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_tx.v	This Verilog HDL file contains the altpcierd_icm_tx module that instantiates an interface FIFO, the altpcierd_msi_bridge and altpcierd_icm_txbridge_withbypass modules. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_tx_pktordering.v	This Verilog HDL file contains the altpcierd_icm_tx_pktordering module that implements packet reordering for bypassing of non-posted requests (npbypass). It contains the npbypass Fifos and the altpcierd_npbypassctl module. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_txbridge.v	This Verilog HDL file contains the altpcierd_icm_txbridge module that implements bridging of the application's tx streaming interface to the core's tx interface. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| altpcierd_icm_txbridge_withbypass.v	This Verilog HDL file contains the altpcierd_icm_txbridge_withbypass module which instantiates the altpcierd_icm_tx_pktordering and altpcierd_icm_txbridge modules. This file is used for simulation and compilation in the Quartus II software.
top_examples \| incremental_compile_module \| top_icm.v	This Verilog HDL file contains the VAR_icm module that instantiates the altpcierd_icm_top and the VAR modules. This file is used for simulation and compilation in the Quartus II software.
top_serdes.v	Variation file from the ALTGXB Megafunction.This file contains the on-chip transceiver settings for PCI Express.
top.ppx	This XML file is a Pin Planner support file that Pin Planner automatically uses. This file must remain in the same directory as the top.ppf file.
top.ppf	This XML file describes the MegaCore pin attributes to the Quartus II Pin Planner. MegaCore pin attributes include pin direction, location, I/O standard assignments, and drive strength. If you launch the MegaWizard outside of the Pin Planner application, you must explicitly load this file to use Pin Planner.
top_bb.v	Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
top.bsf	Quartus^® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.
top.qip	Contains Quartus II project information for your MegaCore function variation.
top.html	The MegaCore function report file.

MegaCore Function Parameters

Name	Value
p_pcie_phy	Stratix IV GX
p_pcie_port_type	Native Endpoint
p_pcie_tag_supported	32
p_pcie_msi_message_requested	4
p_pcie_low_priority_virtual_channels	0
p_pcie_retry_fifo_depth	64
p_pcie_nfts_common_clock	255
p_pcie_nfts_separate_clock	255
p_pcie_exp_rom_bar_used	0
p_pcie_link_common_clock	1
p_pcie_advanced_error_reporting	0
p_pcie_ecrc_check	0
p_pcie_ecrc_generation	0
p_pcie_power_indicator	0
p_pcie_attention_indicator	0
p_pcie_attention_button	0
p_pcie_msi_message_64bits_address_capable	1
p_pcie_auto_configure_retry_buffer	1
p_pcie_implement_data_register	0
p_pcie_device_init_required	0
p_pcie_enable_L1_aspm	0
p_pcie_rate_match_fifo	1
p_pcie_enable_fast_recovery	1
SOPCSystemName	N/A
actualBAR0AvalonAddress	0
actualBAR0Size	0
actualBAR1AvalonAddress	0
actualBAR1Size	0
actualBAR2AvalonAddress	0
actualBAR2Size	0
actualBAR3AvalonAddress	0
actualBAR3Size	0
actualBAR4AvalonAddress	0
actualBAR4Size	0
actualBAR5AvalonAddress	0
actualBAR5Size	0
allowedDeviceFamilies	[Stratix III, Stratix II, HardCopy II, Stratix II GX, Stratix, Stratix GX, Cyclone III LS, Cyclone IV E, Cyclone IV GX, Cyclone III, Cyclone II, Cyclone, Max II, APEX 20KE, APEX 20KC, APEX II, ACEX 1K, FLEX 10KE, HardCopy Stratix, Arria GX, Stratix IV, Stratix V, Arria II GX, HardCopy III, HardCopy IV, Unknown, None]
clockSource	N/A
contextState	NativeContext
deviceFamily	Stratix IV
ordering_code	IP-PCIE/4
p_avalon_hardwired_address_map	true
p_avalon_hw_pci_address_00	0x0000000000000000
p_avalon_hw_pci_address_00_type	Memory32Bit
p_avalon_hw_pci_address_01	0x0000000000000000
p_avalon_hw_pci_address_01_type	Memory32Bit
p_avalon_hw_pci_address_02	0x0000000000000000
p_avalon_hw_pci_address_02_type	Memory32Bit
p_avalon_hw_pci_address_03	0x0000000000000000
p_avalon_hw_pci_address_03_type	Memory32Bit
p_avalon_hw_pci_address_04	0x0000000000000000
p_avalon_hw_pci_address_04_type	Memory32Bit
p_avalon_hw_pci_address_05	0x0000000000000000
p_avalon_hw_pci_address_05_type	Memory32Bit
p_avalon_hw_pci_address_06	0x0000000000000000
p_avalon_hw_pci_address_06_type	Memory32Bit
p_avalon_hw_pci_address_07	0x0000000000000000
p_avalon_hw_pci_address_07_type	Memory32Bit
p_avalon_hw_pci_address_08	0x0000000000000000
p_avalon_hw_pci_address_08_type	Memory32Bit
p_avalon_hw_pci_address_09	0x0000000000000000
p_avalon_hw_pci_address_09_type	Memory32Bit
p_avalon_hw_pci_address_10	0x0000000000000000
p_avalon_hw_pci_address_10_type	Memory32Bit
p_avalon_hw_pci_address_11	0x0000000000000000
p_avalon_hw_pci_address_11_type	Memory32Bit
p_avalon_hw_pci_address_12	0x0000000000000000
p_avalon_hw_pci_address_12_type	Memory32Bit
p_avalon_hw_pci_address_13	0x0000000000000000
p_avalon_hw_pci_address_13_type	Memory32Bit
p_avalon_hw_pci_address_14	0x0000000000000000
p_avalon_hw_pci_address_14_type	Memory32Bit
p_avalon_hw_pci_address_15	0x0000000000000000
p_avalon_hw_pci_address_15_type	Memory32Bit
p_avalon_pane_count	1
p_avalon_pane_size	20
p_enable_pcie_hip_dprio	Disable
p_pci_64bit_bar	false
p_pci_64bit_bus	true
p_pci_66mhz	true
p_pci_allow_param_readback	false
p_pci_altera_arbiter	false
p_pci_arbited_devices	2
p_pci_arbiter	false
p_pci_bar_0_auto_avalon_address	false
p_pci_bar_0_auto_sized	false
p_pci_bar_0_avalon_address	0
p_pci_bar_0_hardwired	false
p_pci_bar_0_pci_address	0
p_pci_bar_0_prefetchable	false
p_pci_bar_1_auto_avalon_address	false
p_pci_bar_1_auto_sized	false
p_pci_bar_1_avalon_address	0
p_pci_bar_1_hardwired	false
p_pci_bar_1_pci_address	0
p_pci_bar_1_prefetchable	false
p_pci_bar_2_auto_avalon_address	false
p_pci_bar_2_auto_sized	false
p_pci_bar_2_avalon_address	0
p_pci_bar_2_hardwired	false
p_pci_bar_2_pci_address	0
p_pci_bar_2_prefetchable	false
p_pci_bar_3_auto_avalon_address	false
p_pci_bar_3_auto_sized	false
p_pci_bar_3_avalon_address	0
p_pci_bar_3_hardwired	false
p_pci_bar_3_pci_address	0
p_pci_bar_3_prefetchable	true
p_pci_bar_4_auto_avalon_address	false
p_pci_bar_4_auto_sized	false
p_pci_bar_4_avalon_address	0
p_pci_bar_4_hardwired	false
p_pci_bar_4_pci_address	0
p_pci_bar_4_prefetchable	true
p_pci_bar_5_auto_avalon_address	false
p_pci_bar_5_auto_sized	false
p_pci_bar_5_avalon_address	0
p_pci_bar_5_hardwired	false
p_pci_bar_5_pci_address	0
p_pci_bar_5_prefetchable	true
p_pci_bus_access_address_width	18
p_pci_global_reset	false
p_pci_host_bridge	false
p_pci_impl_cra_av_slave_port	true
p_pci_master	true
p_pci_master_bursts	true
p_pci_master_concurrent_reads	false
p_pci_master_data_width	64
p_pci_maximum_burst_size	128
p_pci_maximum_burst_size_a2p	128
p_pci_maximum_pending_read_transactions_a2p	8
p_pci_non_pref_av_master_port	true
p_pci_not_target_only_port	false
p_pci_pref_av_master_port	true
p_pci_reqn_gntn_pins	true
p_pci_single_clock	false
p_pci_target_bursts	true
p_pci_target_concurrent_reads	false
p_pci_user_specified_bars	false
p_pcie_L1_exit_latency_common_clock	>64 us
p_pcie_L1_exit_latency_separate_clock	>64 us
p_pcie_advanced_error_int_num	0x00000000
p_pcie_alt2gxb	0
p_pcie_app_signal_interface	AvalonST
p_pcie_bar_size_bar_0	256 MBytes - 28 bits
p_pcie_bar_size_bar_1	256 KBytes - 18 bits
p_pcie_bar_size_bar_2	256 KBytes - 18 bits
p_pcie_bar_size_bar_3	N/A
p_pcie_bar_size_bar_4	N/A
p_pcie_bar_size_bar_5	N/A
p_pcie_bar_type_bar_0	32-bit Non-Prefetchable Memory
p_pcie_bar_type_bar_1	32-bit Non-Prefetchable Memory
p_pcie_bar_type_bar_2	32-bit Non-Prefetchable Memory
p_pcie_bar_type_bar_3	Disable this and all higher BARs
p_pcie_bar_type_bar_4	Disable this and all higher BARs
p_pcie_bar_type_bar_5	Disable this and all higher BARs
p_pcie_bar_used_bar_0	1
p_pcie_bar_used_bar_1	1
p_pcie_bar_used_bar_2	1
p_pcie_bar_used_bar_3	0
p_pcie_bar_used_bar_4	0
p_pcie_bar_used_bar_5	0
p_pcie_channel_number	0
p_pcie_chk_io	0
p_pcie_class_code	0xFF0000
p_pcie_completion_data_credit_vc0	448
p_pcie_completion_data_credit_vc1	0
p_pcie_completion_data_credit_vc2	0
p_pcie_completion_data_credit_vc3	0
p_pcie_completion_data_used_space_vc0	7168
p_pcie_completion_data_used_space_vc1	0
p_pcie_completion_data_used_space_vc2	0
p_pcie_completion_data_used_space_vc3	0
p_pcie_completion_header_credit_vc0	112
p_pcie_completion_header_credit_vc1	0
p_pcie_completion_header_credit_vc2	0
p_pcie_completion_header_credit_vc3	0
p_pcie_completion_header_used_space_vc0	1792
p_pcie_completion_header_used_space_vc1	0
p_pcie_completion_header_used_space_vc2	0
p_pcie_completion_header_used_space_vc3	0
p_pcie_completion_timeout	ABCD
p_pcie_custom_phy_x8	0
p_pcie_custom_rx_buffer_xml	0
p_pcie_device_id	0xE001
p_pcie_dll_active_report_support	0
p_pcie_eie_b4_nfts_count	4
p_pcie_enable_completion_timeout_disable	1
p_pcie_enable_function_msix_support	0
p_pcie_enable_hip	1
p_pcie_enable_root_port_endpoint_mode	0
p_pcie_enable_simple_dma	0
p_pcie_enable_slot_capability	0
p_pcie_enable_tl_bypass_mode	0
p_pcie_endpoint_L0s_acceptable_latency	<64 ns
p_pcie_endpoint_L1_acceptable_latency	<1 us
p_pcie_exp_rom_bar_size	N/A
p_pcie_gen2_nfts_diff_clock	255
p_pcie_gen2_nfts_same_clock	255
p_pcie_initiator_performance_preset	Maximum
p_pcie_internal_clock	125 MHz
p_pcie_io_base_and_limit_register	IODisable
p_pcie_lanerev	0
p_pcie_link_port_number	0x01
p_pcie_max_payload_size	256 Bytes
p_pcie_mem_base_and_limit_register	MemDisable
p_pcie_msix_pba_bir	0
p_pcie_msix_pba_offset	0
p_pcie_msix_table_bir	0
p_pcie_msix_table_offset	0
p_pcie_msix_table_size	0
p_pcie_nonposted_data_credit_vc0	0
p_pcie_nonposted_data_credit_vc1	0
p_pcie_nonposted_data_credit_vc2	0
p_pcie_nonposted_data_credit_vc3	0
p_pcie_nonposted_data_used_space_vc0	0
p_pcie_nonposted_data_used_space_vc1	0
p_pcie_nonposted_data_used_space_vc2	0
p_pcie_nonposted_data_used_space_vc3	0
p_pcie_nonposted_header_credit_vc0	54
p_pcie_nonposted_header_credit_vc1	0
p_pcie_nonposted_header_credit_vc2	0
p_pcie_nonposted_header_credit_vc3	0
p_pcie_nonposted_header_used_space_vc0	864
p_pcie_nonposted_header_used_space_vc1	0
p_pcie_nonposted_header_used_space_vc2	0
p_pcie_nonposted_header_used_space_vc3	0
p_pcie_number_of_lanes	x4
p_pcie_phy_interface	Serial
p_pcie_pme_pending	0
p_pcie_pme_reg_id	0x0000
p_pcie_posted_data_credit_vc0	360
p_pcie_posted_data_credit_vc1	0
p_pcie_posted_data_credit_vc2	0
p_pcie_posted_data_credit_vc3	0
p_pcie_posted_data_used_space_vc0	5760
p_pcie_posted_data_used_space_vc1	0
p_pcie_posted_data_used_space_vc2	0
p_pcie_posted_data_used_space_vc3	0
p_pcie_posted_header_credit_vc0	50
p_pcie_posted_header_credit_vc1	0
p_pcie_posted_header_credit_vc2	0
p_pcie_posted_header_credit_vc3	0
p_pcie_posted_header_used_space_vc0	800
p_pcie_posted_header_used_space_vc1	0
p_pcie_posted_header_used_space_vc2	0
p_pcie_posted_header_used_space_vc3	0
p_pcie_rate	Gen2 (5.0 Gbps)
p_pcie_retry_buffer_size	16 KBytes
p_pcie_revision_id	0x01
p_pcie_rx_buffer_preset	Default
p_pcie_rx_buffer_size_string_vc0	16 KBytes
p_pcie_rx_buffer_size_string_vc1	0
p_pcie_rx_buffer_size_string_vc2	0
p_pcie_rx_buffer_size_string_vc3	0
p_pcie_rx_buffer_size_vc0	16384
p_pcie_rx_buffer_size_vc1	0
p_pcie_rx_buffer_size_vc2	0
p_pcie_rx_buffer_size_vc3	0
p_pcie_slot_capabilities	0x00000000
p_pcie_special_phy_gl	0
p_pcie_special_phy_px	1
p_pcie_subsystem_device_id	0x2400
p_pcie_subsystem_vendor_id	0xF091
p_pcie_surprise_down_error_support	0
p_pcie_target_performance_preset	Maximum
p_pcie_test_out_width	9 bits
p_pcie_threshold_for_L0s_entry	8192 ns
p_pcie_total_header_credit_vc0	216
p_pcie_total_header_credit_vc1	0
p_pcie_total_header_credit_vc2	0
p_pcie_total_header_credit_vc3	0
p_pcie_txrx_clock	100 MHz
p_pcie_underSOPCBuilder	false
p_pcie_use_crc_forwarding	0
p_pcie_variation_name	top_core
p_pcie_vendor_id	0x1172
p_pcie_version	2.0
p_pcie_virutal_channels	1
pref_nonp_independent	false
translationTableSizeInfo	The bridge reserves a contiguous Avalon address range to access PCIe devices. This Avalon address range is segmented into one or more equal-sized pages that are individually mapped to PCIe addresses. Select the number and size of the address pages.
uiAvalonHWAddress0	0x00000000
uiAvalonHWAddress1	0x00000000
uiAvalonHWAddress10	0x00000000
uiAvalonHWAddress11	0x00000000
uiAvalonHWAddress12	0x00000000
uiAvalonHWAddress13	0x00000000
uiAvalonHWAddress14	0x00000000
uiAvalonHWAddress15	0x00000000
uiAvalonHWAddress2	0x00000000
uiAvalonHWAddress3	0x00000000
uiAvalonHWAddress4	0x00000000
uiAvalonHWAddress5	0x00000000
uiAvalonHWAddress6	0x00000000
uiAvalonHWAddress7	0x00000000
uiAvalonHWAddress8	0x00000000
uiAvalonHWAddress9	0x00000000
uiAvalonHWPCIAddress0	0x00000000
uiAvalonHWPCIAddress1	0x00000000
uiAvalonHWPCIAddress10	0x00000000
uiAvalonHWPCIAddress11	0x00000000
uiAvalonHWPCIAddress12	0x00000000
uiAvalonHWPCIAddress13	0x00000000
uiAvalonHWPCIAddress14	0x00000000
uiAvalonHWPCIAddress15	0x00000000
uiAvalonHWPCIAddress2	0x00000000
uiAvalonHWPCIAddress3	0x00000000
uiAvalonHWPCIAddress4	0x00000000
uiAvalonHWPCIAddress5	0x00000000
uiAvalonHWPCIAddress6	0x00000000
uiAvalonHWPCIAddress7	0x00000000
uiAvalonHWPCIAddress8	0x00000000
uiAvalonHWPCIAddress9	0x00000000
uiAvalonTranslationTable	false
uiBar0PCIAddress	0x00000000
uiBar0Prefetchable	false
uiBar1PCIAddress	0x00000000
uiBar1Prefetchable	true
uiBar2PCIAddress	0x00000000
uiBar2Prefetchable	false
uiBar3PCIAddress	0x00000000
uiBar3Prefetchable	true
uiBar4PCIAddress	0x00000000
uiBar4Prefetchable	true
uiBar5PCIAddress	0x00000000
uiBar5Prefetchable	true
uiCRAInfoPanel	other
uiExpROMType	Select to Enable
uiFixedTable	true
uiPCIBar0Type	32-bit Non-Prefetchable Memory
uiPCIBar1Type	32-bit Non-Prefetchable Memory
uiPCIBar2Type	32-bit Non-Prefetchable Memory
uiPCIBar3Type	Disable this and all higher BARs
uiPCIBar4Type	Disable this and all higher BARs
uiPCIBar5Type	Disable this and all higher BARs
uiPCIBarTable	false
uiPCIBusArbiter	external
uiPCIDeviceMode	masterTarget
uiPCIMasterPerformance	burstSinglePending
uiPCITargetPerformance	burstSinglePending
uiPaneCount	1
uiPaneSize	20
ui_pcie_msix_pba_bir	0
ui_pcie_msix_table_bir	0
p_pcie_enable_hip_core_clk	0
p_pcie_avalon_mm_lite	0
altgx_generated	0
p_pcie_altgx_keyParameters_used	{}
p_pcie_disable_L0s	false
p_pcie_enable_pcie_gen2_x8_es	0
p_pcie_enable_pcie_gen2_x8_s5gx	0
p_pcie_use_parity	false
p_tx_cdc_full_value	12

MegaCore Function Variation File Parameters

Name	Value
tx_cdc_full_value	12
p_pcie_hip_type	0
retry_buffer_last_active_address	2047
advanced_errors	false
bar0_io_space	false
bar0_64bit_mem_space	false
bar0_prefetchable	false
bar0_size_mask	28
bar1_io_space	false
bar1_64bit_mem_space	false
bar1_prefetchable	false
bar1_size_mask	18
bar2_io_space	false
bar2_64bit_mem_space	false
bar2_prefetchable	false
bar2_size_mask	18
enable_ecrc_check	false
enable_ecrc_gen	false
enable_l1_aspm	false
l01_entry_latency	31
pcie_mode	SHARED_MODE
extend_tag_field	false
bypass_cdc	false
vc_arbitration	0
no_soft_reset	true
extend_tag_field	false
enable_ch0_pclk_out	false
core_clk_divider	2
millisecond_cycle_count	250000
max_link_width	4
lane_mask	11110000
single_rx_detect	4
enable_adapter_half_rate_mode	false
enable_coreclk_out_half_rate	false
enable_gen2_core	true
gen2_lane_rate_mode	true
lane_mask	11110000
max_link_width	4
vendor_id	4466
device_id	57345
revision_id	1
class_code	16711680
subsystem_vendor_id	61585
subsystem_device_id	9216
port_link_number	1
max_payload_size	1
msi_function_count	2
endpoint_l0_latency	0
endpoint_l1_latency	0
diffclock_nfts_count	255
sameclock_nfts_count	255
l1_exit_latency_sameclock	7
l1_exit_latency_diffclock	7
l0_exit_latency_sameclock	7
l0_exit_latency_diffclock	7
enable_msi_64bit_addressing	true
gen2_diffclock_nfts_count	255
gen2_sameclock_nfts_count	255
enable_function_msix_support	false
credit_buffer_allocation_aux	BALANCED
eie_before_nfts_count	4
completion_timeout	ABCD
enable_adapter_half_rate_mode	false
enable_completion_timeout_disable	true
msix_pba_bir	0
msix_pba_offset	0
msix_table_bir	0
msix_table_offset	0
msix_table_size	0
use_crc_forwarding	false
RX_BUF	11
RH_NUM	8
G_TAG_NUM0	32

MegaCore Function Variation File Ports

Name	Direction	Width
AvlClk_i	INPUT	1
CraAddress_i	INPUT	12
CraByteEnable_i	INPUT	4
CraChipSelect_i	INPUT	1
CraRead	INPUT	1
CraWrite	INPUT	1
CraWriteData_i	INPUT	32
Rstn_i	INPUT	1
RxmIrqNum_i	INPUT	6
RxmIrq_i	INPUT	1
RxmReadDataValid_i	INPUT	1
RxmReadData_i	INPUT	64
RxmWaitRequest_i	INPUT	1
TxsAddress_i	INPUT	17
TxsBurstCount_i	INPUT	10
TxsByteEnable_i	INPUT	8
TxsChipSelect_i	INPUT	1
TxsRead_i	INPUT	1
TxsWriteData_i	INPUT	64
TxsWrite_i	INPUT	1
aer_msi_num	INPUT	5
app_int_sts	INPUT	1
app_msi_num	INPUT	5
app_msi_req	INPUT	1
app_msi_tc	INPUT	3
core_clk_in	INPUT	1
cpl_err	INPUT	7
cpl_pending	INPUT	1
crst	INPUT	1
hpg_ctrler	INPUT	5
lmi_addr	INPUT	12
lmi_din	INPUT	32
lmi_rden	INPUT	1
lmi_wren	INPUT	1
npor	INPUT	1
pclk_central	INPUT	1
pclk_ch0	INPUT	1
pex_msi_num	INPUT	5
pld_clk	INPUT	1
pll_fixed_clk	INPUT	1
pm_auxpwr	INPUT	1
pm_data	INPUT	10
pm_event	INPUT	1
pme_to_cr	INPUT	1
rc_areset	INPUT	1
rc_inclk_eq_125mhz	INPUT	1
rc_pll_locked	INPUT	1
rc_rx_pll_locked_one	INPUT	1
rx_st_mask0	INPUT	1
rx_st_ready0	INPUT	1
srst	INPUT	1
test_in	INPUT	40
tx_st_data0	INPUT	64
tx_st_data0_p1	INPUT	64
tx_st_eop0	INPUT	1
tx_st_eop0_p1	INPUT	1
tx_st_err0	INPUT	1
tx_st_sop0	INPUT	1
tx_st_sop0_p1	INPUT	1
tx_st_valid0	INPUT	1
phystatus0_ext	INPUT	1
rxdata0_ext	INPUT	8
rxdatak0_ext	INPUT	1
rxelecidle0_ext	INPUT	1
rxstatus0_ext	INPUT	3
rxvalid0_ext	INPUT	1
phystatus1_ext	INPUT	1
rxdata1_ext	INPUT	8
rxdatak1_ext	INPUT	1
rxelecidle1_ext	INPUT	1
rxstatus1_ext	INPUT	3
rxvalid1_ext	INPUT	1
phystatus2_ext	INPUT	1
rxdata2_ext	INPUT	8
rxdatak2_ext	INPUT	1
rxelecidle2_ext	INPUT	1
rxstatus2_ext	INPUT	3
rxvalid2_ext	INPUT	1
phystatus3_ext	INPUT	1
rxdata3_ext	INPUT	8
rxdatak3_ext	INPUT	1
rxelecidle3_ext	INPUT	1
rxstatus3_ext	INPUT	3
rxvalid3_ext	INPUT	1
CraIrq_o	OUTPUT	1
CraReadData_o	OUTPUT	32
CraWaitRequest_o	OUTPUT	1
RxmAddress_o	OUTPUT	32
RxmBurstCount_o	OUTPUT	10
RxmByteEnable_o	OUTPUT	8
RxmRead_o	OUTPUT	1
RxmWriteData_o	OUTPUT	64
RxmWrite_o	OUTPUT	1
TxsReadDataValid_o	OUTPUT	1
TxsReadData_o	OUTPUT	64
TxsWaitRequest_o	OUTPUT	1
app_int_ack	OUTPUT	1
app_msi_ack	OUTPUT	1
avs_pcie_reconfig_readdata	OUTPUT	16
avs_pcie_reconfig_readdatavalid	OUTPUT	1
avs_pcie_reconfig_waitrequest	OUTPUT	1
core_clk_out	OUTPUT	1
derr_cor_ext_rcv0	OUTPUT	1
derr_cor_ext_rpl	OUTPUT	1
derr_rpl	OUTPUT	1
dl_ltssm	OUTPUT	5
dlup_exit	OUTPUT	1
eidle_infer_sel	OUTPUT	24
ev_128ns	OUTPUT	1
ev_1us	OUTPUT	1
hip_extraclkout	OUTPUT	2
hotrst_exit	OUTPUT	1
int_status	OUTPUT	4
l2_exit	OUTPUT	1
lane_act	OUTPUT	4
lmi_ack	OUTPUT	1
lmi_dout	OUTPUT	32
npd_alloc_1cred_vc0	OUTPUT	1
npd_cred_vio_vc0	OUTPUT	1
nph_alloc_1cred_vc0	OUTPUT	1
nph_cred_vio_vc0	OUTPUT	1
pme_to_sr	OUTPUT	1
r2c_err0	OUTPUT	1
rate_ext	OUTPUT	1
rc_gxb_powerdown	OUTPUT	1
rc_rx_analogreset	OUTPUT	1
rc_rx_digitalreset	OUTPUT	1
rc_tx_digitalreset	OUTPUT	1
reset_status	OUTPUT	1
rx_fifo_empty0	OUTPUT	1
rx_fifo_full0	OUTPUT	1
rx_st_bardec0	OUTPUT	8
rx_st_be0	OUTPUT	8
rx_st_be0_p1	OUTPUT	8
rx_st_data0	OUTPUT	64
rx_st_data0_p1	OUTPUT	64
rx_st_eop0	OUTPUT	1
rx_st_eop0_p1	OUTPUT	1
rx_st_err0	OUTPUT	1
rx_st_sop0	OUTPUT	1
rx_st_sop0_p1	OUTPUT	1
rx_st_valid0	OUTPUT	1
serr_out	OUTPUT	1
suc_spd_neg	OUTPUT	1
swdn_wake	OUTPUT	1
swup_hotrst	OUTPUT	1
test_out	OUTPUT	64
tl_cfg_add	OUTPUT	4
tl_cfg_ctl	OUTPUT	32
tl_cfg_ctl_wr	OUTPUT	1
tl_cfg_sts	OUTPUT	53
tl_cfg_sts_wr	OUTPUT	1
tx_cred0	OUTPUT	36
tx_deemph	OUTPUT	8
tx_fifo_empty0	OUTPUT	1
tx_fifo_full0	OUTPUT	1
tx_fifo_rdptr0	OUTPUT	4
tx_fifo_wrptr0	OUTPUT	4
tx_margin	OUTPUT	24
tx_st_ready0	OUTPUT	1
use_pcie_reconfig	OUTPUT	1
wake_oen	OUTPUT	1
powerdown0_ext	OUTPUT	2
rxpolarity0_ext	OUTPUT	1
txcompl0_ext	OUTPUT	1
txdata0_ext	OUTPUT	8
txdatak0_ext	OUTPUT	1
txdetectrx0_ext	OUTPUT	1
txelecidle0_ext	OUTPUT	1
powerdown1_ext	OUTPUT	2
rxpolarity1_ext	OUTPUT	1
txcompl1_ext	OUTPUT	1
txdata1_ext	OUTPUT	8
txdatak1_ext	OUTPUT	1
txdetectrx1_ext	OUTPUT	1
txelecidle1_ext	OUTPUT	1
powerdown2_ext	OUTPUT	2
rxpolarity2_ext	OUTPUT	1
txcompl2_ext	OUTPUT	1
txdata2_ext	OUTPUT	8
txdatak2_ext	OUTPUT	1
txdetectrx2_ext	OUTPUT	1
txelecidle2_ext	OUTPUT	1
powerdown3_ext	OUTPUT	2
rxpolarity3_ext	OUTPUT	1
txcompl3_ext	OUTPUT	1
txdata3_ext	OUTPUT	8
txdatak3_ext	OUTPUT	1
txdetectrx3_ext	OUTPUT	1
txelecidle3_ext	OUTPUT	1