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=Chapter 1 DE10-Advanced Development Kit= Terasic A10SOC is a kind of the best SoC FPGA development platform with various advanced interfaces. It built around the Intel Arria 10 SoC FPGA, which combines the dual-core ARM Cortex A9 CPU and provides 660K LEs. A10SOC has many peripherals, it can transfer data to PC with a high speed through PCIEx4 GEN3 and Type-C USB connector. The four SFP interfaces and Gigabit Ethernet ports can be used in network application. HDMI 2.0 output and the two DDR4 SO-DIMMs allow users to deal with high bandwidth of image. A10SOC provides a FMC connector, it can extend more development space. Generally speaking, A10SoC has powerful computing and interface processing capacity, it must be the best choice for Network Communication, High Performance Computing, Image Processing and other applications. ==Package Contents== The DE10-Advanced package includes: *The DE10-Advanced board *Quick Start Guide *TBD ==DE10-Advanced System CD== The DE10-Advanced System CD contains all the documents and supporting materials associated with DE10-Advanced, including the user manual, system builder, reference designs and device datasheets. Users can download this system CD from the link: http://DE10-Advanced.terasic.com/cd. ==Getting Help== Here are the addresses where you can get help if you encounter any problems: Terasic Technologies 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan Email: support@terasic.com Tel.: +886-3-575-0880 Website: DE10-Advanced.terasic.com =Chapter 2 Introduction of the DE10-Advanced Board= This chapter provides an introduction to the features and design characteristics of the board. ==Layout and Components== Figure 2-1 and Figure 2-2 shows a photograph of the board. It depicts the layout of the board and indicates the location of the connectors and key components. [[File:De10-ad1.jpg|700px]] :::::::Figure 2-1 DE10-Advanced development board (top view) ::::[[File:De10-ad2.jpg|600px]] ::::::Figure 2-2 DE10-Advanced development board (bottom view) The DE10-Advanced board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardwares are provided on the board: *FPGA **Intel Arria10® 10 SoC 10AS066K3F40E2SG device (660K LEs) **USB-Blaster II onboard for programming:JTAG Mode **Serial configuration device-EPCQL1024 **DDR4 SO-DIMM Socket, support ECC **On board 32-bits DDR4 with ECC **USB Type-C Interface ***Power Delivery ***DisplayPort TX/RX with 4 lanes ***USB 3.0/2.0 **HDMI TX 2.0 for 4K2K@60-FPGA Transceiver **PCIe Cabling Socket at Gen3 x4 **SFP+ Socket x4, 40Gbps **SATA 3.0 Host and SATA Device x2 (SATA Connector x4) **One Gigabit Ethernet Port **SMA Clock-In and Clock-Out **High Pin Count FMC Connector. Support VADJ 1.2V/1.5V/1.8V **Accelerometer, Gyroscope and Magnetometer **Temperature Sensor **Fan Control **LED x2, KEY x2 , Switch x2, 7-Segment x2 *HPS(Hard Processor System) **1.5GHz Dual-core ARM Cortex-A9 processor **Boot Flash Slot ***1024 Mb QSPI Flash ***Nand Flash ***MicroSD Socket **DDR4 SO-DIMM Socket, support ECC **1 Gigabit Ethernet PHY with RJ45 connector **USB OTG Port, USB mini-AB connector **UART to USB, USB Mini-B connector **RTC **One user button and one user LED **Warm reset button and cold reset button ==Block Diagram of the DE10-Advanced Board== Figure 2-3 is the block diagram of the board. All the connections are established through the Arria 10 SoC FPGA device to provide maximum flexibility for users. Users can configure the FPGA to implement any system design. [[File:De10-ad3.jpg|900px]] ::::::::::::::Figure 2-3 Block diagram of DE10-Advanced Detailed information about Figure 2-3 are listed below. Arria 10 SoC 10AS066K3F40E2SG/10AS057K3F40E2SG FPGA *Dual-core ARM Cortex-A9 (HPS) *660K programmable logic elements *42,660 Kbits embedded memory *Hard memory controllers x5 *Transceivers x48(17.4 Gbps) *18-bit x 19-bit multipliers x3,356 *Accelerometer & Gyroscope Device MPU9250 Configuration *EPCQ512 Serial Configuration Device *Onboard USB-Blaster II (Mini-B USB connector) Memory Device *32GB DDR4 SDRAM on FPGA *Two DDR4 SO-DIMM SDRAM socket *Micro SD card socket *1024Mb QSPI Flash Communication *USB OTG (Mini-AB USB connector) *UART-to-USB (Mini-B USB Connector) *Giga Ethernet x2 *PCIe Gen3 x4 Cabling Socket FMC connector *one HPC(high-pin count) FMC connector with xcvr *Adjustable VADJ:1.2V/1.5V/1.8V *FMC Vita57.1 Standard SDI connectors *Two 12G-SDI connectors for SDI in and out SMA connectors *Two SMA connectors for SMA Clock-In and Clock-Out *Support 1.8V I/O Standard General user input/output *Buttons x3 (FPGA x2, HPS x1) *Switches x2 on FPGA *LEDs x3 (FPGA x2, HPS x1) *7-segment displays x2 System Monitor and Control *Temperature Sensor on FPGA *12V Power Monitor *Power Controller *I2C Fan Control Power *12V DC input =Chapter 3 Board Setting and Status component= This chapter describes all the setting devices on DE10-Advanced board and their functions, such as Switches and Headers. We also will describe the function of some status LEDs. The JTAG interface will be described at the end of this chapter. ==Board Setting Switches== ===USB Type C Connector Setting Switches=== The one USB Type C Connector on the board can be connected to many applications as shown in Figure 3-1, such as USB 3.1 Gen1/Gen2, and Displayport Alternate Mode. [[File:Type c controller.jpg|700px]] ::::Figure 3-1 The switching circuit of the USB type C connector <br/>These applications are connected to many switch circuit, users can use switches(SW3/SW4) to switch different applications. System MAX received the switch setting value and generate related control signal to switch the circuit. Table 3-1 list the switch setting of each application.<br/> About the detailed description of each application interface, please refer to Chapter 4 for their separate introduction.<br/> :::::::::::::Table 3-1 Switches setting for each interface :{| class="wikitable" |- !Item !!Interface !!Switches Setting !!Descriptions |- |1 ||USB3.1 Gen 1 Controller||MAX_SW[7]=0<br/>MAX_SW[4]=0<br/>MAX_SW[3]=0<br/>MAX_SW[1]=0<br/>MAX_SW[5]=0 For OTG Device<br/>MAX_SW[5]=1 For OTG Host||Using Cypress's EZ-USB FX3 SuperSpeed USB Controller |- |2 ||USB 3.1 Gen2 Host||MAX_SW[4]=0<br/>MAX_SW[3]=0<br/>MAX_SW[1]=0<br/>MAX_SW[0]=0||USB 3.1 GEN2 Controller IP,data bus connect to USB Type C connector directly in FPGA |- |3 ||USB 3.1 Gen2 Device||MAX_SW[4]=0<br/>MAX_SW[3]=0<br/>MAX_SW[1]=1<br/>MAX_SW[0]=0||USB 3.1 GEN2 Controller IP,data bus connect to USB Type C connector directly in FPGA |- |4 ||Display Port Source||MAX_SW[4]=0<br/>MAX_SW[3]=1<br/>MAX_SW[2]=1||DisplayPort Controller IP,data bus connect to USB Type C connector directly in FPGA |- |5 ||Display Port Sink||MAX_SW[4]=0<br/>MAX_SW[3]=1<br/>MAX_SW[2]=0||DisplayPort Controller IP,data bus connect to USB Type C connector directly in FPGA |} ===Mode Select Switches=== Mode Select Switch(SW5) is used to set the DE10-Advanced FPGA MSEL pin value.These MSEL pins determined the Configuration Mode of the FPGA.Table 3-2 list the MSEL setting for configuration scheme of FPGA,when MSEL is set to AS mode,FPGA will be booted from EPCQ device.When MSEL is set to FPP mode,FPGA can be configured by HPS Fabric.<br/> :Table 3-2 MSEL setting for configuration scheme of FPGA :{| class="wikitable" |- !Configuration Scheme !!MSEL[2..0] Setting !!SW5 Setting |- |AS Mode (Factory Default) ||010|| |- |FPP Mode ||001|| |} ==Board Setting Headers== ===JTAG Interface Header=== J17 and J18 are headers which are used to set the JTAG bus of system max and FMC connector connect to JTAG interface of DE10-Advanced system.The system max and FMC connector will not be included in the JTAG chain if the headers are set to open. Table 3-3 list the setting of the two headers.<br/> ::::Table 3-3 JTAG Interface Headers Setting :{| class="wikitable" |- !Header !!Setting !!Descriptions |- |J17 ||Installed||Enable the JTAG interface of the system max |- |J18 ||Installed||Enable the JTAG interface of the FMC connector |} ===FMC_VCCIO Select Header=== JP2 is used to set the VCCIO voltage of FPGA I/O on FMC connector, as1.2V/1.5V/1.8V are supported, the FMC connector can support various I/0 standard FMC daughtercards. Table 3-4 list the FMC_VCCIO Headers Setting.<br/> ::Table 3-4 FMC_VCCIO Headers Setting :{| class="wikitable" |- !JP2 Setting !!FMC VCCIO Voltage |- |Installed Pin 1 and 2 ||1.2V |- |Installed Pin 3 and 4 ||1.5V |- |Installed Pin 5 and 6 ||1.8V |} ===DDR4 VCCIO Select Header=== JP3 is used to set the VCCIO voltage of FPGA I/O on DDR4 SO-DIMM Socket.As1.2V/1.5V/1.8V are supported,the DDR4 SO-DIMM Socket can support various I/0 standard DDR4 memory.<br/> ::Table 3-5 DDR4 VCCIO Headers Setting :{| class="wikitable" |- !JP3 Setting !!DDR4 VCCIO Voltage |- |Installed Pin 1 and 2 ||1.2V |- |Installed Pin 3 and 4 ||1.5V |- |Installed Pin 5 and 6 ||1.8V |} ===External USB Blaster Header=== J11 provide users a JTAG interface which can connect external USB blaster to DE10-Advanced board.When the external USB blaster connect to the board,the on-board USB blaster II circuit will be disable temporary until users move the external USB blaster from the J11 header. ==Status LED== This section describes the all status LED for the interfaces on DE10-Advanced board. ===System MAX=== There are five LEDs indicate the status for system MAX, as list in Table 3-6.<br/> ::::::Table 3-6 Status LED for system MAX :{| class="wikitable" |- !Component !!Reference !!Status !!Descriptions |- |CONFIG_DONE ||CONFIG_DONE_LED||ON||FPGA configuration is done |- |FMC_12V ||FMC_12V_LED||ON||FMC daughtercard connect to FMC connector |- |PD ||USB_TYPEC_LED0||ON||USB Type-C work as UFP(Upstream Facing Port) mode |- |DP ||USB_TYPEC_LED1||ON||DisplayPort SINK |- |USB ||USB_TYPEC_LED2||ON||USB Device |} ===UART Interface=== Table 3-7 list the two status LEDs for UART interface.<br/> ::Table 3-7 Status LED for UART Interface :{| class="wikitable" |- !Component !!Reference !!Status !!Descriptions |- |TXD1 ||UART_TXD||ON||Transmitting |- |RXD1 ||UART_ＲXD||ON||Receiving |} ===SFP Interface=== Table 3-8 list the four status LEDs for SFP interface.<br/> :::Table 3-8 Indicator LED for SFP Interface :{| class="wikitable" |- !Component !!Reference !!Status !!Descriptions |- |D4 ||SFPA_MOD0_PRSNT_n||ON||Indicate that the SFP module is present on the SFPA |- |D3 ||SFPB_MOD0_PRSNT_n||ON||Indicate that the SFP module is present on the SFPB |- |D2 ||SFPC_MOD0_PRSNT_n||ON||Indicate that the SFP module is present on the SFPC |- |D1 ||SFPD_MOD0_PRSNT_n||ON||Indicate that the SFP module is present on the SFPD |} ===Ethernet Interface=== Table 3-9 list the four status LEDs for Ethernet interface.<br/> ::Table 3-9 Status LED for Ethernet Interface :{| class="wikitable" |- !Component !!Reference !!Status !!Descriptions |- |D8 ||ETH_LED_TX||ON||Transmitting |- |D9 ||ETH_LED_RX||ON||Receiving |- |D10 ||ETH_LINK1000||ON||1000Mbps Link UP |- |D11 ||SFPD_MOD0_PRSNT_n||ON||100Mbps Link UP |} ===Power=== Table 3-10 list the two status LEDs for power.<br/> ::::Table 3-10 Status LED for Power :{| class="wikitable" |- !Component !!Reference !!Status !!Descriptions |- |D14 ||20V Power Indicator||ON||20V Power Supply |- |D15 ||12V Power Indicator||ON||12V Power Supply |} ==JTAG Interface== Figure 3-2 shows the JTAG interface of DE10-Advanced.Users can access to the JTAG interface through the USB Blaster II circuit or connect external blaster to external blaster header.All the devices which implement JTAG are connect to MAX II device,and switch via MAX II internal switch logic.By using headers J17 and J18,users can include System MAX and FMC connector JTAG interface in the DE10-Advanced JTAG Chain,or exclude them from the JTAG Chain.<br/> [[File:JTAG INTERFACE.jpg|500px]] ::::::Figure 3-2 JTAG interface of DE10-Advanced =Chapter 4 FPGA Fabric component= This chapter describes the interfaces connected to the FPGA. Users can control or monitor different interfaces with user logic from the FPGA. ==USB Type C Port== USB Type-C is the new USB-IF standard that solves several challenges. It provides up to 100W power, so this board can be powered by USB type-C source and also can play a role as a USB power provider (To charge a NB or any USB type-C device up to 12V@3A). The bandwidth is double, increasing to 10Gbps with SuperSpeed+ USB3.1, and it combines multiple protocols in single cable, including DP and PCIe. And the connector is a reversible-plug connector which will be easier to use. Figure 4-1 shows the connections of USB Type C Port.Table 4-1 list the USB Type C Port assignments and signal names relative to the Arria 10 SoC FPGA.<br/> :::[[File:Type c controller.jpg|700px]]<br/> ::::::::::::Figure 4-1 USB Type C Port connections<br/><br/><br/> :Table 4-1 USB Type C Port Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |USB_REFCLK_p ||PIN_AB31 || USB reference clock ||LVDS |- |USB_TX_p ||PIN_AB39 || USB transfer signal ||HSSI DIFFERENTIAL I/O |- |USB_RX_p ||PIN_AA37 || USB receive signal ||HSSI DIFFERENTIAL I/O |- |USB_PD_SCL ||PIN_AJ19 || SerialClock line ||1.8V |- |USB_PD_SDA ||PIN_AV16 ||SerialData line ||1.8V |} ==Gigabit Ethernet== The development board supports one RJ45 10/100/1000 base-T Ethernet using Marvell 88E1111. SGMII AC coupling interface is used between PHY and FPGA transceiver.The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Arria 10 SoC FPGA can communicate with the LVDS interfaces at up to 1.6 Gbps, which is faster than 1.25 Gbps for SGMII. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.1-V power rails and requires a 25MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 with internal magnetics for driving copper lines with Ethernet traffic.Figure 4-2 shows the SGMII interface between the FPGA and Marvell 88E1111 PHY. Table 4-2 lists the Ethernet PHY interface pin assignments. ::::[[File:Ethernet.jpg]]<br/> :::::::::::Figure 4-2 SGMII Interface between FPGA and Marvell 88E1111 PHY :Table 4-2 Ethernet PHY Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |ETH_TX_p ||PIN_AP19||SGMII TX data ||LVDS |- |ETH_RX_p ||PIN_AM20||SGMII RX data ||LVDS |- |ETH_INT_n ||PIN_AU19||Management bus interrupt ||1.8V |- |ETH_MDC ||PIN_AT19||Management bus control ||1.8V |- |ETH_MDIO ||PIN_AJ20||Management bus data ||1.8V |- |ETH_RST_n ||PIN_AK20||Device reset ||1.8V |} ==SFP+ Connector== The development board has four independent 10G SFP+ connectors that use one transceiver channel each from the Arria 10 SoC FPGA device. These modules take in serial data from the Arria 10 SoC FPGA device and transform them to optical signals. The board includes cage assemblies for the SFP+ connectors.Figure 4-3 shows the connections between the SFP+ and Arria 10 SoC FPGA.<br/> :::::[[File:De10-ad SFP.jpg|600px]] ::::::::Figure 4-3 Connection between the SFP+ and Arria 10 SoC FPGA<br/><br/> Table 4-3, Table 4-4, Table 4-5 and Table 4-6 list the four QSF+ connectors assignments and signal names relative to the Arria 10 SoC FPGA<br/> ::::::Table 4-3 SFP+ A Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |SFPA_TXDISABLE ||PIN_W28||Turns off and disables the transmitter output ||1.2V |- |SFPA_TXFAULT ||PIN_T28 ||Transmitter fault ||1.2V |- |SFPA_TX_p ||PIN_AG37||Transmiter data ||HSSI DIFFERENTIAL I/O |- |SFPA_RX_p ||PIN_AD35 ||Receiver data ||HSSI DIFFERENTIAL I/O |- |SFPA_LOS ||PIN_G27||Signal loss indicator ||1.2V |- |SFPA_MOD0_PRSNT_n|| PIN_K27||Module present ||1.2V |- | SFPA_RATESEL0||PIN_G13 || Rate select 0 ||3.3V |- |SFPA_RATESEL1 ||PIN_G15 || Rate select 1 ||3.3V |- |SFPA_TX_n ||PIN_AG36 || Transmitter data ||HSSI DIFFERENTIAL I/O |- | SFPA_RX_n ||PIN_AD34 || Receiver data ||HSSI DIFFERENTIAL I/O |} ::::::Table 4-4 SFP+ B Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |SFPB_TXDISABLE ||PIN_B22||Turns off and disables the transmitter output ||1.2V |- |SFPB_TXFAULT ||PIN_F15||Transmitter fault ||1.2V |- |SFPB_TX_p ||PIN_AF39||Transmiter data ||HSSI DIFFERENTIAL I/O |- |SFPB_RX_p ||PIN_AC37||Receiver data ||HSSI DIFFERENTIAL I/O |- |SFPB_LOS ||PIN_K16||Signal loss indicator ||1.2V |- |SFPB_MOD0_PRSNT_n ||PIN_Y27||Module present ||1.2V |- |SFPB_RATESEL0 || PIN_G14 ||Rate select 0 ||3.3V |- |SFPB_RATESEL1 || PIN_F16 || Rate select 1 ||3.3V |- |SFPB_TX_n || PIN_AF38 || Transmitter data ||HSSI DIFFERENTIAL I/O |- |SFPB_RX_n || PIN_AC36 || Receiver data ||HSSI DIFFERENTIAL I/O |} ::::::Table 4-5 SFP+ C Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |SFPC_TXDISABLE ||PIN_AN6||Turns off and disables the transmitter output ||1.2V |- |SFPC_TXFAULT ||PIN_AE10||Transmitter fault ||1.2V |- |SFPC_TX_p ||PIN_AE37||Transmiter data ||HSSI DIFFERENTIAL I/O |- |SFPC_RX_p ||PIN_AC33||Receiver data ||HSSI DIFFERENTIAL I/O |- |SFPC_LOS ||PIN_AW3||Signal loss indicator ||1.2V |- |SFPC_MOD0_PRSNT_n ||PIN_AP3||Module present ||1.2V |- |SFPC_RATESEL0 || PIN_F15 ||Rate select 0 ||3.3V |- |SFPC_RATESEL1 || PIN_E16 || Rate select 1 ||3.3V |- |SFPC_TX_n || PIN_AE36 || Transmitter data ||HSSI DIFFERENTIAL I/O |- |SFPC_RX_n || PIN_AC32 || Receiver data ||HSSI DIFFERENTIAL I/O |} ::::::Table 4-6 SFP+ D Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |SFPD_TXDISABLE ||PIN_M1||Turns off and disables the transmitter output ||1.2V |- |SFPD_TXFAULT ||PIN_M4||Transmitter fault ||1.2V |- |SFPD_TX_p ||PIN_AD39||Transmiter data ||HSSI DIFFERENTIAL I/O |- |SFPD_RX_p ||PIN_AB35||Receiver data ||HSSI DIFFERENTIAL I/O |- |SFPD_LOS ||PIN_T2||Signal loss indicator ||1.2V |- |SFPD_MOD0_PRSNT_n ||PIN_V7||Module present ||1.2V |- |SFPD_RATESEL0 || PIN_E15 ||Rate select 0 ||3.3V |- |SFPD_RATESEL1 || PIN_F13 || Rate select 1 ||3.3V |- |SFPD_TX_n || PIN_AD38 || Transmitter data ||HSSI DIFFERENTIAL I/O |- |SFPD_RX_n || PIN_AB34 || Receiver data ||HSSI DIFFERENTIAL I/O |} ==SATA== Four Serial ATA (SATA) ports are available on the FPGA development board which are computer bus standard with a primary function of transferring data between the motherboard and mass storage devices (such as hard drives, optical drives, and solid-state disks). Supporting a storage interface is just one of many different applications an FPGA can be used in storage appliances. The Arria 10 SoC device can bridge different protocols such as bridging simple bus I/Os like PCI Express (PCIe) to SATA or network interfaces such as Gigabit Ethernet (GbE) to SATA. The SATA interface supports SATA 3.0 standard with connection speed of 6 Gbps based on Arria 10 SoC device with integrated transceivers compliant to SATA electrical standards.<br/> The four Serial ATA (SATA) ports include two available ports for device and two available ports for host capable of implementing SATA solution with a design that consists of both host and target(device side) functions.Figure 4-4 depicts the host and device design examples.<br/> ::::[[File:SATA.jpg|600px]]<br/> :::::::Figure 4-4 PC and storage device connection to the Arria 10 SoC FPGA<br/> The transmitter and receiver signals of the SATA ports are connected directly to the Arria 10 SoC transceiver channels to provide SATA IO connectivity to both host and target devices. To verify the functionality of the SATA host/device ports, a connection can be established between the two ports by using a SATA cable as Figure 4-5 depicts the associated signals connected.Table 4-7 lists the SATA pin assignments, signal names and functions.<br/> :::[[File:SATA1.jpg|600px]]<br/> ::::::::Figure 4-5 Pin connection between SATA connectors<br/> :::::Table 4-7 SATA Pin Assignments,Signal Names and Functions<br/> :{| class="wikitable" |- !Signal Name!!FPGA Pin Number!!Description!!I/O Standard |- |colspan="4" |Device |- |SATA_DEVICE_REFCLK_p || PIN_M31 || SATA Device reference clock ||LVDS |- | SATA_DEVICE_REFCLK_n || PIN_M30 || SATA Device reference clock ||LVDS |- | SATA_DEVICE_RX_n0 || PIN_D34 ||Differential receive data input after DC blocking capacitor ||HSSI DIFFERENTIAL I/O |- | SATA_DEVICE_RX_n1 ||PIN_B34 ||Differential receive data input after DC blocking capacitor ||HSSI DIFFERENTIAL I/O |- | SATA_DEVICE_TX_n0 || PIN_B38 || Differential transmit data output before DC blocking capacitor ||HSSI DIFFERENTIAL I/O |- | SATA_DEVICE_TX_n1 ||PIN_A36 || Differential transmit data output before DC blocking capacitor ||HSSI DIFFERENTIAL I/O |- |SATA_DEVICE_TX_p0||PIN_B39||Differential transmit data output before DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_DEVICE_TX_p1||PIN_A37||Differential transmit data output before DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_DEVICE_RX_p0||PIN_D35||Differential receive data input after DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_DEVICE_RX_p1||PIN_B35||Differential receive data input after DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |colspan="4" |Host |- |SATA_HOST_REFCLK_p||PIN_V31||SATA Host reference clock||LVDS |- |SATA_HOST_REFCLK_n||PIN_V30||SATA Host reference clock||LVDS |- |SATA_HOST_TX_p0||PIN_P39||Differential transmit data output before DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_TX_p1||PIN_N37||Differential transmit data output before DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_RX_p0||PIN_U33||Differential receive data input after DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_RX_p1||PIN_T35||Differential receive data input after DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_TX_n0||PIN_P38||Differential transmit data output before DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_TX_n1||PIN_N36||Differential transmit data output before DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_RX_n0||PIN_U32||Differential receive data input after DC blocking capacitor||HSSI DIFFERENTIAL I/O |- |SATA_HOST_RX_n1||PIN_T34||Differential receive data input after DC blocking capacitor||HSSI DIFFERENTIAL I/O |} ==PCIe== The DE10-Advanced development board features one PCIe Express downstream interfaces (x4 lane) which are designed to interface with a PC motherboard x4 slot via PCIe cable and PCIe adapter card. Utilizing built-in transceivers on a Arria 10 SoC device, it is able to provide a fully integrated PCI Express compliant solution for multi-lane (x4) applications. With the PCI Express hard IP block incorporated in the Arria 10 SoC device, it will allow users to implement simple and fast protocols, as well as saving logic resources for logic applications. The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane, Gen2 at 5.0Gbps/lane, and Gen3 at 8.0Gbps/lane protocol stack solution compliant to PCI Express base specification 3.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks. To use PCIe interface, two external associated devices will be needed to establish a link with PC. First, a PCIe half-height add-in host card with a PCIe x4 cable connector called PCA (PCIe Cabling Adapter Card and see Figure 4-5, it will be used to plug into the PCIe slot on a mother board.<br/> ::::[[File:PCA.jpg|200px]]<br/> ::::Figure 4-5 PCIe Cabling Adaptor(PCA) card<br/> Then,a PCIe x4 cable(See Figure 4-6) will be used to connect DE10-Advanced board and PCIe add-in card, the longest length is up to 3 meters.These two associated devices are not included in DE10-Advanced board. To purchase the PCA card as well as the external cable, please refer to Terasic website [http://pca.terasic.com PCIe x4 Cable Adapter]and [http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=77&No=687 PCIe x4 Gen.2 Cable].Table 4-8 summarizes the PCI Express pin assignments of the signal names relative to the Arria 10 SoC FPGA.PCIe pin connection is showed in Figure 4-7.<br/> ::::[[File:PCA Cable.jpg|300px]]<br/> ::::::Figure 4-6 PCIe External Cable<br/> [[File:PCIe.jpg|500px]]<br/> :::::Figure 4-7 PCI Express Pin Connection ::::Table 4-8 PCIe Pin Assignments,Signal Names and Functions :{| class="wikitable" |- !Signal Name!!FPGA Pin Number!!Description!!I/O Standard |- |PCIE_REFCLK_p||PIN_AH31||PCIe reference clock||LVDS |- |PCIE_TX_p[0]||PIN_AR37||PCIe Transmitter data p0||HSSI DIFFERENTIAL I/O |- |PCIE_TX_p[1]||PIN_AP39||PCIe Transmitter data p1||HSSI DIFFERENTIAL I/O |- |PCIE_TX_p[2]||PIN_AN37||PCIe Transmitter data p2||HSSI DIFFERENTIAL I/O |- |PCIE_TX_p[3]||PIN_AM39||PCIe Transmitter data p3||HSSI DIFFERENTIAL I/O |- |PCIE_RX_p[0]||PIN_AL33||PCIe Receiver data p0||HSSI DIFFERENTIAL I/O |- |PCIE_RX_p[1]||PIN_AM35||PCIe Receiver data p1||HSSI DIFFERENTIAL I/O |- |PCIE_RX_p[2]||PIN_AJ33||PCIe Receiver data p2||HSSI DIFFERENTIAL I/O |- |PCIE_RX_p[3]||PIN_AK35||PCIe Receiver data p3||HSSI DIFFERENTIAL I/O |- |PCIE_PERST_n||PIN_AW20||PCIe present,active low||1.8 V |- |PCIE_WAKE_n||PIN_AL19||PCIe wake||1.8 V |} ==DDR4 SO-DIMM Socket== The development board supports two DDR4 SDRAM SO-DIMM,one is implemented on FPGA side and another one is implemented on HPS side. The DDR4 SODIMM socket is wired to support a maximum capacity of 8GB with a 64-bit data bus. Using differential DQS signaling for the DDR4 SDRAM interfaces, it is capable of running at up to 1067MHz memory clock. It also supports Terasic QDRII+ module and RLDRAM3 module.Figure 4-8 shows the connections between the DDR4 SDRAM SO-DIMM and Arria 10 SoC FPGA.The pin assignments for DDR4 SDRAM SO-DIMM are listed in Table 4-8.<br/> ::::[[File:DDR4-DE10-AD.jpg|500px]] ::::Figure 4-8 Connection between DDR4 SDRAM SO-DIMM and Arria 10 SoC FPGA<br/> :::::Table 4-8 DDR4 SO-DIMM Socket Pin Assignments,Signal Names and Functions :{| class="wikitable" |- !FPGA Pin Number !! Signal Name !!Description !!I/O Standard |- |PIN_AB12 ||DDR4A_REFCLK_p|| DDR4 A port Reference Clock p ||LVDS |- |PIN_AC1 ||DDR4A_A[0]|| Address [0] ||SSTL-12 |- |PIN_AB1 || DDR4A_A[1] ||Address [1] ||SSTL-12 |- |PIN_AB4 ||DDR4A_A[2]|| Address [2] ||SSTL-12 |- |PIN_AA5 ||DDR4A_A[3]|| Address [3] ||SSTL-12 |- |PIN_AA3 ||DDR4A_A[4]|| Address [4] ||SSTL-12 |- |PIN_AA4 ||DDR4A_A[5]|| Address [5] ||SSTL-12 |- |PIN_Y2 || DDR4A_A[6]|| Address [6] ||SSTL-12 |- |PIN_AA2 ||DDR4A_A[7]|| Address [7] ||SSTL-12 |- |PIN_AB5 || DDR4A_A[8]|| Address [8] ||SSTL-12 |- |PIN_AB6 || DDR4A_A[9]|| Address [9] ||SSTL-12 |- |PIN_W5 ||DDR4A_A[10]|| Address [10] ||SSTL-12 |- |PIN_Y5 ||DDR4A_A[11]|| Address [11] ||SSTL-12 |- |PIN_AA9 ||DDR4A_A[12]|| Address [12] ||SSTL-12 |- |PIN_AB7 ||DDR4A_A[13]|| Address [13] ||SSTL-12 |- |PIN_AA7 ||DDR4A_A[14]|| Address [14]/WE_n ||SSTL-12 |- |PIN_AB10 ||DDR4A_A[15]|| Address [15]/CAS_n ||SSTL-12 |- |PIN_AB11 ||DDR4A_A[16]|| Address [16]/RAS_n ||SSTL-12 |- |PIN_Y7 ||DDR4A_BA[0]|| Bank Select [0] ||SSTL-12 |- |PIN_AB9 ||DDR4A_BA[1]|| Bank Select [1] ||SSTL-12 |- |PIN_AA10 ||DDR4A_BG[0]|| Bank Group Select[0] ||SSTL-12 |- |PIN_AE2 ||DDR4A_BG[1]|| Bank Group Select[1] ||SSTL-12 |- |PIN_AD3 ||DDR4A_CK|| Clock p0 ||DIFFERENTIAL 1.2-V SSTL |- |PIN_AD4 ||DDR4A_CK_n|| Clock n0 ||DIFFERENTIAL 1.2-V SSTL |- |PIN_AC2 || DDR4A_CKE|| Clock Enable pin ||SSTL-12 |- |PIN_AE8 ||DDR4A_DQS[0] ||Data Strobe p[0] ||DIFFERENTIAL 1.2-V POD |- |PIN_AF7 ||DDR4A_DQS[1]||Data Strobe p[1] ||DIFFERENTIAL 1.2-V POD |- |PIN_AN1 ||DDR4A_DQS[2]||Data Strobe p[2] ||DIFFERENTIAL 1.2-V POD |- |PIN_AH2 ||DDR4A_DQS[3]||Data Strobe p[3] ||DIFFERENTIAL 1.2-V POD |- |PIN_P1 ||DDR4A_DQS[4]||Data Strobe p[4] ||DIFFERENTIAL 1.2-V POD |- |PIN_J3 ||DDR4A_DQS[5]||Data Strobe p[5] ||DIFFERENTIAL 1.2-V POD |- |PIN_R5 ||DDR4A_DQS[6]||Data Strobe p[6] ||DIFFERENTIAL 1.2-V POD |- |PIN_V9 ||DDR4A_DQS[7]||Data Strobe p[7] ||DIFFERENTIAL 1.2-V POD |- |PIN_V2 ||DDR4A_DQS[8]||Data Strobe p[8] ||DIFFERENTIAL 1.2-V POD |- |PIN_AD8 ||DDR4A_DQS_n[0]|| Data Strobe n[0] ||DIFFERENTIAL 1.2-V POD |- |PIN_AE7 ||DDR4A_DQS_n[1]||Data Strobe n[1] ||DIFFERENTIAL 1.2-V POD |- |PIN_AN2 ||DDR4A_DQS_n[2]|| Data Strobe n[2] ||DIFFERENTIAL 1.2-V POD |- |PIN_AH3 ||DDR4A_DQS_n[3]|| Data Strobe n[3] ||DIFFERENTIAL 1.2-V POD |- |PIN_R1 ||DDR4A_DQS_n[4]||Data Strobe n[4] ||DIFFERENTIAL 1.2-V POD |- |PIN_K3 ||DDR4A_DQS_n[5]|| Data Strobe n[5] ||DIFFERENTIAL 1.2-V POD |- |PIN_R6 ||DDR4A_DQS_n[6]||Data Strobe n[6] ||DIFFERENTIAL 1.2-V POD |- |PIN_W9 ||DDR4A_DQS_n[7]|| Data Strobe n[7] ||DIFFERENTIAL 1.2-V POD |- |PIN_V3 ||DDR4A_DQS_n[8]||Data Strobe n[8] ||DIFFERENTIAL 1.2-V POD |- |PIN_AC11 || DDR4A_DQ[0] ||Data [0] ||1.2-V POD |- |PIN_AD10 || DDR4A_DQ[1]|| Data [1] ||1.2-V POD |- |PIN_AC9 || DDR4A_DQ[2]|| Data [2] ||1.2-V POD |- |PIN_AG7 || DDR4A_DQ[3]|| Data [3] ||1.2-V POD |- |PIN_AD13 || DDR4A_DQ[4]|| Data [4] ||1.2-V POD |- |PIN_AD11 || DDR4A_DQ[5]|| Data [5] ||1.2-V POD |- |PIN_AC8 ||DDR4A_DQ[6]|| Data [6] ||1.2-V POD |- |PIN_AF8 ||DDR4A_DQ[7] ||Data [7] ||1.2-V POD |- |PIN_AE6 || DDR4A_DQ[8]|| Data [8] ||1.2-V POD |- |PIN_AJ6 || DDR4A_DQ[9] ||Data [9] ||1.2-V POD |- |PIN_AG6 ||DDR4A_DQ[10]|| Data [10] ||1.2-V POD |- |PIN_AD6 ||DDR4A_DQ[11] ||Data [11] ||1.2-V POD |- |PIN_AG5 ||DDR4A_DQ[12]||Data [12] ||1.2-V POD |- |PIN_AK5 ||DDR4A_DQ[13]|| Data [13] ||1.2-V POD |- |PIN_AC7 ||DDR4A_DQ[14] ||Data [14] ||1.2-V POD |- |PIN_AH6 ||DDR4A_DQ[15] ||Data [15] ||1.2-V POD |- |PIN_AK1 ||DDR4A_DQ[16]|| Data [16] ||1.2-V POD |- |PIN_AL4 ||DDR4A_DQ[17]|| Data [17] ||1.2-V POD |- |PIN_AJ4 ||DDR4A_DQ[18] ||Data [18] ||1.2-V POD |- |PIN_AM1 ||DDR4A_DQ[19]|| Data [19] ||1.2-V POD |- |PIN_AK3 ||DDR4A_DQ[20]||Data [20] ||1.2-V POD |- |PIN_AL2 ||DDR4A_DQ[21]|| Data [21] ||1.2-V POD |- |PIN_AJ3 ||DDR4A_DQ[22] ||Data [22] ||1.2-V POD |- |PIN_AM2 ||DDR4A_DQ[23]|| Data [23] ||1.2-V POD |- |PIN_AF2 ||DDR4A_DQ[24]|| Data [24] ||1.2-V POD |- |PIN_AH1 ||DDR4A_DQ[25] || Data [25]||1.2-V POD |- |PIN_AG4 ||DDR4A_DQ[26]|| Data [26] ||1.2-V POD |- |PIN_AE5 ||DDR4A_DQ[27]|| Data [27] ||1.2-V POD |- |PIN_AF3 ||DDR4A_DQ[28]|| Data [28] ||1.2-V POD |- |PIN_AH4 ||DDR4A_DQ[29]|| Data [29] ||1.2-V POD |- |PIN_AG1 ||DDR4A_DQ[30]|| Data [30] ||1.2-V POD |- |PIN_AF4 ||DDR4A_DQ[31]|| Data [31] ||1.2-V POD |- |PIN_K1 ||DDR4A_DQ[32] || Data [32]||1.2-V POD |- |PIN_P4 ||DDR4A_DQ[33] || Data [33]||1.2-V POD |- |PIN_N2 ||DDR4A_DQ[34]|| Data [34] ||1.2-V POD |- |PIN_K2 ||DDR4A_DQ[35]|| Data [35] ||1.2-V POD |- |PIN_M2 ||DDR4A_DQ[36]|| Data [36] ||1.2-V POD |- |PIN_P3 ||DDR4A_DQ[37]|| Data [37] ||1.2-V POD |- |PIN_N1 ||DDR4A_DQ[38] || Data [38]||1.2-V POD |- |PIN_J1 ||DDR4A_DQ[39] || Data [39]||1.2-V POD |- |PIN_N3 ||DDR4A_DQ[40]|| Data [40] ||1.2-V POD |- |PIN_P5 ||DDR4A_DQ[41]|| Data [41] ||1.2-V POD |- |PIN_M5 ||DDR4A_DQ[42]|| Data [42] ||1.2-V POD |- |PIN_R2 ||DDR4A_DQ[43]|| Data [43] ||1.2-V POD |- |PIN_N4 ||DDR4A_DQ[44]|| Data [44] ||1.2-V POD |- |PIN_P6 ||DDR4A_DQ[45]|| Data [45] ||1.2-V POD |- |PIN_L4 ||DDR4A_DQ[46]|| Data [46] ||1.2-V POD |- |PIN_R3 ||DDR4A_DQ[47]|| Data [47] ||1.2-V POD |- |PIN_V6 ||DDR4A_DQ[48]|| Data [48] ||1.2-V POD |- |PIN_T7 ||DDR4A_DQ[49]|| Data [49] ||1.2-V POD |- |PIN_U5 ||DDR4A_DQ[50]|| Data [50] ||1.2-V POD |- |PIN_U7 ||DDR4A_DQ[51]|| Data [51] ||1.2-V POD |- |PIN_T4 ||DDR4A_DQ[52] ||Data [52] ||1.2-V POD |- |PIN_W6 ||DDR4A_DQ[53]|| Data [53] ||1.2-V POD |- |PIN_T3 ||DDR4A_DQ[54] || Data [54]||1.2-V POD |- |PIN_U6 ||DDR4A_DQ[55]|| Data [55] ||1.2-V POD |- |PIN_W8 ||DDR4A_DQ[56]|| Data [56] ||1.2-V POD |- |PIN_Y12 ||DDR4A_DQ[57]|| Data [57] ||1.2-V POD |- |PIN_Y11 ||DDR4A_DQ[58]|| Data [58] ||1.2-V POD |- |PIN_W10 ||DDR4A_DQ[59]|| Data [59] ||1.2-V POD |- |PIN_Y13 ||DDR4A_DQ[60]|| Data [60] ||1.2-V POD |- |PIN_Y8 ||DDR4A_DQ[61] || Data [61] ||1.2-V POD |- |PIN_Y10 ||DDR4A_DQ[62]|| Data [62] ||1.2-V POD |- |PIN_W11 ||DDR4A_DQ[63]|| Data [63] ||1.2-V POD |- |PIN_V1 ||DDR4A_DQ[64]|| Data [64] ||1.2-V POD |- |PIN_Y1 ||DDR4A_DQ[65]|| Data [65] ||1.2-V POD |- |PIN_W3 ||DDR4A_DQ[66]|| Data [66] ||1.2-V POD |- |PIN_W1 ||DDR4A_DQ[67]|| Data [67] ||1.2-V POD |- |PIN_Y3 ||DDR4A_DQ[68]|| Data [68] ||1.2-V POD |- |PIN_W4 ||DDR4A_DQ[69]|| Data [69] ||1.2-V POD |- |PIN_U1 ||DDR4A_DQ[70] || Data [70]||1.2-V POD |- |PIN_U2 ||DDR4A_DQ[71]|| Data [71] ||1.2-V POD |- |PIN_AD9 ||DDR4A_DBI_n[0]|| Data Bus Inversion [0] ||1.2-V POD |- |PIN_AJ5 ||DDR4A_DBI_n[1]|| Data Bus Inversion [1] ||1.2-V POD |- |PIN_AK2 ||DDR4A_DBI_n[2]|| Data Bus Inversion [2] ||1.2-V POD |- |PIN_AG2 ||DDR4A_DBI_n[3]|| Data Bus Inversion [3] ||1.2-V POD |- |PIN_L2 ||DDR4A_DBI_n[4]|| Data Bus Inversion [4] ||1.2-V POD |- |PIN_L3 ||DDR4A_DBI_n[5]|| Data Bus Inversion [5] ||1.2-V POD |- |PIN_U4 ||DDR4A_DBI_n[6]|| Data Bus Inversion [6] ||1.2-V POD |- |PIN_V8 ||DDR4A_DBI_n[7]|| Data Bus Inversion [7] ||1.2-V POD |- |PIN_V4 ||DDR4A_DBI_n[8]|| Data Bus Inversion [8] ||1.2-V POD |- |PIN_AE1 ||DDR4A_CS_n|| Chip Select ||SSTL-12 |- |PIN_AE3 ||DDR4A_RESET_n ||Chip Reset ||1.2 V |- |PIN_AC3 ||DDR4A_ODT|| On Die Termination ||SSTL-12 |- |PIN_AC6 || DDR4A_PAR|| Command and Address Parity Input ||SSTL-12 |- |PIN_AC12 ||DDR4A_ALERT_n|| Register ALERT_n output ||SSTL-12 |- |PIN_AD1 ||DDR4A_ACT_n|| Activation Command Input ||SSTL-12 |- |PIN_T5 ||DDR4A_EVENT_n|| Chip Temperature Event ||1.2 V |- |PIN_AA8 ||DDR4A_RZQ|| External reference ball for output drive calibration ||1.2 V |} ==HDMI== The development board provides High Performance HDMI Transmitter via the devices SN75DP159 which incorporates HDMI v2.0a features, including Ultra HD video and HDTV support. The SN75DP159 is controlled via a serial I2C bus interface, which is connected to pins on the Arria 10 SoC FPGA.Figure 4-9 shows the connections between the HDMI port and Arria 10 SoC FPGA. The pin assignment associated to HDMI port is listed in Table 4-9 .<br/><br/> :::[[File:HDMI-de10-ad.jpg|500px]] ::::Figure 4-9 Connections between the HDMI port and Arria 10 SoC FPGA ::::Table 4-9 HDMI port Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name!!FPGA Pin Number!!Description!!I/O Standard |- |HDMI_REFCLK_p||PIN_Y31||HDMI reference clock||LVDS |- |HDMI_TX_CLK_p||PIN_V39||HDMI transmit clock||HSSI DIFFERENTIAL I/O |- |HDMI_TX_CLK_n || PIN_V38 || HDMI transmit clock ||HSSI DIFFERENTIAL I/O |- |HDMI_TX_D_p0||PIN_U37||HDMI transmit data p0 ||HSSI DIFFERENTIAL I/O |- |HDMI_TX_D_p1||PIN_T39||HDMI transmit data p1 ||HSSI DIFFERENTIAL I/O |- |HDMI_TX_D_p2||PIN_R37||HDMI transmit data p2||HSSI DIFFERENTIAL I/O |- |HDMI_TX_D_n0 || PIN_U36 || HDMI transmit data n0 ||HSSI DIFFERENTIAL I/O |- |HDMI_TX_D_n1 ||PIN_T38 || HDMI transmit data n1 ||HSSI DIFFERENTIAL I/O |- |HDMI_TX_D_n2 ||PIN_R36 || HDMI transmit data n2 ||HSSI DIFFERENTIAL I/O |- |HDMI_PRE_SEL || PIN_E13 || ||3.3V |- |HDMI_SLEW_CTL || PIN_E12 || ||3.3V |- |HDMI_IC_I2C_EN || PIN_E14 || ||3.3V |- |HDMI_EQ_SEL_A0 || PIN_C14 || ||3.3V |- |HDMI_SEL_A1 || PIN_C15 || ||3.3V |} ==Display Port== The DE10-Advanced board includes a DisplayPort connector. We plan to support DisplayPort both source and sink port on USB Type-C connector：support DisplayPort 1.2a spec and data rate up to 5.4Gbps per lane,4 lanes in total.<br/> ::Table 4-10 Display Port Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |DP_REFCLK_p ||PIN_AM31||Display reference clock ||LVDS |- |DP_TX_p[0] ||PIN_AW37||Transmitter data p0 ||HSSI DIFFERENTIAL I/O |- |DP_TX_p[1] ||PIN_AV39||Transmitter data p1 ||HSSI DIFFERENTIAL I/O |- |DP_TX_p[2] ||PIN_AU37||Transmitter data p2 ||HSSI DIFFERENTIAL I/O |- |DP_TX_p[3] ||PIN_AT39||Transmitter data p3 ||HSSI DIFFERENTIAL I/O |- |DP_RX_p[0] ||PIN_AV35||Receiver data p0 ||HSSI DIFFERENTIAL I/O |- |DP_RX_p[1] ||PIN_AT35||Receiver data p1 ||HSSI DIFFERENTIAL I/O |- |DP_RX_p[2] ||PIN_AN33||Receiver data p2 ||HSSI DIFFERENTIAL I/O |- |DP_RX_p[3] ||PIN_AP35||Receiver data p3 ||HSSI DIFFERENTIAL I/O |- |DP_AUX_p ||PIN_AM22||Display port AUX port ||1.8V |} ==FMC Connector== The FPGA Mezzanine Card (FMC) interface provides a mechanism to extend the peripheral-set of an FPGA host board by means of add-on daughter cards, which can address today’s high speed signaling requirements as well as low-speed device interface support.The FMC interfaces support JTAG,clock outputs and inputs,high-speed serial I/O (transceivers),and single-ended or differential signaling.<br/> There is one FMC connector on the DE10-Advanced board,it is a High Pin Count (HPC) size of connector,The HPC connector on DE10-Advanced board can provides 172 user-define,single-ended signals (include clock signals) and 10 serial transceiver pairs.Figure 4-10 is the FMC connector on DE10-Advanced board<br/> ::[[File:FMC.jpg]] :::::Figure 4-10 FMC connector on DE10-Advanced board :::::::::Table 4-11 FMC Connector Pin Assignments, Signal Names and Functions :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |FMC_CLK2_BIDIR_p|| PIN_AW18|| FMC bidirection Clock signal ||1.8 V |- |FMC_CLK2_BIDIR_n|| PIN_AV17||FMC bidirection Clock signal ||1.8 V |- |FMC_CLK3_BIDIR_p|| PIN_C1|| FMC bidirection Clock signal||1.8 V |- |FMC_CLK3_BIDIR_n|| PIN_D1|| FMC bidirection Clock signal ||1.8 V |- |FMC_CLK_M2C_p[0]|| PIN_K5|| Clock input 0 ||1.8 V |- |FMC_CLK_M2C_p[1]|| PIN_AW14|| Clock input 1 ||1.8 V |- |FMC_CLK_M2C_n[0]|| PIN_L5|| Clock input 0 ||1.8 V |- |FMC_CLK_M2C_n[1]|| PIN_AW15||Clock input 1 ||1.8 V |- |FMC_HA_p[0]|| PIN_K12|| FMC data bus ||1.8 V |- |FMC_HA_p[1]|| PIN_M12|| FMC data bus ||1.8 V |- |FMC_HA_p[2]|| PIN_D10|| FMC data bus ||1.8 V |- |FMC_HA_p[3]|| PIN_E12|| FMC data bus ||1.8 V |- |FMC_HA_p[4]|| PIN_H13|| FMC data bus ||1.8 V |- |FMC_HA_p[5]|| PIN_J11|| FMC data bus ||1.8 V |- |FMC_HA_p[6]|| PIN_N13|| FMC data bus ||1.8 V |- |FMC_HA_p[7]|| PIN_L13|| FMC data bus ||1.8 V |- |FMC_HA_p[8]|| PIN_J14|| FMC data bus ||1.8 V |- |FMC_HA_p[9]|| PIN_F13||FMC data bus ||1.8 V |- |FMC_HA_p[10]|| PIN_D13|| FMC data bus ||1.8 V |- |FMC_HA_p[11]|| PIN_G14||FMC data bus ||1.8 V |- |FMC_HA_p[12]|| PIN_A10||FMC data bus ||1.8 V |- |FMC_HA_p[13]|| PIN_G12||FMC data bus ||1.8 V |- |FMC_HA_p[14]|| PIN_A12||FMC data bus ||1.8 V |- |FMC_HA_p[15]|| PIN_A7|| FMC data bus||1.8 V |- |FMC_HA_p[16]|| PIN_A9|| FMC data bus ||1.8 V |- |FMC_HA_p[17]|| PIN_C12|| FMC data bus ||1.8 V |- |FMC_HA_p[18]|| PIN_B11|| FMC data bus ||1.8 V |- |FMC_HA_p[19]|| PIN_M7|| FMC data bus||1.8 V |- |FMC_HA_p[20]|| PIN_F10|| FMC data bus ||1.8 V |- |FMC_HA_p[21]|| PIN_C9|| FMC data bus ||1.8 V |- |FMC_HA_p[22]|| PIN_C8|| FMC data bus ||1.8 V |- |FMC_HA_p[23]|| PIN_G11|| FMC data bus ||1.8 V |- |FMC_HA_n[0]|| PIN_L12|| FMC data bus ||1.8 V |- |FMC_HA_n[1]|| PIN_N12|| FMC data bus ||1.8 V |- |FMC_HA_n[2]|| PIN_E10|| FMC data bus ||1.8 V |- |FMC_HA_n[3]|| PIN_F12|| FMC data bus ||1.8 V |- |FMC_HA_n[4]|| PIN_J13|| FMC data bus ||1.8 V |- |FMC_HA_n[5]|| PIN_K11||FMC data bus ||1.8 V |- |FMC_HA_n[6]|| PIN_P13|| FMC data bus ||1.8 V |- |FMC_HA_n[7]|| PIN_L14|| FMC data bus ||1.8 V |- |FMC_HA_n[8]|| PIN_K13|| FMC data bus ||1.8 V |- |FMC_HA_n[9]|| PIN_F14|| FMC data bus ||1.8 V |- |FMC_HA_n[10]|| PIN_E13|| FMC data bus ||1.8 V |- |FMC_HA_n[11]|| PIN_H14|| FMC data bus ||1.8 V |- |FMC_HA_n[12]|| PIN_B10|| FMC data bus ||1.8 V |- |FMC_HA_n[13]|| PIN_H12||FMC data bus ||1.8 V |- |FMC_HA_n[14]|| PIN_B12|| FMC data bus ||1.8 V |- |FMC_HA_n[15]|| PIN_A8|| FMC data bus ||1.8 V |- |FMC_HA_n[16]|| PIN_B9|| FMC data bus ||1.8 V |- |FMC_HA_n[17]|| PIN_C13|| FMC data bus ||1.8 V |- |FMC_HA_n[18]|| PIN_C11|| FMC data bus ||1.8 V |- |FMC_HA_n[19]|| PIN_N7|| FMC data bus ||1.8 V |- |FMC_HA_n[20]|| PIN_G10||FMC data bus ||1.8 V |- |FMC_HA_n[21]|| PIN_D9|| FMC data bus ||1.8 V |- |FMC_HA_n[22]|| PIN_D8|| FMC data bus ||1.8 V |- |FMC_HA_n[23]|| PIN_H11||FMC data bus ||1.8 V |- |FMC_HB_p[0]|| PIN_E1|| FMC data bus ||1.8 V |- |FMC_HB_p[1]|| PIN_G4|| FMC data bus ||1.8 V |- |FMC_HB_p[2]|| PIN_N8||FMC data bus ||1.8 V |- |FMC_HB_p[3]|| PIN_J4|| FMC data bus ||1.8 V |- |FMC_HB_p[4]|| PIN_H2|| FMC data bus ||1.8 V |- |FMC_HB_p[5]|| PIN_G5|| FMC data bus ||1.8 V |- |FMC_HB_p[6]|| PIN_D3|| FMC data bus ||1.8 V |- |FMC_HB_p[7]|| PIN_A2|| FMC data bus ||1.8 V |- |FMC_HB_p[8]|| PIN_B1|| FMC data bus ||1.8 V |- |FMC_HB_p[9]|| PIN_AT13||FMC data bus ||1.8 V |- |FMC_HB_p[10]|| PIN_AM17||FMC data bus ||1.8 V |- |FMC_HB_p[11]|| PIN_AJ16|| FMC data bus ||1.8 V |- |FMC_HB_p[12]|| PIN_AW13||FMC data bus ||1.8 V |- |FMC_HB_p[13]|| PIN_AV14|| FMC data bus ||1.8 V |- |FMC_HB_p[14]|| PIN_AP14||FMC data bus ||1.8 V |- |FMC_HB_p[15]|| PIN_AK16|| FMC data bus ||1.8 V |- |FMC_HB_p[16]|| PIN_AU16|| FMC data bus ||1.8 V |- |FMC_HB_p[17]|| PIN_AT17|| FMC data bus ||1.8 V |- |FMC_HB_p[18]|| PIN_AM15|| FMC data bus ||1.8 V |- |FMC_HB_p[19]|| PIN_AR15||FMC data bus ||1.8 V |- |FMC_HB_p[20]|| PIN_AP16|| FMC data bus ||1.8 V |- |FMC_HB_p[21]|| PIN_AV18||FMC data bus ||1.8 V |- |FMC_HB_n[0]|| PIN_E2|| FMC data bus ||1.8 V |- |FMC_HB_n[1]|| PIN_H4|| FMC data bus ||1.8 V |- |FMC_HB_n[2]|| PIN_P8|| FMC data bus ||1.8 V |- |FMC_HB_n[3]|| PIN_J5||FMC data bus ||1.8 V |- |FMC_HB_n[4]|| PIN_H3||FMC data bus ||1.8 V |- |FMC_HB_n[5]|| PIN_H6|| FMC data bus ||1.8 V |- |FMC_HB_n[6]|| PIN_E3|| FMC data bus ||1.8 V |- |FMC_HB_n[7]|| PIN_B2|| FMC data bus ||1.8 V |- |FMC_HB_n[8]|| PIN_C2|| FMC data bus ||1.8 V |- |FMC_HB_n[9]|| PIN_AT14||FMC data bus ||1.8 V |- |FMC_HB_n[10]|| PIN_AL17|| FMC data bus ||1.8 V |- |FMC_HB_n[11]|| PIN_AH16|| FMC data bus ||1.8 V |- |FMC_HB_n[12]|| PIN_AV13|| FMC data bus ||1.8 V |- |FMC_HB_n[13]|| PIN_AU14||FMC data bus ||1.8 V |- |FMC_HB_n[14]|| PIN_AP15||FMC data bus ||1.8 V |- |FMC_HB_n[15]|| PIN_AK17|| FMC data bus ||1.8 V |- |FMC_HB_n[16]|| PIN_AU17|| FMC data bus ||1.8 V |- |FMC_HB_n[17]|| PIN_AT18|| FMC data bus ||1.8 V |- |FMC_HB_n[18]|| PIN_AM16|| FMC data bus ||1.8 V |- |FMC_HB_n[19]|| PIN_AR16|| FMC data bus ||1.8 V |- |FMC_HB_n[20]|| PIN_AN16|| FMC data bus ||1.8 V |- |FMC_HB_n[21]|| PIN_AV19|| FMC data bus ||1.8 V |- |FMC_LA_p[0]|| PIN_A3||FMC data bus ||1.8 V |- |FMC_LA_p[1]|| PIN_B4|| FMC data bus ||1.8 V |- |FMC_LA_p[2]|| PIN_T9|| FMC data bus ||1.8 V |- |FMC_LA_p[3]|| PIN_M10||FMC data bus ||1.8 V |- |FMC_LA_p[4]|| PIN_U9|| FMC data bus||1.8 V |- |FMC_LA_p[5]|| PIN_J10|| FMC data bus ||1.8 V |- |FMC_LA_p[6]|| PIN_H8|| FMC data bus ||1.8 V |- |FMC_LA_p[7]|| PIN_L9|| FMC data bus ||1.8 V |- |FMC_LA_p[8]|| PIN_M9|| FMC data bus ||1.8 V |- |FMC_LA_p[9]|| PIN_G6|| FMC data bus ||1.8 V |- |FMC_LA_p[10]|| PIN_E8|| FMC data bus ||1.8 V |- |FMC_LA_p[11]|| PIN_B6|| FMC data bus ||1.8 V |- |FMC_LA_p[12]|| PIN_A5|| FMC data bus ||1.8 V |- |FMC_LA_p[13]|| PIN_D5|| FMC data bus ||1.8 V |- |FMC_LA_p[14]|| PIN_B7|| FMC data bus ||1.8 V |- |FMC_LA_p[15]|| PIN_E6|| FMC data bus ||1.8 V |- |FMC_LA_p[16]|| PIN_E5|| FMC data bus ||1.8 V |- |FMC_LA_p[17]|| PIN_F9|| FMC data bus ||1.8 V |- |FMC_LA_p[18]|| PIN_K8|| FMC data bus ||1.8 V |- |FMC_LA_p[19]|| PIN_R8|| FMC data bus ||1.8 V |- |FMC_LA_p[20]|| PIN_F7|| FMC data bus ||1.8 V |- |FMC_LA_p[21]|| PIN_C4|| FMC data bus ||1.8 V |- |FMC_LA_p[22]|| PIN_U11|| FMC data bus ||1.8 V |- |FMC_LA_p[23]|| PIN_V11|| FMC data bus ||1.8 V |- |FMC_LA_p[24]|| PIN_R11|| FMC data bus ||1.8 V |- |FMC_LA_p[25]|| PIN_F2|| FMC data bus ||1.8 V |- |FMC_LA_p[26]|| PIN_R7|| FMC data bus ||1.8 V |- |FMC_LA_p[27]|| PIN_T12|| FMC data bus ||1.8 V |- |FMC_LA_p[28]|| PIN_J6|| FMC data bus ||1.8 V |- |FMC_LA_p[29]|| PIN_G1|| FMC data bus ||1.8 V |- |FMC_LA_p[30]|| PIN_K7||FMC data bus ||1.8 V |- |FMC_LA_p[31]|| PIN_P10|| FMC data bus ||1.8 V |- |FMC_LA_p[32]|| PIN_M6|| FMC data bus ||1.8 V |- |FMC_LA_p[33]|| PIN_N11|| FMC data bus ||1.8 V |- |FMC_LA_n[0]|| PIN_A4|| FMC data bus ||1.8 V |- |FMC_LA_n[1]|| PIN_C3|| FMC data bus ||1.8 V |- |FMC_LA_n[2]|| PIN_T10|| FMC data bus ||1.8 V |- |FMC_LA_n[3]|| PIN_M11||FMC data bus ||1.8 V |- |FMC_LA_n[4]|| PIN_U10|| FMC data bus ||1.8 V |- |FMC_LA_n[5]|| PIN_K10|| FMC data bus ||1.8 V |- |FMC_LA_n[6]|| PIN_J8|| FMC data bus ||1.8 V |- |FMC_LA_n[7]|| PIN_L10|| FMC data bus ||1.8 V |- |FMC_LA_n[8]|| PIN_N9|| FMC data bus ||1.8 V |- |FMC_LA_n[9]|| PIN_H7|| FMC data bus ||1.8 V |- |FMC_LA_n[10]|| PIN_F8|| FMC data bus ||1.8 V |- |FMC_LA_n[11]|| PIN_C6|| FMC data bus ||1.8 V |- |FMC_LA_n[12]|| PIN_B5|| FMC data bus ||1.8 V |- |FMC_LA_n[13]|| PIN_D6|| FMC data bus ||1.8 V |- |FMC_LA_n[14]|| PIN_C7|| FMC data bus ||1.8 V |- |FMC_LA_n[15]|| PIN_E7|| FMC data bus ||1.8 V |- |FMC_LA_n[16]|| PIN_F5|| FMC data bus ||1.8 V |- |FMC_LA_n[17]|| PIN_G9|| FMC data bus ||1.8 V |- |FMC_LA_n[18]|| PIN_L8|| FMC data bus ||1.8 V |- |FMC_LA_n[19]|| PIN_P9|| FMC data bus ||1.8 V |- |FMC_LA_n[20]|| PIN_G7|| FMC data bus ||1.8 V |- |FMC_LA_n[21]|| PIN_D4|| FMC data bus ||1.8 V |- |FMC_LA_n[22]|| PIN_U12|| FMC data bus ||1.8 V |- |FMC_LA_n[23]|| PIN_V12|| FMC data bus ||1.8 V |- |FMC_LA_n[24]|| PIN_R12|| FMC data bus ||1.8 V |- |FMC_LA_n[25]|| PIN_G2|| FMC data bus ||1.8 V |- |FMC_LA_n[26]|| PIN_T8|| FMC data bus ||1.8 V |- |FMC_LA_n[27]|| PIN_T13|| FMC data bus ||1.8 V |- |FMC_LA_n[28]|| PIN_K6|| FMC data bus ||1.8 V |- |FMC_LA_n[29]|| PIN_H1|| FMC data bus ||1.8 V |- |FMC_LA_n[30]|| PIN_L7|| FMC data bus ||1.8 V |- |FMC_LA_n[31]|| PIN_R10|| FMC data bus ||1.8 V |- |FMC_LA_n[32]|| PIN_N6|| FMC data bus ||1.8 V |- |FMC_LA_n[33]|| PIN_P11|| FMC data bus ||1.8 V |- |FMC_GBTCLK_M2C_p[0]|| PIN_P31|| LVDS input from the installed FMC card to dedicated reference clock inputs ||LVDS |- |FMC_GBTCLK_M2C_p[1]|| PIN_K31|| LVDS input from the installed FMC card to dedicated reference clock inputs ||LVDS |- |FMC_REFCLK_p|| PIN_T31|| Reference Clock ||LVDS |- |FMC_DP_C2M_p[0]|| PIN_M39|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[1]|| PIN_L37|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[2]|| PIN_K39|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[3]|| PIN_J37|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[4]|| PIN_H39|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[5]|| PIN_G37|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[6]|| PIN_F39|| Transmit channel||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[7]|| PIN_E37|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[8]|| PIN_D39|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_C2M_p[9]|| PIN_C37|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[0]|| PIN_P35|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[1]|| PIN_R33|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[2]|| PIN_M35||Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[3]|| PIN_N33|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[4]|| PIN_K35|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[5]|| PIN_L33|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[6]|| PIN_H35|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[7]|| PIN_J33|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[8]|| PIN_F35|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_DP_M2C_p[9]||PIN_G33|| Transmit channel ||HSSI DIFFERENTIAL I/O |- |FMC_GA[0]||PIN_E11|| FMC geographical address 0 ||1.8 V |- |FMC_GA[1]||PIN_AL18||FMC geographical address 1 ||1.8 V |- |FMC_SCL||PIN_J9||Management serial clock line ||1.8 V |- |FMC_SDA||PIN_F4|| Management serial data line ||1.8 V |} ==Temperature Sensor,Fan Control and Power Monitor== The FPGA board is equipped with a temperature sensor, TMP441AIDCNT, which provides temperature sensing.This functions is accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Arria 10 SoC device. The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two-wire SMBus, which is connected to the Arria 10 SoC FPGA. In addition, the 7-bit POR slave address for this sensor is set to‘0011100b'. A 3-pin +12V fan located on J22 of the FPGA board is intended to reduce the temperature of the FPGA.The board is equipped with a Fan-Speed regulator and monitor MAX6650 with an I2C/SMBus interfaces,Users regulate and monitor the speed of fan depending on the measured system temperature.<br/> The DE10-Advanced has implemented a power monitor chip to monitor the board input power voltage and current.Figure 4-10 shows the connection between the power monitor chip and the Arria 10 SoC FPGA.The power monitor chip monitors both shunt voltage drops and board input power voltage allows user to monitor the total board power consumption. Programmable calibration value,conversion times,and averaging,combined with an internal multiplier,enable direct readouts of current in amperes and power in watts.Note that,the temperature sensor,fan control and power monitor share the same I2C/SMBUS.<br/> [[File:Power monitor.jpg|600px]] <br/>Figure 4-10 Connections between the temperature sensor/fan control/power monitor and the Arria 10 SoC FPGA ::Table 4-12 Temperature Sensor and Fan Speed Control Pin Assignments,Schematic Signal Names and Functions :{| class="wikitable" |- !Schematic Signal Name !!Description !!I/O Standard !!Arria 10 SoC Pin Number |- |TEMPDIODEp || Positive pin of temperature diode in Arria 10 || -- ||B15 |- |TEMPDIODEn || Negative pin of temperature diode in Arria 10 || -- ||B14 |- |FPGA_I2C_SCL || SMBus clock ||1.8V ||M1 |- |FPGA_I2C_SDA ||SMBus data ||1.8V ||M4 |- |FAN_ALERT || Active-low ALERT input ||1.8V ||E25 |} =Chapter 5 HPS Fabric Component= This section introduces the interfaces connected to the HPS section of the Arria 10 SoC FPGA. Users can access these interfaces via the HPS processor. ==User Push-buttons and LEDs== Similar to the FPGA, the HPS also has its set of switches, buttons, LEDs, and other interfaces connected exclusively. Users can control these interfaces to monitor the status of HPS.<br/> Table 5-1 gives the pin assignment of all the LEDs, switches and push-buttons.<br/> :Table 5-1 Pin Assignment of LEDs, Switches and Push-buttons :{| class="wikitable" |- !Signal Name !!HPS Pin Number !!Function !!I/O Standard |- |HPS_KEY ||PIN_A29||I/O ||1.8 V |- |HPS_LED ||PIN_D29||I/O ||1.8 V |} ==Gigabit Ethernet== The board supports Gigabit Ethernet transfer by an external Micrel KSZ9031RNX PHY chip and HPS Ethernet MAC function. The KSZ9031RNX chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver also supports RGMII MAC interface. Figure 5-1 shows the connections between the HPS, Gigabit Ethernet PHY, and RJ-45 connector. The pin assignment associated with Gigabit Ethernet interface is listed in Table 5-2. More information about the KSZ9031RNX PHY chip and its datasheet, as well as the application notes, is available on the manufacturer’s website.<br/> :::[[File:HPSETH.jpg|700px]] ::::::::::Figure 5-1 Connections between the HPS and Gigabit Ethernet ::::::Table 5-2 Pin Assignment of Gigabit Ethernet PHY :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |HPS_ENET_GTX_CLK ||PIN_F25||GMII Transmit Clock ||1.8V |- |HPS_ENET_MDC ||PIN_D24||Management Data Clock Reference ||1.8V |- |HPS_ENET_MDIO ||PIN_C24||Management Data ||1.8V |- |HPS_ENET_RX_CLK ||PIN_K22||GMII and MII receive clock ||1.8V |- |HPS_ENET_RX_DATA[0] ||PIN_H23||GMII and MII receive data[0] ||1.8V |- |HPS_ENET_RX_DATA[1] ||PIN_J23||GMII and MII receive data[1] ||1.8V |- |HPS_ENET_RX_DATA[2] ||PIN_F24||GMII and MII receive data[2] ||1.8V |- |HPS_ENET_RX_DATA[3] ||PIN_G24||GMII and MII receive data[3] ||1.8V |- |HPS_ENET_RX_DV ||PIN_L22|| GMII and MII receive data valid ||1.8V |- |HPS_ENET_TX_DATA[0] ||PIN_H24||MII transmit data[0] ||1.8V |- |HPS_ENET_TX_DATA[1] ||PIN_J24||MII transmit data[1] ||1.8V |- |HPS_ENET_TX_DATA[2] ||PIN_M22||MII transmit data[2] ||1.8V |- |HPS_ENET_TX_DATA[3] ||PIN_M21||MII transmit data[3] ||1.8V |- |HPS_ENET_TX_EN ||PIN_G25||GMII and MII transmit enable ||1.8V |- |HPS_ENET_RESET_N ||PIN_H3||Hardware Reset Signal ||1.8V |- |HPS_ENET_INT_N ||PIN_G5||Interrupt Open Drain Output||1.8V |} There are four LEDs, two green LEDs(LEDG) and two yellow LEDs(LEDY), which represent the status of Ethernet PHY (KSZ9031RNX). The LED control signals are connected to the LEDs on the RJ45 connector. The state and definition of LEDG and LEDY are listed in Table 5-3. For instance, the connection from board to Gigabit Ethernet is established once the LEDG lights on. :::Table 5-3 State and Definition of LED Mode Pins :{| class="wikitable" |- ! colspan="2" style="text-align: center;" | LED (State) !!colspan="2" style="text-align: center;" | LED (Definition) !!rowspan="2" |Link /Activity |- !LEDG !!LEDY !!LEDG !!LEDY |- |H ||H ||OFF ||OFF ||Link off |- |L ||H ||ON ||OFF ||1000 Link / No Activity |- |Toggle ||H ||Blinking ||OFF ||1000 Link / Activity (RX, TX) |- |H ||L ||OFF ||ON ||100 Link / No Activity |- |H ||Toggle ||OFF ||Blinking ||100 Link / Activity (RX, TX) |- |L ||L ||ON ||ON ||10 Link/ No Activity |- |Toggle ||Toggle ||Blinking ||Blinking ||10 Link / Activity (RX, TX) |} ==UART to USB== The board has one UART interface connected for communication with the HPS. This interface doesn’t support HW flow control signals. The physical interface is implemented by UART-USB onboard bridge from a FT232R chip to the host with an USB Mini-B connector. More information about the chip is available on the manufacturer’s website, or in the directory \Datasheets\UART TO USB of DE10-Advanced system CD. Figure 5-2 shows the connections between the HPS, FT232R chip, and the USB Mini-B connector. Table 5-4 lists the pin assignment of UART interface connected to the HPS.<br/> :::[[File:De10-ad-UART.jpg|600px]] ::::::Figure 5-2 Connections between the HPS and USB Mini-B connector ::::Table 5-4 Pin Assignment of UART Interface :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |USBFX3_UART_TX ||PIN_AP23||HPS UART Transmitter ||1.8V |- |USBFX3_UART_RX ||PIN_AU27||HPS UART Receiver ||1.8V |} ==Micro SD Card Socket== The board supports Micro SD card interface with x4 data lines. It serves not only an external storage for the HPS, but also an alternative boot option for DE10-Standard board. Figure 5-3 shows signals connected between the HPS and Micro SD card socket. Table 5-5 lists the pin assignment of Micro SD card socket to the HPS.<br/> ::::[[File:DE10-AD-SD.jpg|600px]] ::::::::Figure 5-3 Connections between the FPGA and SD card socket ::::Table 5-5 Pin Assignment of Micro SD Card Socket :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |HPS_SD_CLK || ||HPS SD Clock || |- |HPS_SD_CMD || ||HPS SD Command Line || |- |HPS_SD_DATA[0] || ||HPS SD Data[0] || |- |HPS_SD_DATA[1] || ||HPS SD Data[1] || |- |HPS_SD_DATA[2] || ||HPS SD Data[2] || |- |HPS_SD_DATA[3] || ||HPS SD Data[3] || |} ==USB OTG== The board has one USB 2.0 type-A port with a SMSC USB3320 controller. The SMSC USB3320 device in 32-pin QFN RoHS Compliant package. This device supports UTMI+ Low Pin Interface (ULPI), which communicates with the USB 2.0 controller in HPS. The PHY operates in Host mode by connecting the ID pin of USB3320 to ground. When operating in Host mode, the device is powered by the USB type-A port. Figure 5-4 shows the connections of USB PTG PHY to the HPS. Table 5-6 lists the pin assignment of USB OTG PHY to the HPS.<br/> ::::[[File:DE10-AD-OTG.jpg|700px]] ::::::::Figure 5-4 Connections between the HPS and USB OTG PHY ::::::Table 5-6 Pin Assignment of USB OTG PHY :{| class="wikitable" |- !Signal Name !!FPGA Pin Number !!Description !!I/O Standard |- |HPS_USB_CLKOUT || PIN_L25 || 60MHz Reference Clock Output ||1.8V |- |HPS_USB_DATA[0] ||PIN_K25 || HPS USB_DATA[0] ||1.8V |- |HPS_USB_DATA[1] ||PIN_G26 || HPS USB_DATA[1]||1.8V |- |HPS_USB_DATA[2] || PIN_E27 || HPS USB_DATA[2]||1.8V |- |HPS_USB_DATA[3] ||PIN_F27 || HPS USB_DATA[3]||1.8V |- |HPS_USB_DATA[4] || PIN_L24 || HPS USB_DATA[4] ||1.8V |- |HPS_USB_DATA[5] ||PIN_M24 ||HPS USB_DATA[5] ||1.8V |- |HPS_USB_DATA[6] ||PIN_K23 || HPS USB_DATA[6]||1.8V |- |HPS_USB_DATA[7] || PIN_L23 ||HPS USB_DATA[7] ||1.8V |- |HPS_USB_DIR || PIN_J25 ||Direction of the Data Bus ||1.8V |- |HPS_USB_NXT || PIN_H26 ||Direction of the Data Bus ||1.8V |- |HPS_USB_STP || PIN_M25 || Stop Data Stream on the Bus ||1.8V |- |HPS_USB_RESET ||PIN_L3 ||HPS USB PHY Reset || 1.8V |} =Chapter 6 System Clocks= The DE10-Advance development kit contains five types of clock sources to provide the clocks to the FPGA.They are: *25MHz on-board clock oscillator *25MHz oscillator for FPGA Ethernet clock *100MHz oscillator for User-supplied configuration clock *SMA connectors for external clock input/output *Si5350 programmable oscillator for FPGA configuration & HPS clock resources *CDCM6208 clock generator *Six LMK61E2 programmable oscillators Below Figure 6-1 illustrates the DE10-Advanced clock circuitry.And Figure 6-2 shows the default settings for the programmable clock generator and Oscillators. :::[[File:System clock.jpg|500px]] :::::Figure 6-1 DE10-Advanced Clock Circuitry Block Diagram :::[[File:Clock.jpg|600px]] ::::::::::Figure 6-2 Clock Generation =Chapter 7 Power and Reset= This chapter describe DE10-Advanced board power source and reset. ==Power Supply== The DE10-Advanced board features with an 12V DC input power connector and an USB Type-C connector.The power supply can be either DC power adapter or USB Type-C power supply.Table 7-1 lists the power supply for the DE10-Advanced board. :Table 7-1 Power supply for the DE10-Advanced board :{| class="wikitable" |- !Source !!Supply voltage !!Current |- |DC Adapter ||12V||10A |- | rowspan="2" |USB Type-C power supply ||12V||-- |- ||20V||-- |} In addition,some notebooks have USB Type-C connector and the power is big enough (at least 60W),it can drive this DE10-Advanced board. ==Power Tree== Figure 7-1 shows the power tree on the DE10-Advanced development board,which reflects the power consumption for each part and sharing in the currents.<br/> [[File:Power tree.jpg|700px]] :::::::::Figure 7-1 Power tree for the DE10-Advanced board ==Reset== Figure 7-2 illustrates the reset circuit on the DE10-Advanced development board.<br/> [[File:Reset.jpg|600px]] :::::Figure 7-2 Reset circuit for the DE10-Advanced board ===HPS Reset=== The HPS cold reset (HPS_RESET_n) is an input to MAX V controller, which force to reset the HPS and the peripheral circuit connected to HPS.It is active low input which resets all HPS logics.<br/> The HPS warm reset (HPS_WARM_RST_n) is also an input to MAX V controller,the active input affect the system reset domain for debug purpose. ===PCIe Reset=== A PCIe reset resets the logics and PCIe core. ===MAX V Reset=== The MAX V reset (MAX_RESET_n) is an input to MAX V controller,it resets the MAX V power and logics. ===HPS USB Reset=== The HPS USB reset (HPS_USB_RESET_n) is an input to MAX V controller,it resets the USB PHY logics on HPS position.

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