http://www.terasic.com.tw/wiki/index.php?action=history&feed=atom&title=Apollo_S10_User_Manual_revA_CH2 2026-06-06T15:22:10Z Revision history for this page on the wiki MediaWiki 1.16.5 http://www.terasic.com.tw/wiki/index.php?title=Apollo_S10_User_Manual_revA_CH2&diff=4002&oldid=prev 2019-12-09T05:44:38Z

<p><span class="autocomment">2.1 Configuration Interface</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 05:44, 9 December 2019</td> </tr><tr><td colspan="2" class="diff-lineno">Line 1:</td> <td colspan="2" class="diff-lineno">Line 1:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This chapter introduces all the important components on the Apoolo-S10 Board. &nbsp;</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>This chapter introduces all the important components on the Apoolo-S10 Board. &nbsp;</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>=2.1 Configuration Interface=</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>=2.1 Configuration Interface=</div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">This section describes the configuration mode for Stratix 10 SX FPGAs available on the Apoolo-S10 board. The peripheral circuits and usage scenarios for each mode will be listed.</ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">The Apoolo-S10 board supports the following configuration modes:</ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">*JTAG Mode (Configure the FPGA using the on-board USB-Blaster II). </ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">*Active Serial (AS) mode</ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">Users can use these modes to configure the FPGA or HPS (Hardware Process System) fabric in the Stratix 10 SX FPGA and make the FPGA to run the user's logic or boot the HPS to run the OS.</ins></div></td></tr> </table>

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