DE10-Advance usermanual revB - Revision history

Bingxia: /* 5.3 UART to USB */

2018-08-23T09:07:39Z

5.3 UART to USB

← Older revision		Revision as of 09:07, 23 August 2018
Line 2,065:		Line 2,065:
	!Signal Name !!FPGA Pin Number !!Description !!I/O Standard		!Signal Name !!FPGA Pin Number !!Description !!I/O Standard
	\|-		\|-
-	\|~~USBFX3_UART_TX~~ \|\|~~PIN_AP23~~\|\|~~HPS UART Transmitter~~ \|\|1.8V	+	\|USB_PD_SCL \|\|PIN_AJ19\|\|I2C Serial Clock \|\|1.8V
	\|-		\|-
-	\|~~USBFX3_UART_RX~~ \|\|~~PIN_AU27~~\|\|HPS UART Receiver \|\|1.8V	+	\|USB_PD_SDA \|\|PIN_AV16\|\|I2C Serial Data \|\|1.8V
		+	\|-
		+	\|I2C_INT \|\|PIN_AH27\|\|inter-integrated circuit \|\|1.8V
		+	\|-
		+	\|HPS_RXD_M \|\|PIN_L20\|\|HPS UART Receiver \|\|1.8V
		+	\|-
		+	\|HPS_TXD_M \|\|PIN_J19\|\|HPS UART Transmitter \|\|1.8V
	\|}		\|}

Bingxia: /* 5.3 UART to USB */

2018-08-23T08:24:48Z

5.3 UART to USB

← Older revision		Revision as of 08:24, 23 August 2018
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	==5.3 UART to USB==		==5.3 UART to USB==
	The board has one UART interface connected for communication with the HPS. This interface doesn’t support HW flow control signals. The physical interface is implemented by UART-USB onboard bridge from a FT232R chip to the host with an USB Mini-B connector. More information about the chip is available on the manufacturer’s website, or in the directory \Datasheets\UART TO USB of DE10-Advanced system CD. Figure 5-2 shows the connections between the HPS, FT232R chip, and the USB Mini-B connector. Table 5-4 lists the pin assignment of UART interface connected to the HPS.<br/>		The board has one UART interface connected for communication with the HPS. This interface doesn’t support HW flow control signals. The physical interface is implemented by UART-USB onboard bridge from a FT232R chip to the host with an USB Mini-B connector. More information about the chip is available on the manufacturer’s website, or in the directory \Datasheets\UART TO USB of DE10-Advanced system CD. Figure 5-2 shows the connections between the HPS, FT232R chip, and the USB Mini-B connector. Table 5-4 lists the pin assignment of UART interface connected to the HPS.<br/>
-	:::[[File:~~De10~~-~~ad-UART~~.jpg\|600px]]	+	:::[[File:DE10-Advanced uart.jpg\|600px]]
	::::::Figure 5-2 Connections between the HPS and USB Mini-B connector		::::::Figure 5-2 Connections between the HPS and USB Mini-B connector
	::::Table 5-4 Pin Assignment of UART Interface		::::Table 5-4 Pin Assignment of UART Interface

Admin: /* 5.6 GPIO Header */

2018-08-22T08:00:27Z

5.6 GPIO Header

← Older revision		Revision as of 08:00, 22 August 2018
Line 2,129:		Line 2,129:

	==5.6 GPIO Header ==		==5.6 GPIO Header ==
-	There is a 2x5 2.54mm ~~header~~ on the DE10-Advanced which connected to six FPGA HPS farbric GPIOs.These I/Os can be used as ~~GPIOs~~ that are directly controlled by HPS. Or it can be used as SPI interface (HPS_DIO[11:8]), using the SPI master controller in HPS to communicate with other SPI devices.	+	There is a 2x5 pin header(2.54mm) on the DE10-Advanced which connected to six FPGA HPS farbric GPIOs.These I/Os can be used as GPIO that are directly controlled by HPS. Or it can be used as SPI interface (HPS_DIO[11:8]), using the SPI master controller in HPS to communicate with other SPI devices.

	=Chapter 6 System Clocks=		=Chapter 6 System Clocks=

Admin: /* 5.6 GPIO Header */

2018-08-22T07:51:57Z

5.6 GPIO Header

← Older revision		Revision as of 07:51, 22 August 2018
Line 2,129:		Line 2,129:

	==5.6 GPIO Header ==		==5.6 GPIO Header ==
-	There is a 2x5 2.54mm header on the DE10-Advanced which connected to six FPGA HPS farbric GPIOs.	+	There is a 2x5 2.54mm header on the DE10-Advanced which connected to six FPGA HPS farbric GPIOs.These I/Os can be used as GPIOs that are directly controlled by HPS. Or it can be used as SPI interface (HPS_DIO[11:8]), using the SPI master controller in HPS to communicate with other SPI devices.

	=Chapter 6 System Clocks=		=Chapter 6 System Clocks=

Admin: /* 3.3 Status LED */

2018-08-22T07:14:16Z

3.3 Status LED

← Older revision		Revision as of 07:14, 22 August 2018
Line 252:		Line 252:
	This section describes the all status LED for the interfaces on DE10-Advanced board. Figure 3-6 shows all the status LED on the DE10-advanced. Following are the detailed descriptions of these interface LED.		This section describes the all status LED for the interfaces on DE10-Advanced board. Figure 3-6 shows all the status LED on the DE10-advanced. Following are the detailed descriptions of these interface LED.

-		+	[[File:De10 advanced revc ledinterface.jpg\|550px]]

	::: '''Figure 3-6 The status LED on the DE10-Advanced board		::: '''Figure 3-6 The status LED on the DE10-Advanced board

Admin: /* 3.4 JTAG Interface */

2018-08-22T07:10:32Z

3.4 JTAG Interface

← Older revision		Revision as of 07:10, 22 August 2018
Line 340:		Line 340:


-	[[File:~~JTAG INTERFACE~~.jpg\|500px]]	+	[[File:De10 advanced revc jtagchain.jpg\|500px]]
	::::::'''Figure 3-2 JTAG interface of DE10-Advanced'''		::::::'''Figure 3-2 JTAG interface of DE10-Advanced'''

Admin: /* Chapter 6 System Clocks */

2018-08-22T07:07:40Z

Chapter 6 System Clocks

← Older revision		Revision as of 07:07, 22 August 2018
Line 2,138:		Line 2,138:


-	:::[[File:~~Clock Net~~ connected to FPGA.~~png~~\|~~550px~~]]	+	:::[[File:De10 advanced revc clock net connected to FPGA.jpg\|600px]]

	:::::::::Figure 6-1 System Clock in the DE10-Advanced		:::::::::Figure 6-1 System Clock in the DE10-Advanced

Admin: /* 5.6 GPIO Header */

2018-08-22T03:52:37Z

5.6 GPIO Header

← Older revision		Revision as of 03:52, 22 August 2018
Line 2,129:		Line 2,129:

	==5.6 GPIO Header ==		==5.6 GPIO Header ==
		+	There is a 2x5 2.54mm header on the DE10-Advanced which connected to six FPGA HPS farbric GPIOs.

	=Chapter 6 System Clocks=		=Chapter 6 System Clocks=

Admin: /* 5.5 USB OTG */

2018-08-22T03:48:40Z

5.5 USB OTG

← Older revision		Revision as of 03:48, 22 August 2018
Line 2,127:		Line 2,127:
	\|HPS_USB_STP \|\| PIN_M25 \|\| Stop Data Stream on the Bus \|\|1.8V		\|HPS_USB_STP \|\| PIN_M25 \|\| Stop Data Stream on the Bus \|\|1.8V
	\|}		\|}
		+
		+	==5.6 GPIO Header ==

	=Chapter 6 System Clocks=		=Chapter 6 System Clocks=

Bingxia: /* 4.7 HDMI Transmitter and Receiver */

2018-08-22T03:42:06Z

4.7 HDMI Transmitter and Receiver

← Older revision		Revision as of 03:42, 22 August 2018
Line 1,360:		Line 1,360:
	::::[[File:HDMI interface of the DE10-Advanced.png\|500px]]		::::[[File:HDMI interface of the DE10-Advanced.png\|500px]]
	:::::::Figure 4-13 The HDMI transceiver interface of the DE10-Advanced		:::::::Figure 4-13 The HDMI transceiver interface of the DE10-Advanced
-	Table 4-X HDMI TX and RX port Pin Assignments, Signal Names and Functions	+	::::Table 4-11 HDMI TX and RX port Pin Assignments, Signal Names and Functions
		+	:{\| class="wikitable"
		+	\|-
		+	!Signal Name !!FPGA Pin Number !!Description !!I/O Standard
		+	\|-
		+	\|HDMI_TX_CLK_p \|\|V39 \|\|TX TMDS clock channel \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_TX_D_p[0] \|\|U37 \|\|TX TMDS data channel 0 \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_TX_D_p[1] \|\|T39 \|\|TX TMDS data channel 1 \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_TX_D_p[2] \|\|R37 \|\|TX TMDS data channel 2 \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_TX_SCL \|\|A28 \|\|I2C clock of the TX retimer IC and DCC \|\|1.8V
		+	\|-
		+	\|HDMI_TX_SDA \|\|A27 \|\|I2C data of the TX retimer IC and DCC \|\|1.8V
		+	\|-
		+	\|HDMI_HPD \|\|AF28 \|\|TX Hot Plug Detect \|\|1.8V
		+	\|-
		+	\|HDMI_RX_CLK_p \|\|Y31 \|\|RX TMDS clock channel \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_RX_D_p[0] \|\|Y35 \|\|RX TMDS data channel 0 \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_RX_D_p[1] \|\|W37 \|\|RX TMDS data channel 1 \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_RX_D_p[2] \|\|W33 \|\|RX TMDS data channel 2 \|\|HSSI Differential I/O
		+	\|-
		+	\|HDMI_RX_SCL \|\|V7 \|\|I2C clock of the RX redriver IC \|\|1.2 V
		+	\|-
		+	\|HDMI_RX_SDA \|\|T2 \|\|I2C clock of the RX redriver IC \|\|1.2 V
		+	\|-
		+	\|HDMI_HPD_RX \|\|AG27 \|\|RX Hot Plug Detect \|\|1.8V
		+	\|-
		+	\|HDMI_RX_5V_N \|\|C29 \|\|Detect if the TX terminal has 5V output \|\|1.8V
		+	\|-
		+	\|HDMI_REFCLK_p \|\|V31 \|\|HDMI Reference clock from on board PLL \|\|LVDS
		+	\|}

	==4.8 Gigabit Ethernet==		==4.8 Gigabit Ethernet==