DE10-Agilex Board Revision Document - Revision history

Admin: /* Board Revision Details */

2021-02-26T08:18:49Z

Board Revision Details

← Older revision		Revision as of 08:18, 26 February 2021
Line 10:		Line 10:

	=Board Revision Details=		=Board Revision Details=
-	*[DE10-Agilex Rev.A to Rev.B Revision List\|DE10-Agilex Rev.A to Rev.B Revision List]	+	*[[DE10-Agilex Rev.A to Rev.B Revision List\|DE10-Agilex Rev.A to Rev.B Revision List]]
-	~~==Rev. A to Rev. B==~~	+
-	~~#Add Force External Power Switch '''(SW1)''' to Enable/Disable External Power Requirement when connected to the HOST PC.~~	+
-	#:	+
-	~~#:[[File:De ag sw1.jpg\|400px~~]]	+
-	~~#Add System MAX10 Jtag bypass switch '''(SW9)''' for increase JTAG sacn speed.~~	+
-	#:	+
-	~~#:[[File:De ag sw9.jpg\|400px]]~~	+
-	~~#Modify the direction of the external power connector.~~	+
-	#:	+
-	~~#:[[File:De ag ex pwr.jpg\|700px]]~~	+
-	~~# Remove DDR4 Clock Source Switch (SW5) and change the DDR4 source clock oscillator (Y2) from dual clock OSC (166.667/300.0MHz) to 33.333Mhz OSC.~~	+
-	#:	+
-	#:	+
-	~~#:[[File:De ag ddr4 clock osc.jpg\|800px]]~~	+
-	~~#Modify the reference clock source(Y1) of the SI5340 clock generator(U13) to TCXO to increase the quality of the QSFPDD reference clock.~~	+
-	#:	+
-	~~#:[[File:De ag si5340 ref.jpg\|1200px]]~~	+
-	~~#Improve the core power chip(U15, VCC_CORE) from LT4680(rev.A) to LT4700(rev.B) , the power can be improve from 60A to 100A~~	+
-	~~#Rev.B board add a 30.72Mhz OCXO(U161) but it is not installed, reserved for CPRI application.~~	+
-	#:	+
-	~~#:[[File:De ag ocxo.jpg\|800px]]~~	+
-	~~# Pin Assignment change.~~	+
-	~~{\| class="wikitable sortable" border="1"~~	+
-	~~\|- bgcolor=#9999CC~~	+
-	~~!Net Name~~	+
-	~~!Rev.A Pin Assignment~~	+
-	~~!Rev.B Pin Assignment~~	+
-	\|-	+
-	~~\|\|PCIE_SMBCLK~~	+
-	~~\|\|F59~~	+
-	~~\|\|G50~~	+
-	\|-	+
-	~~\|\|PCIE_CLKREQ_n~~	+
-	~~\|\|J58~~	+
-	~~\|\|F55~~	+
-	\|-	+
-	~~\|\|PCIE_WAKE_n~~	+
-	~~\|\|G58~~	+
-	~~\|\|J50~~	+
-	\|-	+
-	~~\|\|DDR4B_SDA~~	+
-	~~\|\|H57~~	+
-	~~\|\|B19~~	+
-	\|-	+
-	~~\|\|GPIO_CLK0~~	+
-	~~\|\|CU24~~	+
-	~~\|\|DA22~~	+
-	\|-	+
-	~~\|\|GPIO_P0~~	+
-	~~\|\|DA22~~	+
-	~~\|\|CY21~~	+
-	\|-	+
-	~~\|\|INFO_SPI_MISO~~	+
-	~~\|\|CY21~~	+
-	~~\|\|CU26~~	+
-	\|}	+

Admin: /* Board Revision Details */

2021-02-26T08:18:09Z

Board Revision Details

← Older revision		Revision as of 08:18, 26 February 2021
Line 10:		Line 10:

	=Board Revision Details=		=Board Revision Details=
		+	*[DE10-Agilex Rev.A to Rev.B Revision List\|DE10-Agilex Rev.A to Rev.B Revision List]
	==Rev. A to Rev. B==		==Rev. A to Rev. B==
	#Add Force External Power Switch '''(SW1)''' to Enable/Disable External Power Requirement when connected to the HOST PC.		#Add Force External Power Switch '''(SW1)''' to Enable/Disable External Power Requirement when connected to the HOST PC.

Admin: /* Rev. A to Rev. B */

2021-02-26T08:15:27Z

Rev. A to Rev. B

← Older revision		Revision as of 08:15, 26 February 2021
Line 31:		Line 31:
	#:		#:
	#:[[File:De ag ocxo.jpg\|800px]]		#:[[File:De ag ocxo.jpg\|800px]]
		+	# Pin Assignment change.
		+	{\| class="wikitable sortable" border="1"
		+	\|- bgcolor=#9999CC
		+	!Net Name
		+	!Rev.A Pin Assignment
		+	!Rev.B Pin Assignment
		+	\|-
		+	\|\|PCIE_SMBCLK
		+	\|\|F59
		+	\|\|G50
		+	\|-
		+	\|\|PCIE_CLKREQ_n
		+	\|\|J58
		+	\|\|F55
		+	\|-
		+	\|\|PCIE_WAKE_n
		+	\|\|G58
		+	\|\|J50
		+	\|-
		+	\|\|DDR4B_SDA
		+	\|\|H57
		+	\|\|B19
		+	\|-
		+	\|\|GPIO_CLK0
		+	\|\|CU24
		+	\|\|DA22
		+	\|-
		+	\|\|GPIO_P0
		+	\|\|DA22
		+	\|\|CY21
		+	\|-
		+	\|\|INFO_SPI_MISO
		+	\|\|CY21
		+	\|\|CU26
		+	\|}

Admin: /* Rev. A to Rev. B */

2021-02-26T07:06:20Z

Rev. A to Rev. B

← Older revision		Revision as of 07:06, 26 February 2021
Line 27:		Line 27:
	#:		#:
	#:[[File:De ag si5340 ref.jpg\|1200px]]		#:[[File:De ag si5340 ref.jpg\|1200px]]
-	#Improve the core power chip(U15, VCC_CORE) from LT4680 to LT4700 , the power can be improve from 60A to 100A	+	#Improve the core power chip(U15, VCC_CORE) from LT4680(rev.A) to LT4700(rev.B) , the power can be improve from 60A to 100A
-	#~~Add~~ a 30.72Mhz OCXO(U161) but it is not installed, reserved for CPRI application.	+	#Rev.B board add a 30.72Mhz OCXO(U161) but it is not installed, reserved for CPRI application.
	#:		#:
	#:[[File:De ag ocxo.jpg\|800px]]		#:[[File:De ag ocxo.jpg\|800px]]

Admin: /* Rev. A to Rev. B */

2021-02-26T07:05:39Z

Rev. A to Rev. B

← Older revision		Revision as of 07:05, 26 February 2021
Line 28:		Line 28:
	#:[[File:De ag si5340 ref.jpg\|1200px]]		#:[[File:De ag si5340 ref.jpg\|1200px]]
	#Improve the core power chip(U15, VCC_CORE) from LT4680 to LT4700 , the power can be improve from 60A to 100A		#Improve the core power chip(U15, VCC_CORE) from LT4680 to LT4700 , the power can be improve from 60A to 100A
		+	#Add a 30.72Mhz OCXO(U161) but it is not installed, reserved for CPRI application.
		+	#:
		+	#:[[File:De ag ocxo.jpg\|800px]]

Admin: /* Rev. A to Rev. B */

2021-02-26T06:49:56Z

Rev. A to Rev. B

← Older revision		Revision as of 06:49, 26 February 2021
Line 27:		Line 27:
	#:		#:
	#:[[File:De ag si5340 ref.jpg\|1200px]]		#:[[File:De ag si5340 ref.jpg\|1200px]]
		+	#Improve the core power chip(U15, VCC_CORE) from LT4680 to LT4700 , the power can be improve from 60A to 100A

Admin: /* Rev. A to Rev. B */

2021-02-26T06:44:36Z

Rev. A to Rev. B

← Older revision		Revision as of 06:44, 26 February 2021
Line 24:		Line 24:
	#:		#:
	#:[[File:De ag ddr4 clock osc.jpg\|800px]]		#:[[File:De ag ddr4 clock osc.jpg\|800px]]
-	#:	+	#Modify the reference clock source(Y1) of the SI5340 clock generator(U13) to TCXO to increase the quality of the QSFPDD reference clock.
	#:		#:
	#:[[File:De ag si5340 ref.jpg\|1200px]]		#:[[File:De ag si5340 ref.jpg\|1200px]]

Admin: /* Rev. A to Rev. B */

2021-02-26T06:39:36Z

Rev. A to Rev. B

← Older revision		Revision as of 06:39, 26 February 2021
Line 24:		Line 24:
	#:		#:
	#:[[File:De ag ddr4 clock osc.jpg\|800px]]		#:[[File:De ag ddr4 clock osc.jpg\|800px]]
		+	#:
		+	#:
		+	#:[[File:De ag si5340 ref.jpg\|1200px]]

Admin: /* Rev. A to Rev. B */

2021-02-26T06:29:30Z

Rev. A to Rev. B

← Older revision		Revision as of 06:29, 26 February 2021
Line 20:		Line 20:
	#:		#:
	#:[[File:De ag ex pwr.jpg\|700px]]		#:[[File:De ag ex pwr.jpg\|700px]]
-	# Remove DDR4 Clock Source Switch (SW5) and change the DDR4 source clock oscillator (Y2) from dual clock OSC to 33.333Mhz OSC.	+	# Remove DDR4 Clock Source Switch (SW5) and change the DDR4 source clock oscillator (Y2) from dual clock OSC (166.667/300.0MHz) to 33.333Mhz OSC.
	#:		#:
	#:		#:
	#:[[File:De ag ddr4 clock osc.jpg\|800px]]		#:[[File:De ag ddr4 clock osc.jpg\|800px]]

Admin: /* Rev. A to Rev. B */

2021-02-26T06:28:19Z

Rev. A to Rev. B

← Older revision		Revision as of 06:28, 26 February 2021
Line 14:		Line 14:
	#:		#:
	#:[[File:De ag sw1.jpg\|400px]]		#:[[File:De ag sw1.jpg\|400px]]
-	#Add System MAX10 Jtag bypass switch (SW9) for increase JTAG sacn speed.	+	#Add System MAX10 Jtag bypass switch '''(SW9)''' for increase JTAG sacn speed.
	#:		#:
	#:[[File:De ag sw9.jpg\|400px]]		#:[[File:De ag sw9.jpg\|400px]]

← Older revision		Revision as of 08:15, 26 February 2021
Line 31:		Line 31:
	#:		#:
	#:[[File:De ag ocxo.jpg\|800px]]		#:[[File:De ag ocxo.jpg\|800px]]
		+	# Pin Assignment change.
		+	{\| class="wikitable sortable" border="1"
		+	\|- bgcolor=#9999CC
		+	!Net Name
		+	!Rev.A Pin Assignment
		+	!Rev.B Pin Assignment
		+	\|-
		+	\|\|PCIE_SMBCLK
		+	\|\|F59
		+	\|\|G50
		+	\|-
		+	\|\|PCIE_CLKREQ_n
		+	\|\|J58
		+	\|\|F55
		+	\|-
		+	\|\|PCIE_WAKE_n
		+	\|\|G58
		+	\|\|J50
		+	\|-
		+	\|\|DDR4B_SDA
		+	\|\|H57
		+	\|\|B19
		+	\|-
		+	\|\|GPIO_CLK0
		+	\|\|CU24
		+	\|\|DA22
		+	\|-
		+	\|\|GPIO_P0
		+	\|\|DA22
		+	\|\|CY21
		+	\|-
		+	\|\|INFO_SPI_MISO
		+	\|\|CY21
		+	\|\|CU26
		+	\|}