Bingxia at 07:10, 7 June 2017

2017-06-07T07:10:23Z

← Older revision		Revision as of 07:10, 7 June 2017
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	*<font size="3"><font face="Times New Roman">Q：Why the FPGA side using SDRAM instead of DDR3?</font></font><br/><font size="3"><font face="Times New Roman">A：DE10-Standard is mostly for colleges, the board has six 7-segment dispalys, ten slide switches, 4 push-buttons and so on, so no pins assigned for DDR3.</font></font><br/><br/>		*<font size="3"><font face="Times New Roman">Q：Why the FPGA side using SDRAM instead of DDR3?</font></font><br/><font size="3"><font face="Times New Roman">A：DE10-Standard is mostly for colleges, the board has six 7-segment dispalys, ten slide switches, 4 push-buttons and so on, so no pins assigned for DDR3.</font></font><br/><br/>
-	*<font size="3"><font face="Times New Roman">Q：Why DE10-Standard equipped with Cyclone V SX FPGA, but no transceiver on HSMC?</font></font><br/><font size="3"><font face="Times New Roman">A： It requires fitted clock gen if add transceiver on HSMC, also more PCB material is needed and cost will increase, consider that most of users won't use transceiver, so the board isn't implement the transceiver.</font></font>	+	*<font size="3"><font face="Times New Roman">Q：Why DE10-Standard equipped with Cyclone V SX FPGA, but no transceiver on HSMC?</font></font><br/><font size="3"><font face="Times New Roman">A： It requires fitted clock gen if add transceiver on HSMC, also more PCB material is needed and cost will increase, consider that most of users won't use transceiver, so the board isn't implement the transceiver.</font></font><br/><br/><br/><br/>[[DE10 Standard Reference FAQ\|Back]]

Bingxia: Created page with "*Q：Why the FPGA side using SDRAM instead of DDR3?
A：DE10-Standard is..."

2017-06-07T07:04:29Z

Created page with "*Q：Why the FPGA side using SDRAM instead of DDR3? A：DE10-Standard is..."

New page

*Q：Why the FPGA side using SDRAM instead of DDR3? A：DE10-Standard is mostly for colleges, the board has six 7-segment dispalys, ten slide switches, 4 push-buttons and so on, so no pins assigned for DDR3. 
*Q：Why DE10-Standard equipped with Cyclone V SX FPGA, but no transceiver on HSMC? A： It requires fitted clock gen if add transceiver on HSMC, also more PCB material is needed and cost will increase, consider that most of users won't use transceiver, so the board isn't implement the transceiver.

English - Revision history

Bingxia at 07:10, 7 June 2017

Bingxia: Created page with "*Q：Why the FPGA side using SDRAM instead of DDR3?A：DE10-Standard is..."

Bingxia: Created page with "*Q：Why the FPGA side using SDRAM instead of DDR3?
A：DE10-Standard is..."