F2G User Manual - Revision history

Admin: /* Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 */

2022-06-20T08:49:32Z

Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3

← Older revision		Revision as of 08:49, 20 June 2022
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	<span style="color:#00b050;">'''(*1) : Pin 29: VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: [[F2G_User_Manual#Pin_Out_Of_the_GPIO_Header\|Pin Out Of the GPIO Header]] for details</span>'''		<span style="color:#00b050;">'''(*1) : Pin 29: VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: [[F2G_User_Manual#Pin_Out_Of_the_GPIO_Header\|Pin Out Of the GPIO Header]] for details</span>'''

-	=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===	+	=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 pin ===
	<span style="color:#ff0000;">Note: The following header is not to adjust the i/o stadnard of the GPIO pin, but to adjust the voltage level fo the power pin (Pin 29) on the connector.</span>''		<span style="color:#ff0000;">Note: The following header is not to adjust the i/o stadnard of the GPIO pin, but to adjust the voltage level fo the power pin (Pin 29) on the connector.</span>''

Admin: /* Pin Mappings for GPIO and FMC */

2022-06-20T08:45:42Z

Pin Mappings for GPIO and FMC

← Older revision		Revision as of 08:45, 20 June 2022
Line 1,005:		Line 1,005:


-	<span style="color:#00b050;">'''(*1) : VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: [[F2G_User_Manual#Pin_Out_Of_the_GPIO_Header\|Pin Out Of the GPIO Header]] for details</span>'''	+	<span style="color:#00b050;">'''(*1) : Pin 29: VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: [[F2G_User_Manual#Pin_Out_Of_the_GPIO_Header\|Pin Out Of the GPIO Header]] for details</span>'''

	=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===		=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===

Admin: /* Chpater1 Introduction */

2022-06-20T08:43:43Z

Chpater1 Introduction

← Older revision		Revision as of 08:43, 20 June 2022
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	= <span style="color:#000080;">Chpater1 Introduction</span> =		= <span style="color:#000080;">Chpater1 Introduction</span> =
	The F2G board is designed to convert a '''FPGA Mezzanine Card'''(FMC) or '''FPGA Mezzanine Card Plus'''(FMC+) interface to four 2x20pin expansion prototype(GPIO) headers. Users can connect up to four GPIO headers onto a FMC-interfaced host board via a F2G board.		The F2G board is designed to convert a '''FPGA Mezzanine Card'''(FMC) or '''FPGA Mezzanine Card Plus'''(FMC+) interface to four 2x20pin expansion prototype(GPIO) headers. Users can connect up to four GPIO headers onto a FMC-interfaced host board via a F2G board.
-	<span style="color:#ff0000;"> a </span>'''	+
		+	<span style="color:#ff0000;"> Note : the I/O Pin of the GPIO header is directly connected to the I/O of the FMC connector and has not been converted by any level translator. Therefore, the I / O standard of the GPIO header depends on the voltage settings on the FPGA maina board. </span>'''
	==1-1 Kit Contents ==		==1-1 Kit Contents ==
	<span style="color:#0000ff;">Figure 1-1</span> shows a photograph of the F2G package.		<span style="color:#0000ff;">Figure 1-1</span> shows a photograph of the F2G package.

Admin: /* Chpater1 Introduction */

2022-06-20T08:42:40Z

Chpater1 Introduction

← Older revision		Revision as of 08:42, 20 June 2022
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	= <span style="color:#000080;">Chpater1 Introduction</span> =		= <span style="color:#000080;">Chpater1 Introduction</span> =
-	The F2G board is designed to convert a '''FPGA Mezzanine Card'''(FMC) or '''FPGA Mezzanine Card Plus'''(FMC+) interface to four 2x20pin expansion prototype(GPIO) headers~~, which are compatible with the expansion headers of the Terasic DE-Series board(Such as DE2-115/DE10-Standard)~~. Users can connect up to four GPIO headers onto a FMC-interfaced host board via a F2G board.	+	The F2G board is designed to convert a '''FPGA Mezzanine Card'''(FMC) or '''FPGA Mezzanine Card Plus'''(FMC+) interface to four 2x20pin expansion prototype(GPIO) headers. Users can connect up to four GPIO headers onto a FMC-interfaced host board via a F2G board.
		+	<span style="color:#ff0000;"> a </span>'''
	==1-1 Kit Contents ==		==1-1 Kit Contents ==
	<span style="color:#0000ff;">Figure 1-1</span> shows a photograph of the F2G package.		<span style="color:#0000ff;">Figure 1-1</span> shows a photograph of the F2G package.

Admin: /* Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 */

2022-06-20T08:41:25Z

Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3

← Older revision		Revision as of 08:41, 20 June 2022
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	<span style="color:#ff0000;">Note: The following header is not to adjust the i/o stadnard of the GPIO pin, but to adjust the voltage level fo the power pin (Pin 29) on the connector.</span>''		<span style="color:#ff0000;">Note: The following header is not to adjust the i/o stadnard of the GPIO pin, but to adjust the voltage level fo the power pin (Pin 29) on the connector.</span>''

-	On the F2G board, user can choose to provide 3.3V or VADJ (from maina board through FMC) via 3-pin header. For example, pin 29 on GPIO0 is VCC_GPIO0, and this power is controlled by JP6. If pin1 and pin2 of JP6 are short-circuited, then VCC_GPIO0 will be 3.3V. If short Pin 2 and Pin3, VCC_GPIO0 will be VADJ. The default setting of all the 3-pin header is short pin 1 and 2, i.e. 3.3V is provided. The control header corresponding to each GPIO header is shown in <span style="color:#0000ff;">Table 2-1</span>.	+	On the F2G board, user can choose to provide 3.3V or VADJ (from maina board through FMC) on the pin 29 of the GPIO header via 3-pin header. For example, pin 29 on GPIO0 is VCC_GPIO0, and this power is controlled by JP6. If pin1 and pin2 of JP6 are short-circuited, then VCC_GPIO0 will be 3.3V. If short Pin 2 and Pin3, VCC_GPIO0 will be VADJ. The default setting of all the 3-pin header is short pin 1 and 2, i.e. 3.3V is provided. The control header corresponding to each GPIO header is shown in <span style="color:#0000ff;">Table 2-1</span>.

	<div style="text-align:center;"> '''Table 2‑1 3-pin headers of controlling VCC_GPIOX and corresponding GPIO headers'''</div>		<div style="text-align:center;"> '''Table 2‑1 3-pin headers of controlling VCC_GPIOX and corresponding GPIO headers'''</div>

Admin: /* Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 */

2022-06-20T08:40:09Z

Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3

← Older revision		Revision as of 08:40, 20 June 2022
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	=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===		=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===
		+	<span style="color:#ff0000;">Note: The following header is not to adjust the i/o stadnard of the GPIO pin, but to adjust the voltage level fo the power pin (Pin 29) on the connector.</span>''

		+	On the F2G board, user can choose to provide 3.3V or VADJ (from maina board through FMC) via 3-pin header. For example, pin 29 on GPIO0 is VCC_GPIO0, and this power is controlled by JP6. If pin1 and pin2 of JP6 are short-circuited, then VCC_GPIO0 will be 3.3V. If short Pin 2 and Pin3, VCC_GPIO0 will be VADJ. The default setting of all the 3-pin header is short pin 1 and 2, i.e. 3.3V is provided. The control header corresponding to each GPIO header is shown in <span style="color:#0000ff;">Table 2-1</span>.

	<div style="text-align:center;"> '''Table 2‑1 3-pin headers of controlling VCC_GPIOX and corresponding GPIO headers'''</div>		<div style="text-align:center;"> '''Table 2‑1 3-pin headers of controlling VCC_GPIOX and corresponding GPIO headers'''</div>

Admin: /* Pin Out Of the GPIO Header */

2022-06-20T08:37:08Z

Pin Out Of the GPIO Header

← Older revision		Revision as of 08:37, 20 June 2022
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	There are four 2x20 GPIO headers on the F2G board(See <span style="color:#0000ff;">Figure 2-1a</span>). <span style="color:#0000ff;">Figure 2-1b</span> shows the Pin 1 of the GPIO headers. The pin distribution and power of each GPIO header (See <span style="color:#0000ff;">Figure 2-2</span> and <span style="color:#0000ff;">Figure 2-3</span>)is almost the same as the GPIO of Teraic DE series board. Each GPIO header can provide 36 user I / O and two sets of power supply and ground pin.		There are four 2x20 GPIO headers on the F2G board(See <span style="color:#0000ff;">Figure 2-1a</span>). <span style="color:#0000ff;">Figure 2-1b</span> shows the Pin 1 of the GPIO headers. The pin distribution and power of each GPIO header (See <span style="color:#0000ff;">Figure 2-2</span> and <span style="color:#0000ff;">Figure 2-3</span>)is almost the same as the GPIO of Teraic DE series board. Each GPIO header can provide 36 user I / O and two sets of power supply and ground pin.

-	Only on pin 29: Power pin is a little different. On the F2G board, user can choose to provide 3.3V or VADJ (from maina board through FMC) via 3-pin header. For example, pin 29 on GPIO0 is VCC_GPIO0, and this power is controlled by JP6. If pin1 and pin2 of JP6 are short-circuited, then VCC_GPIO0 will be 3.3V. If short Pin 2 and Pin3, VCC_GPIO0 will be VADJ. The default setting of all the 3-pin header is short pin 1 and 2, i.e. 3.3V is provided. The control header corresponding to each GPIO header is shown in <span style="color:#0000ff;">Table 2-1</span>.

	{\| align="center" class="" border="1"		{\| align="center" class="" border="1"

Admin: /* Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 */

2022-06-20T08:36:11Z

Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3

← Older revision		Revision as of 08:36, 20 June 2022
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	=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===		=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===
		+
		+
		+	<div style="text-align:center;"> '''Table 2‑1 3-pin headers of controlling VCC_GPIOX and corresponding GPIO headers'''</div>
		+	{\| align="center" style="border-spacing:0;width:11.772cm;"
		+	\|- style="background-color:#846a44;border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;"
		+	\| align="center" style="background-color:#846a44;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.212cm;color:#000000;" \| <span style="color:#ffffff;">'''3-Pin Header for VCC_GPIOX'''</span>
		+	\| align="center" style="background-color:#846a44;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.212cm;color:#000000;" \| <span style="color:#ffffff;">'''GPIO Header'''</span>
		+	\|-
		+	\| align=center style="background-color:#ffffcc;border-top:0.5pt solid #00000a;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.049cm;color:#404040;" \| JP6
		+	\| align=center style="background-color:#ffffcc;border-top:0.5pt solid #00000a;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.049cm;color:#404040;" \| <span style="color:#000000;">GPIO0(JP1)</span>
		+	\|-
		+	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| JP7
		+	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| <span style="color:#000000;">GPIO1(JP2)</span>
		+	\|-
		+	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| JP8
		+	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| <span style="color:#000000;">GPIO2(JP3)</span>
		+	\|-
		+	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| JP9
		+	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| <span style="color:#000000;">GPIO3(JP4)</span>
		+	\|-
		+	\|}

	==2-2 2x6 TMD Headers ==		==2-2 2x6 TMD Headers ==

Admin: /* Pin Out Of the GPIO Header */

2022-06-20T08:35:57Z

Pin Out Of the GPIO Header

← Older revision		Revision as of 08:35, 20 June 2022
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	<div style="text-align:center;color:#ff0000;"> [[Image: F2g gpio23a pin.jpg\|750px]]</div>		<div style="text-align:center;color:#ff0000;"> [[Image: F2g gpio23a pin.jpg\|750px]]</div>
	<div style="text-align:center;"> '''Figure 2‑3 Pin-outs of the GPIO2 and GPIO3'''</div>		<div style="text-align:center;"> '''Figure 2‑3 Pin-outs of the GPIO2 and GPIO3'''</div>
-
-
-	~~<div style="text-align:center;"> '''Table 2‑1 3-pin headers of controlling VCC_GPIOX and corresponding GPIO headers'''</div>~~
-	~~{\| align="center" style="border-spacing:0;width:11.772cm;"~~
-	~~\|- style="background-color:#846a44;border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;"~~
-	\| align="center" style="background-color:#846a44;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.212cm;color:#000000;" \| <span style="color:#ffffff;">'''3-Pin Header for VCC_GPIOX'''</span>
-	\| align="center" style="background-color:#846a44;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding:0.212cm;color:#000000;" \| <span style="color:#ffffff;">'''GPIO Header'''</span>
-	\|-
-	\| align=center style="background-color:#ffffcc;border-top:0.5pt solid #00000a;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.049cm;color:#404040;" \| JP6
-	\| align=center style="background-color:#ffffcc;border-top:0.5pt solid #00000a;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.049cm;color:#404040;" \| <span style="color:#000000;">GPIO0(JP1)</span>
-	\|-
-	~~\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| JP7~~
-	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| <span style="color:#000000;">GPIO1(JP2)</span>
-	\|-
-	~~\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| JP8~~
-	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| <span style="color:#000000;">GPIO2(JP3)</span>
-	\|-
-	~~\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| JP9~~
-	\| align=center style="background-color:#ffffcc;border:0.5pt solid #999999;padding-top:0cm;padding-bottom:0cm;padding-left:0.058cm;padding-right:0.058cm;color:#404040;" \| <span style="color:#000000;">GPIO3(JP4)</span>
-	\|-
-	\|}

	=== I/O standard of the GPIO headers===		=== I/O standard of the GPIO headers===

Admin: /* Voltage Setting for VCCIO */

2022-06-20T08:35:34Z

Voltage Setting for VCCIO

← Older revision		Revision as of 08:35, 20 June 2022
Line 1,027:		Line 1,027:
	<span style="color:#00b050;">'''(*1) : VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: [[F2G_User_Manual#Pin_Out_Of_the_GPIO_Header\|Pin Out Of the GPIO Header]] for details</span>'''		<span style="color:#00b050;">'''(*1) : VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: [[F2G_User_Manual#Pin_Out_Of_the_GPIO_Header\|Pin Out Of the GPIO Header]] for details</span>'''

-	=== Voltage Setting for ~~VCCIO~~ ===	+	=== Voltage Setting for VCC_GPIO0/VCC_GPIO1/VCC_GPIO2/VCC_GPIO3 ===

	==2-2 2x6 TMD Headers ==		==2-2 2x6 TMD Headers ==