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<p><span class="autocomment">3.7 USB 3.0 从设备(Device)</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 06:24, 13 October 2025</td> </tr><tr><td colspan="2" class="diff-lineno">Line 223:</td> <td colspan="2" class="diff-lineno">Line 223:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA加速板上放置了一颗Cypress型号为CYUSB3014的 USB 3.0控制器. 能提USB3.0 Device端以及USB2.0 OTG的相关应用. 用户可以透过这个接口, 将FPGA与CPU主系统或者其他计算机主机进行USB3.0的数据传输。</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA加速板上放置了一颗Cypress型号为CYUSB3014的 USB 3.0控制器. 能提USB3.0 Device端以及USB2.0 OTG的相关应用. 用户可以透过这个接口, 将FPGA与CPU主系统或者其他计算机主机进行USB3.0的数据传输。</div></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del style="color: red; font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2">&nbsp;</td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del style="color: red; font-weight: bold; text-decoration: none;">更多详细的资料请参考ＣＤ内的Datasheet文件夹中FX3子文件夹。</del></div></td><td colspan="2">&nbsp;</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-6USBDevice.jpg|400px]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-6USBDevice.jpg|400px]]</div></td></tr> </table>

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<p><span class="autocomment">3.6 USB 3.0 主设备(Host)</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 06:24, 13 October 2025</td> </tr><tr><td colspan="2" class="diff-lineno">Line 214:</td> <td colspan="2" class="diff-lineno">Line 214:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA加速版上保留了一颗 USB 3.0兼容的xHCI Host 控制器(TI :TUSB7320IRKM), 搭配了两个USB 3.0 Standard-A接口.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPGA加速版上保留了一颗 USB 3.0兼容的xHCI Host 控制器(TI :TUSB7320IRKM), 搭配了两个USB 3.0 Standard-A接口.</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>预期能让ＦＰＧＡ加速板可以提供两个USB 3.0 Host的功能. '''注意, 此功能目前为保留设计, 尚无法使用'''.</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>预期能让ＦＰＧＡ加速板可以提供两个USB 3.0 Host的功能. '''注意, 此功能目前为保留设计, 尚无法使用'''.</div></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>TUSB7320IRKM 控制器与FPGA连接的接口遵从PCIe x1 Gen2 协议.所以，需将两者间用一对ＴＸ/RX的transceiver相连接。 <del class="diffchange diffchange-inline">详细的控制器信息可以参考ＣＤ内的Datasheet文件夹中tusb7320.pdf文件。</del></div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>TUSB7320IRKM 控制器与FPGA连接的接口遵从PCIe x1 Gen2 协议.所以，需将两者间用一对ＴＸ/RX的transceiver相连接。</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-5USBHOST_2.jpg|400px]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-5USBHOST_2.jpg|400px]]</div></td></tr> </table>

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<p><span class="autocomment">3.2 FPGA加速版卡功能方块图</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 06:27, 29 August 2019</td> </tr><tr><td colspan="2" class="diff-lineno">Line 165:</td> <td colspan="2" class="diff-lineno">Line 165:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>图3-1为FPGA加速系统的主要组件与ＣＰＵ主机系统连接区块图</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>图3-1为FPGA加速系统的主要组件与ＣＰＵ主机系统连接区块图</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>:[[File:Hero FPGA acceleration system block diagram 1.jpg|<del class="diffchange diffchange-inline">600px</del>]]</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>:[[File:Hero FPGA acceleration system block diagram 1.jpg|<ins class="diffchange diffchange-inline">700px</ins>]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-1 FPGA 加速卡组件框图'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-1 FPGA 加速卡组件框图'''</div></td></tr> </table>

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<p><span class="autocomment">3.2 FPGA加速版卡功能方块图</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 06:27, 29 August 2019</td> </tr><tr><td colspan="2" class="diff-lineno">Line 165:</td> <td colspan="2" class="diff-lineno">Line 165:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>图3-1为FPGA加速系统的主要组件与ＣＰＵ主机系统连接区块图</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>图3-1为FPGA加速系统的主要组件与ＣＰＵ主机系统连接区块图</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>:[[File:Hero FPGA acceleration system block diagram.jpg|600px]]</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>:[[File:Hero FPGA acceleration system block diagram <ins class="diffchange diffchange-inline">1</ins>.jpg|600px]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-1 FPGA 加速卡组件框图'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-1 FPGA 加速卡组件框图'''</div></td></tr> </table>

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<p><span class="autocomment">2.8 时钟电路</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 01:45, 3 October 2018</td> </tr><tr><td colspan="2" class="diff-lineno">Line 244:</td> <td colspan="2" class="diff-lineno">Line 244:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>如图x所示.FPGA加速板上有多个osc与 on board PLL提供时钟频率给FPGA进行多样的应用.&nbsp; 其中提供给 FPGA transceiver bank的 PLL 可以透过 I2C去改变输出的频率.以便满足其特殊需求. 其他输入FPGA的固定频率也被连接入专属的FPGA时钟输入管脚.&nbsp; 用户可以使用FPGA内部的PLL对输入频率进行倍频或者分频后使用。</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>如图x所示.FPGA加速板上有多个osc与 on board PLL提供时钟频率给FPGA进行多样的应用.&nbsp; 其中提供给 FPGA transceiver bank的 PLL 可以透过 I2C去改变输出的频率.以便满足其特殊需求. 其他输入FPGA的固定频率也被连接入专属的FPGA时钟输入管脚.&nbsp; 用户可以使用FPGA内部的PLL对输入频率进行倍频或者分频后使用。</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-8clock.jpg|<del class="diffchange diffchange-inline">600px</del>]]</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-8clock.jpg|<ins class="diffchange diffchange-inline">900px</ins>]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-8&nbsp; 时钟框图'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-8&nbsp; 时钟框图'''</div></td></tr> </table>

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<p><span class="autocomment">3.4 DDR4内存</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 01:43, 3 October 2018</td> </tr><tr><td colspan="2" class="diff-lineno">Line 199:</td> <td colspan="2" class="diff-lineno">Line 199:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPG加速板上提供了四颗总容量共2GB的DDR4器件(见图2-x). 可用于数据缓存使用. 可使用的位宽最大为64bit并在2400Mhz(I1 速度等级的FPGA)频率下运行. 最大的理论带宽为153.6Gbps. 详细的FPGA对于DDR4的I/O管脚分配如表2-x。</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPG加速板上提供了四颗总容量共2GB的DDR4器件(见图2-x). 可用于数据缓存使用. 可使用的位宽最大为64bit并在2400Mhz(I1 速度等级的FPGA)频率下运行. 最大的理论带宽为153.6Gbps. 详细的FPGA对于DDR4的I/O管脚分配如表2-x。</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>[[File:Hero_HD_f3-4-DDR4.jpg|<del class="diffchange diffchange-inline">400px</del>]]</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>[[File:Hero_HD_f3-4-DDR4.jpg|<ins class="diffchange diffchange-inline">600px</ins>]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-4&nbsp; DDR4与FPGA连接图'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-4&nbsp; DDR4与FPGA连接图'''</div></td></tr> </table>

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<p><span class="autocomment">3.4 DDR4内存</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 01:43, 3 October 2018</td> </tr><tr><td colspan="2" class="diff-lineno">Line 199:</td> <td colspan="2" class="diff-lineno">Line 199:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPG加速板上提供了四颗总容量共2GB的DDR4器件(见图2-x). 可用于数据缓存使用. 可使用的位宽最大为64bit并在2400Mhz(I1 速度等级的FPGA)频率下运行. 最大的理论带宽为153.6Gbps. 详细的FPGA对于DDR4的I/O管脚分配如表2-x。</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>FPG加速板上提供了四颗总容量共2GB的DDR4器件(见图2-x). 可用于数据缓存使用. 可使用的位宽最大为64bit并在2400Mhz(I1 速度等级的FPGA)频率下运行. 最大的理论带宽为153.6Gbps. 详细的FPGA对于DDR4的I/O管脚分配如表2-x。</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>[[File:Hero_HD_f3-4-DDR4.<del class="diffchange diffchange-inline">png</del>|400px]]</div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>[[File:Hero_HD_f3-4-DDR4.<ins class="diffchange diffchange-inline">jpg</ins>|400px]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-4&nbsp; DDR4与FPGA连接图'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-4&nbsp; DDR4与FPGA连接图'''</div></td></tr> </table>

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<p></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 06:56, 29 September 2018</td> </tr><tr><td colspan="2" class="diff-lineno">Line 247:</td> <td colspan="2" class="diff-lineno">Line 247:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-8&nbsp; 时钟框图'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-8&nbsp; 时钟框图'''</div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">[[HERO_Doucment_Hardware_Manual|'''Back''']]</ins></div></td></tr> </table>

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<p><span class="autocomment">3.8 千兆以太网络</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 04:50, 29 September 2018</td> </tr><tr><td colspan="2" class="diff-lineno">Line 232:</td> <td colspan="2" class="diff-lineno">Line 232:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==3.8 千兆以太网络 ==</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==3.8 千兆以太网络 ==</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>FPGA加速板上配置了一颗10/100/1000千兆位以太网收发芯片 <del class="diffchange diffchange-inline">MARVELL　88E1111．该芯片是一个自动协商的以太网PHY，使用默认的SGMII MAC接口与ＦＰＧＡ相连.．</del></div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>FPGA加速板上配置了一颗10/100/1000千兆位以太网收发芯片 <ins class="diffchange diffchange-inline">MARVELL　88E1111。该芯片是一个自动协商的以太网PHY，使用默认的SGMII MAC接口与ＦＰＧＡ相连。</ins></div></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>传输的形式为LVDS I/O, 速度为1.<del class="diffchange diffchange-inline">2Gbps. 用户可以在ＦＰＧＡ内置入一个MAC </del>IP.便可以让此加速板与外部设备使用Ethernet <del class="diffchange diffchange-inline">进行通信.</del></div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>传输的形式为LVDS I/O, 速度为1.<ins class="diffchange diffchange-inline">2Gbps。用户可以在ＦＰＧＡ内置入一个MAC </ins>IP.便可以让此加速板与外部设备使用Ethernet <ins class="diffchange diffchange-inline">进行通信。</ins></div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-7NET.jpg|400px]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-7NET.jpg|400px]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-7&nbsp; FPGA加速卡网口'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-7&nbsp; FPGA加速卡网口'''</div></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del style="color: red; font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2">&nbsp;</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==2.8 时钟电路==</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==2.8 时钟电路==</div></td></tr> </table>

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<p><span class="autocomment">3.7 USB 3.0 从设备(Device)</span></p> <table style="background-color: white; color:black;"> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr valign='top'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 04:49, 29 September 2018</td> </tr><tr><td colspan="2" class="diff-lineno">Line 222:</td> <td colspan="2" class="diff-lineno">Line 222:</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==3.7 USB 3.0 从设备(Device)==&nbsp; &nbsp;</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==3.7 USB 3.0 从设备(Device)==&nbsp; &nbsp;</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div>FPGA加速板上放置了一颗Cypress型号为CYUSB3014的 USB 3.0控制器. 能提USB3.0 Device端以及USB2.0 OTG的相关应用. 用户可以透过这个接口, 将FPGA与CPU主系统或者其他计算机主机进行USB3.<del class="diffchange diffchange-inline">0的数据传输.</del></div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>FPGA加速板上放置了一颗Cypress型号为CYUSB3014的 USB 3.0控制器. 能提USB3.0 Device端以及USB2.0 OTG的相关应用. 用户可以透过这个接口, 将FPGA与CPU主系统或者其他计算机主机进行USB3.<ins class="diffchange diffchange-inline">0的数据传输。</ins></div></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del class="diffchange diffchange-inline">更多详细的资料请参考ＣＤ内的Datasheet文件夹中FX3子文件夹.</del></div></td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div>&#160;</div></td></tr> <tr><td colspan="2">&nbsp;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins class="diffchange diffchange-inline">更多详细的资料请参考ＣＤ内的Datasheet文件夹中FX3子文件夹。</ins></div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-6USBDevice.jpg|400px]]</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>[[File:Hero-HD-f3-6USBDevice.jpg|400px]]</div></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-6&nbsp; FPGA加速卡USB3.0从设备'''</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>'''图3-6&nbsp; FPGA加速卡USB3.0从设备'''</div></td></tr> <tr><td class='diff-marker'>-</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del style="color: red; font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2">&nbsp;</td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==3.8 千兆以太网络 ==</div></td><td class='diff-marker'> </td><td style="background: #eee; color:black; font-size: smaller;"><div>==3.8 千兆以太网络 ==</div></td></tr> </table>

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