HERO Doucment Hardware Manual English - Revision history

Admin: /* 3.7 USB 3.0 Device */

2025-10-13T06:23:57Z

3.7 USB 3.0 Device

← Older revision		Revision as of 06:23, 13 October 2025
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	The FPGA accelerator is equipped with a USB3.0 controller which is the Cypress model CYUSB3014. It can be used as the USB3.0 Device and related applications of USB2.0 OTG. The user can use this port to transmit data from the FPGA to the CPU system or other hosts.		The FPGA accelerator is equipped with a USB3.0 controller which is the Cypress model CYUSB3014. It can be used as the USB3.0 Device and related applications of USB2.0 OTG. The user can use this port to transmit data from the FPGA to the CPU system or other hosts.
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-	~~See more details from the CD\Datasheet\FX3 subfolder.~~

	[[File:Hero-HD-f3-6USBDevice.jpg\|400px]]		[[File:Hero-HD-f3-6USBDevice.jpg\|400px]]

	'''Figure 3-6 USB Blaster II Port of the FPGA Accelerator'''		'''Figure 3-6 USB Blaster II Port of the FPGA Accelerator'''
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	==3.8 Gigabit Ethernet==		==3.8 Gigabit Ethernet==

2025-10-13T06:23:41Z

3.6 USB 3.0 Host Port

← Older revision		Revision as of 06:23, 13 October 2025
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	The interface between the TUSB7320IRKM controller and FPGA follows the PCIe x1 Gen2 protocol.		The interface between the TUSB7320IRKM controller and FPGA follows the PCIe x1 Gen2 protocol.
-	So a pair of TX/RX transceiver should be used to connect these two devices~~. Please refer to the tusb7320.pdf document in the CD\Datasheet folder for the detailed information~~.	+	So a pair of TX/RX transceiver should be used to connect these two devices.

	[[File:Hero-HD-f3-5USBHOST_2.jpg\|400px]]		[[File:Hero-HD-f3-5USBHOST_2.jpg\|400px]]

2019-08-29T06:26:45Z

3.2 FPGA accelerator card block diagram

← Older revision		Revision as of 06:26, 29 August 2019
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	==3.2 FPGA accelerator card block diagram==		==3.2 FPGA accelerator card block diagram==
	Figure 3-1 shows the FPGA acceleration system components and the connection with the CPU system.		Figure 3-1 shows the FPGA acceleration system components and the connection with the CPU system.
-	:[[File:Hero FPGA acceleration system block diagram 1.jpg\|~~600px~~]]	+	:[[File:Hero FPGA acceleration system block diagram 1.jpg\|700px]]
	:::::'''Figure 3-1 FPGA acceleration system block diagram''''		:::::'''Figure 3-1 FPGA acceleration system block diagram''''

2019-08-29T06:26:36Z

3.2 FPGA accelerator card block diagram

← Older revision		Revision as of 06:26, 29 August 2019
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	==3.2 FPGA accelerator card block diagram==		==3.2 FPGA accelerator card block diagram==
	Figure 3-1 shows the FPGA acceleration system components and the connection with the CPU system.		Figure 3-1 shows the FPGA acceleration system components and the connection with the CPU system.
-	:[[File:Hero FPGA acceleration system block diagram.jpg\|600px]]	+	:[[File:Hero FPGA acceleration system block diagram 1.jpg\|600px]]
	:::::'''Figure 3-1 FPGA acceleration system block diagram''''		:::::'''Figure 3-1 FPGA acceleration system block diagram''''

2018-12-27T07:46:12Z

← Older revision		Revision as of 07:46, 27 December 2018
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	:*Wireless: Intel® Wireless-AC 8265 + Bluetooth 4.2		:*Wireless: Intel® Wireless-AC 8265 + Bluetooth 4.2
	*FPGA Acceleration system		*FPGA Acceleration system
-	:*FPGA: ~~Altera~~ Arria 10 GX FPGA (10AX115S2F45I1SG)	+	:*FPGA: Intel Arria 10 GX FPGA (10AX115S2F45I1SG)
	:*FPGA Configuration Circuit		:*FPGA Configuration Circuit
	::*On-Board USB Blaster II or JTAG header for FPGA programming		::*On-Board USB Blaster II or JTAG header for FPGA programming

2018-10-03T01:44:55Z

3.9 Clock Circuit

← Older revision		Revision as of 01:44, 3 October 2018
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	As shown in figure x, there is a variety of clock frequencies (OSC & on board PLL) for a variety of FPGA applications. The output frequency of PLL which is provided to FPGA transceiver bank can be changed through I2C interface for the different requirements. And the other input of fixed frequency is also being connected into the FPGA clock input dedicated pin. User can also get the frequency multiplied or frequency divided by using the FPGA internal PLL megafunction.		As shown in figure x, there is a variety of clock frequencies (OSC & on board PLL) for a variety of FPGA applications. The output frequency of PLL which is provided to FPGA transceiver bank can be changed through I2C interface for the different requirements. And the other input of fixed frequency is also being connected into the FPGA clock input dedicated pin. User can also get the frequency multiplied or frequency divided by using the FPGA internal PLL megafunction.

-	[[File:Hero-HD-f3-8clock.jpg\|~~600px~~]]	+	[[File:Hero-HD-f3-8clock.jpg\|900px]]

	'''Figure 3-8 Clock Networks'''		'''Figure 3-8 Clock Networks'''

2018-10-03T01:44:21Z

3.4 DDR4 Memory

← Older revision		Revision as of 01:44, 3 October 2018
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	The FPGA accelerator provides four DDR4 devices with a total capacity of 2GB (see figure 2-x). They can be used for data caching. The available bit width is up to 64bit and runs at 2400Mhz(FPGA speed grade: I1). The maximum bandwidth is 153.6Gbps theoretically. The I/O pin assignment of DDR4 is shown in table 2-x.		The FPGA accelerator provides four DDR4 devices with a total capacity of 2GB (see figure 2-x). They can be used for data caching. The available bit width is up to 64bit and runs at 2400Mhz(FPGA speed grade: I1). The maximum bandwidth is 153.6Gbps theoretically. The I/O pin assignment of DDR4 is shown in table 2-x.

-	[[File:Hero_HD_f3-4-DDR4.~~png~~\|~~400px~~]]	+	[[File:Hero_HD_f3-4-DDR4.jpg\|600px]]

	'''Figure 3-4 DDR4 to FPGA connection'''		'''Figure 3-4 DDR4 to FPGA connection'''
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	==3.5 PCIe interface==		==3.5 PCIe interface==

2018-09-29T04:40:35Z

3.6 USB 3.0 Host Port

← Older revision		Revision as of 04:40, 29 September 2018
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	So a pair of TX/RX transceiver should be used to connect these two devices. Please refer to the tusb7320.pdf document in the CD\Datasheet folder for the detailed information.		So a pair of TX/RX transceiver should be used to connect these two devices. Please refer to the tusb7320.pdf document in the CD\Datasheet folder for the detailed information.

-	[[File:Hero-HD-f3-~~5USBHOST~~.jpg\|400px]]	+	[[File:Hero-HD-f3-5USBHOST_2.jpg\|400px]]

	'''Figure 3-5 USB Hos Port of the FPGA Accelerator'''		'''Figure 3-5 USB Hos Port of the FPGA Accelerator'''

2018-09-29T01:12:28Z

3.9 Clock Circuit

← Older revision		Revision as of 01:12, 29 September 2018
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	'''Figure 3-8 Clock Networks'''		'''Figure 3-8 Clock Networks'''
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		+	*[[HERO_Doucment_Hardware_Manual\|'''Back''']]

2018-09-29T00:47:11Z

Gigabit Ethernet LAN Port

← Older revision		Revision as of 00:47, 29 September 2018
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	\|Yellow \|\|1000Mb/s data rate is selected		\|Yellow \|\|1000Mb/s data rate is selected
	\|}		\|}
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	===USB 3.0 Ports===		===USB 3.0 Ports===