VPX-A5SOC User Manual - Revision history

Bingxia: /* 2.1 Layout and Components */

2017-07-06T01:50:30Z

2.1 Layout and Components

← Older revision		Revision as of 01:50, 6 July 2017
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	<br/>The VPX-A5SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.		<br/>The VPX-A5SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.
-	<br/>The following ~~hardwares are~~ provided on the board:	+	<br/>The following hardware is provided on the board:
	*FPGA		*FPGA
	**EPCQ for AS-Mode FPGA configure		**EPCQ for AS-Mode FPGA configure

Bingxia: /* Chapter 1 VPX-A5SoC Development Kit */

2017-07-06T01:49:43Z

Chapter 1 VPX-A5SoC Development Kit

← Older revision		Revision as of 01:49, 6 July 2017
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	=Chapter 1 VPX-A5SoC Development Kit=		=Chapter 1 VPX-A5SoC Development Kit=

-	The VPX-A5SoC is a high-performance, reconfigurable 6U VPX card based on the Altera Arria V SOC FPGA. The FPGA is also embedded with dual-core ARM Cortex-A9 Processor running up to 1.05 GHz which can be used for control panel interfaces such as Ethernet,USB,SD Card and UART, etc. The board features up to 1 GB of DDR3 SDRAM as well as Flash memory for booting the FPGAs. The PCI Express ports x4 lanes in the VPX expansion plane, with up to PCI Express Gen2 (5Gbps) throughput offers a high performance interface to mainstream peripherals and I/O cards. Two VITA 57 FMC sites are provided for enhancing the board's I/O and processing capabilities. The A5-VPX-A5SoC is a powerful, feature-rich solution for the next generation of compute-intensive embedded applications.	+	The VPX-A5SoC is a high-performance, reconfigurable 6U VPX card based on the Altera Arria V SOC FPGA. The FPGA is also embedded with dual-core ARM Cortex-A9 Processor running up to 1.05 GHz which can be used for control panel interfaces such as Ethernet, USB, SD Card and UART, etc. The board features up to 1 GB of DDR3 SDRAM as well as Flash memory for booting the FPGAs. The PCI Express ports x4 lanes in the VPX expansion plane, with up to PCI Express Gen2 (5Gbps) throughput offers a high performance interface to mainstream peripherals and I/O cards. Two VITA 57 FMC sites are provided for enhancing the board's I/O and processing capabilities. The A5-VPX-A5SoC is a powerful, feature-rich solution for the next generation of compute-intensive embedded applications.

	[[File:6U-VPX 45.jpg\|600px]]		[[File:6U-VPX 45.jpg\|600px]]

Bingxia: /* 2.1 Layout and Components */

2017-07-06T01:26:28Z

2.1 Layout and Components

← Older revision		Revision as of 01:26, 6 July 2017
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	*FPGA		*FPGA
	**EPCQ for AS-Mode FPGA configure		**EPCQ for AS-Mode FPGA configure
-	**Two FMC ~~Connector~~,each support transceiver x8	+	**Two FMC Connectors,each support transceiver x8
	**1GB DDR3 with ECC(40-bits data bus),can be extended to 2GB DDR3 by replacing with double-sized ddr3 chip		**1GB DDR3 with ECC(40-bits data bus),can be extended to 2GB DDR3 by replacing with double-sized ddr3 chip
	**SFP x1 connector(xcvr x1) and one differential programmable clock generator(Si570)		**SFP x1 connector(xcvr x1) and one differential programmable clock generator(Si570)
-	**User ~~LEDx4~~,~~KEYx4~~,~~Switch~~ x4,User Bracket ~~LED~~ x4	+	**User LEDs x4,KEYs x4,Switches x4,User Bracket LEDs x4
	*VPX P0: JTAG,SYSRESET,NVMRO,REF_CLK,RES_BUS(1 PPS),GA0/1/2/3/4,GAP,SM0/1/2/3(SM Bus)		*VPX P0: JTAG,SYSRESET,NVMRO,REF_CLK,RES_BUS(1 PPS),GA0/1/2/3/4,GAP,SM0/1/2/3(SM Bus)
	**VPX P1: SYS_CON,P1-SE7(MaskableReset),one PCIe Gen2 x4		**VPX P1: SYS_CON,P1-SE7(MaskableReset),one PCIe Gen2 x4
Line 59:		Line 59:
	**microSD Socket(eMCC shared Bus, DNI)		**microSD Socket(eMCC shared Bus, DNI)
	**RTC(Power by system power or VPX P0 3.3-AUX with Auto switching)		**RTC(Power by system power or VPX P0 3.3-AUX with Auto switching)
-	**User ~~LED~~ x4,~~KEY~~ x4,~~Switch~~ x4	+	**User LEDs x4,KEYs x4,Switches x4
	**Giga Ethernet PHY: Switchable to VPX or Front RJ45		**Giga Ethernet PHY: Switchable to VPX or Front RJ45
	**USB 2.0 OTG PHY: Switchable to VPX or Front micro-AB USB connector		**USB 2.0 OTG PHY: Switchable to VPX or Front micro-AB USB connector

Bingxia: /* 2.1 Layout and Components */

2017-07-06T01:24:49Z

2.1 Layout and Components

← Older revision		Revision as of 01:24, 6 July 2017
Line 40:		Line 40:

	<br/>The VPX-A5SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.		<br/>The VPX-A5SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.
-	<br/>The following ~~hardware is~~ provided on the board:	+	<br/>The following hardwares are provided on the board:
	*FPGA		*FPGA
	**EPCQ for AS-Mode FPGA configure		**EPCQ for AS-Mode FPGA configure

Bingxia: /* Chapter 1 VPX-A5SoC Development Kit */

2017-07-06T01:20:50Z

Chapter 1 VPX-A5SoC Development Kit

← Older revision		Revision as of 01:20, 6 July 2017
Line 1:		Line 1:
	=Chapter 1 VPX-A5SoC Development Kit=		=Chapter 1 VPX-A5SoC Development Kit=

-	The VPX-A5SoC is a high-performance, reconfigurable 6U VPX card based on the Altera Arria V SOC FPGA. The FPGA is also ~~embeded~~ with dual-core ARM Cortex-A9 Processor running up to 1.05 GHz which can be used for control ~~plane~~ interfaces such as ~~Ethenet~~, USB , SD Card and UART, etc. The board features up to 1 GB of DDR3 SDRAM as well as Flash memory for booting the FPGAs. The PCI Express ports x4 lanes in the VPX expansion plane, with up to PCI Express Gen2 (5Gbps) throughput offers a high performance interface to mainstream peripherals and	+	The VPX-A5SoC is a high-performance, reconfigurable 6U VPX card based on the Altera Arria V SOC FPGA. The FPGA is also embedded with dual-core ARM Cortex-A9 Processor running up to 1.05 GHz which can be used for control panel interfaces such as Ethernet,USB,SD Card and UART, etc. The board features up to 1 GB of DDR3 SDRAM as well as Flash memory for booting the FPGAs. The PCI Express ports x4 lanes in the VPX expansion plane, with up to PCI Express Gen2 (5Gbps) throughput offers a high performance interface to mainstream peripherals and I/O cards. Two VITA 57 FMC sites are provided for enhancing the board's I/O and processing capabilities. The A5-VPX-A5SoC is a powerful, feature-rich solution for the next generation of compute-intensive embedded applications.
-	I/O cards. ~~Tow~~ VITA 57 FMC sites are provided for enhancing the board's I/O and processing capabilities. The A5-VPX-A5SoC is a powerful, feature-rich solution for the next generation of compute-intensive embedded applications.	+

	[[File:6U-VPX 45.jpg\|600px]]		[[File:6U-VPX 45.jpg\|600px]]
Line 12:		Line 11:
	*TBD		*TBD
	== 1.2 VPX-A5SoC System CD==		== 1.2 VPX-A5SoC System CD==
-	The 6U-VPX System CD contains all the documents and supporting materials associated with 6U-VPX, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://6U-VPX.terasic.com/cd.	+	The 6U-VPX System CD contains all the documents and supporting materials associated with 6U-VPX, including the user manual, system builder, reference designs and device datasheets. Users can download this system CD from the link: http://6U-VPX.terasic.com/cd.

	== 1.3 Getting Help ==		== 1.3 Getting Help ==

Bingxia: /* 1.2 Package Contents */

2017-07-05T02:33:26Z

1.2 Package Contents

← Older revision		Revision as of 02:33, 5 July 2017
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	*Quick Start Guide		*Quick Start Guide
	*TBD		*TBD
-	== 1.2 ~~Package Contents~~==	+	== 1.2 VPX-A5SoC System CD==
	The 6U-VPX System CD contains all the documents and supporting materials associated with 6U-VPX, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://6U-VPX.terasic.com/cd.		The 6U-VPX System CD contains all the documents and supporting materials associated with 6U-VPX, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://6U-VPX.terasic.com/cd.
		+
	== 1.3 Getting Help ==		== 1.3 Getting Help ==
	Here are the addresses where you can get help if you encounter any problems:		Here are the addresses where you can get help if you encounter any problems:

Bingxia: /* 2.2 Block Diagram of the VPX-A5SoC Board */

2017-07-05T01:30:30Z

2.2 Block Diagram of the VPX-A5SoC Board

← Older revision		Revision as of 01:30, 5 July 2017
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	Arria V SOC FPGA device to provide maximum flexibility for users.<br/>Users can configure the		Arria V SOC FPGA device to provide maximum flexibility for users.<br/>Users can configure the
	FPGA to implement any system design.<br/>		FPGA to implement any system design.<br/>
-	[[File:~~Block diagram Richard~~.jpg\|900px]]	+	[[File:QQ截图20170705092457.jpg\|900px]]

	Figure 2-3 Block diagram of VPX-A5SoC		Figure 2-3 Block diagram of VPX-A5SoC

Bingxia: /* 2.1 Layout and Components */

2017-06-19T02:46:28Z

2.1 Layout and Components

← Older revision		Revision as of 02:46, 19 June 2017
Line 44:		Line 44:
	**EPCQ for AS-Mode FPGA configure		**EPCQ for AS-Mode FPGA configure
	**Two FMC Connector,each support transceiver x8		**Two FMC Connector,each support transceiver x8
-	**1GB DDR3 with ECC(40-bits data bus);can be extended to 2GB DDR3 by replacing with double-sized ddr3 chip	+	**1GB DDR3 with ECC(40-bits data bus),can be extended to 2GB DDR3 by replacing with double-sized ddr3 chip
	**SFP x1 connector(xcvr x1) and one differential programmable clock generator(Si570)		**SFP x1 connector(xcvr x1) and one differential programmable clock generator(Si570)
	**User LEDx4,KEYx4,Switch x4,User Bracket LED x4		**User LEDx4,KEYx4,Switch x4,User Bracket LED x4
Line 55:		Line 55:
	**CSEL[1:0] and BSEL[2:0](DNI,CSEL default 00,BSEL=101 default boot from sdcard)		**CSEL[1:0] and BSEL[2:0](DNI,CSEL default 00,BSEL=101 default boot from sdcard)
	**Two single-ended 25MHz clock source for HPS(Si5338)		**Two single-ended 25MHz clock source for HPS(Si5338)
-	**1GB DDR3 with ECC(40-bits data bus);can be extended to 2GB DDR3 by replacing with double size ddr3 chip	+	**1GB DDR3 with ECC(40-bits data bus),can be extended to 2GB DDR3 by replacing with double size ddr3 chip
	**512 Mbits QSPI Flash(for HPS configure,P/N N25Q512A83GSF40F)		**512 Mbits QSPI Flash(for HPS configure,P/N N25Q512A83GSF40F)
	**microSD Socket(eMCC shared Bus, DNI)		**microSD Socket(eMCC shared Bus, DNI)

Bingxia: /* 2.2 Block Diagram of the VPX-A5SoC Board */

2017-06-19T02:20:29Z

2.2 Block Diagram of the VPX-A5SoC Board

← Older revision		Revision as of 02:20, 19 June 2017
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	*One SFP connector		*One SFP connector

-	Switches, Buttons, and Indicators	+	Switches, Buttons and Indicators
	*8 user Keys (FPGA x4, HPS x4)		*8 user Keys (FPGA x4, HPS x4)
	*8 user switches (FPGA x4, HPS x4)		*8 user switches (FPGA x4, HPS x4)

Bingxia: /* 2.2 Block Diagram of the VPX-A5SoC Board */

2017-06-16T09:41:02Z

2.2 Block Diagram of the VPX-A5SoC Board

← Older revision		Revision as of 09:41, 16 June 2017
Line 72:		Line 72:

	Figure 2-3 Block diagram of VPX-A5SoC		Figure 2-3 Block diagram of VPX-A5SoC
		+

	Detailed information about Figure 2-3 are listed below.		Detailed information about Figure 2-3 are listed below.