Terasic USB Blaster revB Manual
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The Intel FPGA , Serial configuration device and host systems that UBT supported are list in Table 1-1, Table 1-2 and Table 1-3 | The Intel FPGA , Serial configuration device and host systems that UBT supported are list in Table 1-1, Table 1-2 and Table 1-3 | ||
| + | |||
| + | {| class="wikitable" border="1" | ||
| + | |- bgcolor=#01A9FF | ||
| + | !FPGA Serie | ||
| + | !Deivce | ||
| + | |- | ||
| + | ||'''Stratix''' Series | ||
| + | ||Stratix 10, Stratix V, Stratix IV, Stratix III, Stratix II GX and Stratix GX | ||
| + | |- | ||
| + | ||'''Arria''' Series | ||
| + | ||Arria 10, Arria V, Arria II, Arria GX | ||
| + | |- | ||
| + | |- | ||
| + | ||'''Cyclone''' Series | ||
| + | ||Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II, Cyclone | ||
| + | |- | ||
| + | |- | ||
| + | ||'''MAX''' series | ||
| + | ||MAX10,MAX V, MAXII , MAX3000, MAX7000 and MAX9000 | ||
| + | |- | ||
| + | |- | ||
| + | ||Other | ||
| + | ||FLEX10K, ACEX1K, APEX 20K | ||
| + | |- | ||
| + | |} | ||
Revision as of 14:24, 17 December 2019
Introduction
The Terasic USB Blaster Download Cable(UBT) interfaces a USB port on a host computer to an FPGA mounted on a printed circuit board. The cable sends configuration data from the host computer to a standard 10-pin header connected to the FPGA. You can use the UBT to iteratively download configuration data to a system during prototyping or to program data into the system during production.
Supported Devices and Host System
The Intel FPGA , Serial configuration device and host systems that UBT supported are list in Table 1-1, Table 1-2 and Table 1-3
| FPGA Serie | Deivce |
|---|---|
| Stratix Series | Stratix 10, Stratix V, Stratix IV, Stratix III, Stratix II GX and Stratix GX |
| Arria Series | Arria 10, Arria V, Arria II, Arria GX |
| Cyclone Series | Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II, Cyclone |
| MAX series | MAX10,MAX V, MAXII , MAX3000, MAX7000 and MAX9000 |
| Other | FLEX10K, ACEX1K, APEX 20K |
