Terasic Host FPGA Board
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== High Profile PCIe Board == | == High Profile PCIe Board == | ||
| + | *[[Mercury_A2700_Accelerator_Cardt_TopPage|Mercury A2700 Accelerator Card(MA27)]] | ||
| + | *[[Agilex_7_FPGA_Starter_Kit_TopPage|Agilex 7 FPGA Starter Kit(A7SK)]] | ||
*[[DE10-Agilex_TopPage|DE10-Agilex]] | *[[DE10-Agilex_TopPage|DE10-Agilex]] | ||
*[[DE10-Pro_TopPage|DE10-Pro]] | *[[DE10-Pro_TopPage|DE10-Pro]] | ||
| Line 24: | Line 26: | ||
*[[Apollo_S10_SoM_TopPage|Apollo_S10_SoM]] | *[[Apollo_S10_SoM_TopPage|Apollo_S10_SoM]] | ||
*[[Apollo_Agilex_SoM_TopPage|Apollo_Agilex_SoM]] | *[[Apollo_Agilex_SoM_TopPage|Apollo_Agilex_SoM]] | ||
| + | *[[Atum_A5_Development_Kit_TopPage|Atum A5 Development Kit]] | ||
| + | *[[DE25-Standard_TopPage|DE25-Standard]] | ||
== ASIC Prototyping Board == | == ASIC Prototyping Board == | ||
| Line 38: | Line 42: | ||
*[[DE10-Lite_TopPage|DE10-Lite]] | *[[DE10-Lite_TopPage|DE10-Lite]] | ||
*[[DE-Core_TopPage|T-Core]] | *[[DE-Core_TopPage|T-Core]] | ||
| + | *[[DE23-Lite_TopPage|DE23-Lite]] | ||
== Multi-Media Platform == | == Multi-Media Platform == | ||
*[[VEEK-MT2S_TopPage|VEEK-MT2S]] | *[[VEEK-MT2S_TopPage|VEEK-MT2S]] | ||
Latest revision as of 14:21, 3 November 2025
Contents |
High Profile PCIe Board
- Mercury A2700 Accelerator Card(MA27)
- Agilex 7 FPGA Starter Kit(A7SK)
- DE10-Agilex
- DE10-Pro
- DE5a-NET
- DE5a-NET-DDR4
- DE5-NET
- DE4
- TR10a-HL
- TR10a-HL2
- TR10a-LPQ
- HERO
SoC Platform (With ARM or ATOM Processor)
- VPX-A5SOC
- HAN Pilot Platform
- TSoM
- Apollo_S10_SoM
- Apollo_Agilex_SoM
- Atum A5 Development Kit
- DE25-Standard
