Terasic USB Blaster III Manual

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The UBT3 connects the Host and the FPGA on the user's board through the USB Port and 10-Pin cable. At the same time, it can support several target board voltage standards, allowing UBT3 to be widely used in various FPGA boards.
The UBT3 connects the Host and the FPGA on the user's board through the USB Port and 10-Pin cable. At the same time, it can support several target board voltage standards, allowing UBT3 to be widely used in various FPGA boards.
-
= Supported Devices and Host System =
+
= Supported Devices, Host System and Software =
The Intel FPGA , Serial  configuration device and host systems that UBT3 supported are list in Table 1-1, Table 1-2 and Table 1-3
The Intel FPGA , Serial  configuration device and host systems that UBT3 supported are list in Table 1-1, Table 1-2 and Table 1-3
-
<div style="">        '''Table 1‑1 Supported Intel FPGA Devices'''</div>
+
<div style="">        '''Table 1‑1 Supported Altera FPGA Devices'''</div>
{| class="" border="1"
{| class="" border="1"
                                 |- bgcolor=#00A9FF
                                 |- bgcolor=#00A9FF
-
                               !FPGA Serie
+
                               !FPGA Series
!Deivce
!Deivce
|-
|-
-
||'''Stratix'''  Series
+
||'''Agilex'''  Series
-
||Stratix 10, Stratix V, Stratix IV, Stratix III, Stratix II GX and Stratix GX    
+
||Agilex 3, Agilex 5, Agilex 7, Agilex 9    
|-
|-
||'''Stratix'''  Series
||'''Stratix'''  Series
-
||Stratix 10, Stratix V, Stratix IV, Stratix III, Stratix II GX and Stratix GX
+
||Stratix 10, Stratix V, Stratix IV, Stratix III
|-   
|-   
||'''Arria'''  Series
||'''Arria'''  Series
-
||Arria 10, Arria V, Arria II,  Arria GX
+
||Arria 10, Arria V
|-
|-
|-
|-
||'''Cyclone'''  Series
||'''Cyclone'''  Series
-
||Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II, Cyclone
+
||Cyclone 10 GX, Cyclone 10 LP, Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II
|-
|-
|-
|-
||'''MAX''' series
||'''MAX''' series
-
||MAX10,MAX V, MAXII , MAX3000, MAX7000 and MAX9000
+
||MAX 10, MAX V, MAX II
-
|-
+
-
|-
+
-
||Other
+
-
||FLEX10K, ACEX1K, APEX 20K
+
|-
|-
|}
|}
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{| class="" border="1"
{| class="" border="1"
                                 |- bgcolor=#00A9FF
                                 |- bgcolor=#00A9FF
-
  !FPGA Serie  
+
  !Serial Flash Series  
|-
|-
-
||EPCS devices
+
||EPCQA devices
|-
|-
-
||EPCQ devices
 
|-
|-
-
||EPCQ-L devices
+
||Micron MT25QL devices
 +
|-
 +
|-
 +
||Micron MT25QU devices
 +
|-
 +
|-
 +
||Macronix MX25L devices
 +
|-
 +
|-
 +
||Macronix MX25U devices
 +
|-
 +
|-
 +
||Macronix MX66U devices
 +
|-
 +
|-
 +
||Infineon S25FL devices
|-
|-
|}
|}
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  !Host System   
  !Host System   
|-
|-
-
||Window
+
||Window 10/11 (64-bit)
|-
|-
||Linux
||Linux
 +
|-
 +
|}
 +
 +
 +
<div style="">        '''Table 1‑4 Supported Quartus software'''</div>
 +
 +
{| class="" border="1"
 +
                                |- bgcolor=#00A9FF
 +
!Quartus software 
 +
|-
 +
||Quartus® Prime version 25.1 or later
|-
|-
|}
|}
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= Operating Conditions =
= Operating Conditions =
-
UBT can support several voltage standard of the target board. Table 1-4 shows the supported voltage.
+
UBT3 can support several voltage standard of the target board. Table 1-5 shows the supported voltage.
-
Users need to pay attention to whether the JTAG voltage standard of the target board is within the range of Table 1-4.
+
Users need to pay attention to whether the JTAG voltage standard of the target board is within the range of Table 1-5.
-
<div style="">        '''Table 1‑4 Support Target board supply voltage'''</div>
+
<div style="">        '''Table 1‑5 Support Target board supply voltage'''</div>
{| class="" border="1"
{| class="" border="1"
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  !Support Target board supply voltage  
  !Support Target board supply voltage  
|-
|-
-
||1.2V <span style="color:#00f000;"> '''(*1)''' </span>
+
||1.2V  
|-
|-
-
||1.5V <span style="color:#00f000;"> '''(*1)''' </span>
+
||1.5V  
|-
|-
-
||1.8V <span style="color:#00f000;"> '''(*1)''' </span>
+
||1.8V
|-
|-
||2.5V  
||2.5V  
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|-
|-
|}
|}
-
 
-
<span style="color:#00f000;"> '''(*1) Only Rev .B can support .''' </span>
 
=Pin define=
=Pin define=
-
The following picture and table list the pins of the Terasic Download Cable female plug and
+
The following picture and table list the pins of the Terasic UBT3 Download Cable female plug and
-
describes their functions in the JTAG and passive serial modes.
+
describes their functions in the JTAG and Active Serial modes.
-
[[File:Ubt pin define.jpg]]
+
[[File:Ubt3 pin define.png|200px]]
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!Pin Define
!Pin Define
!JTAG Mode Descriptions
!JTAG Mode Descriptions
-
!PS Mode Descriptions
+
!AS Mode Descriptions
|-
|-
||1
||1
-
||TRGTCK
+
||TCK
||Clock signal
||Clock signal
||Clock signal
||Clock signal
Line 119: Line 138:
|-
|-
||3
||3
-
||TRGTDO
+
||TDO
-
||Data from
+
||Test data output
||Configuration done
||Configuration done
|-
|-
||4
||4
||TRGVCC
||TRGVCC
-
||Target power supplied by the device board
+
||Target power supply
-
||Target power supplied by the device board
+
||Target power supply
|-
|-
||5
||5
-
||TRGTMS
+
||TMS
-
||JTAG state machine control.
+
||Test mode select input
-
||Configuration control.
+
||Configuration control
|-
|-
||6
||6
-
||TRGNCE
+
||PROC_RST
-
||-
+
||Processor reset
-
||-
+
||Target chip enable
|-
|-
||7
||7
-
||TRGNST
 
||-
||-
-
||Active serial data out
+
||-
 +
||-
|-
|-
||8
||8
-
||TRGNCSO
+
||TRST
-
||-
+
||Test reset
||Serial configuration device chip select
||Serial configuration device chip select
|-
|-
||9
||9
-
||TRGASDO
+
||TDI
-
||Data to device.
+
||Test data input
||Active serial data in
||Active serial data in
|-
|-
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|}
|}
-
=Dimension of the Terasic USB Download Cable =
+
=Dimension of the Terasic USB Blaster III Download Cable =
[[File:800px-Ubt dimension.jpg|600px]]
[[File:800px-Ubt dimension.jpg|600px]]
-
=Using the Terasic USB Download Cable=
+
=Using the Terasic USB Blaster III Download Cable=
-
To start using the Intel FPGA Download Cable, user need to install the drivers on your
+
To start using the USB Blaster III Download Cable, user need to install the drivers on your
-
system and set up the hardware in the Intel Quartus® Prime software.  
+
system and set up the hardware in the Altera Quartus® Prime software.  
To program or configure the device, connect the host system to the device board using
To program or configure the device, connect the host system to the device board using
-
the Terasic Download Cable and initiate the programming or configuration using
+
the Terasic USB Blaster III Download Cable and initiate the programming or configuration using
-
the Intel Quartus Prime Programmer. You can also use the cable with the Intel Quartus
+
the Altera Quartus Prime Programmer. You can also use the cable with the Quartus
-
Prime Signal Tap Logic Analyzer for logic analysis.
+
Prime Signal Tap Logic Analyzer for logic analysis. It also can be used with JTAG and debug tools supported by the JTAG server such as System Console, Nios® V debugger.
-
 
+
*Install the Driver for windows
*Install the Driver for windows

Latest revision as of 15:13, 24 August 2026

Contents

Introduction

The main function of the Terasic USB Blaster III Download Cable (UBT3) is to allow users to download configuration data to the system during prototype development, or to program data into the system during production. The UBT3 connects the Host and the FPGA on the user's board through the USB Port and 10-Pin cable. At the same time, it can support several target board voltage standards, allowing UBT3 to be widely used in various FPGA boards.

Supported Devices, Host System and Software

The Intel FPGA , Serial configuration device and host systems that UBT3 supported are list in Table 1-1, Table 1-2 and Table 1-3


Table 1‑1 Supported Altera FPGA Devices
FPGA Series Deivce
Agilex Series Agilex 3, Agilex 5, Agilex 7, Agilex 9
Stratix Series Stratix 10, Stratix V, Stratix IV, Stratix III
Arria Series Arria 10, Arria V
Cyclone Series Cyclone 10 GX, Cyclone 10 LP, Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II
MAX series MAX 10, MAX V, MAX II


Table 1‑2 Supported Serial Configuration Device
Serial Flash Series
EPCQA devices
Micron MT25QL devices
Micron MT25QU devices
Macronix MX25L devices
Macronix MX25U devices
Macronix MX66U devices
Infineon S25FL devices


Table 1‑3 Supported Operation System
Host System
Window 10/11 (64-bit)
Linux


Table 1‑4 Supported Quartus software
Quartus software
Quartus® Prime version 25.1 or later

Operating Conditions

UBT3 can support several voltage standard of the target board. Table 1-5 shows the supported voltage. Users need to pay attention to whether the JTAG voltage standard of the target board is within the range of Table 1-5.

Table 1‑5 Support Target board supply voltage
Support Target board supply voltage
1.2V
1.5V
1.8V
2.5V
3.3V

Pin define

The following picture and table list the pins of the Terasic UBT3 Download Cable female plug and describes their functions in the JTAG and Active Serial modes.


Ubt3 pin define.png


Pin Number Pin Define JTAG Mode Descriptions AS Mode Descriptions
1 TCK Clock signal Clock signal
2 GND Signal ground Signal ground
3 TDO Test data output Configuration done
4 TRGVCC Target power supply Target power supply
5 TMS Test mode select input Configuration control
6 PROC_RST Processor reset Target chip enable
7 - - -
8 TRST Test reset Serial configuration device chip select
9 TDI Test data input Active serial data in
10 GND Signal ground. Signal ground

Dimension of the Terasic USB Blaster III Download Cable

800px-Ubt dimension.jpg

Using the Terasic USB Blaster III Download Cable

To start using the USB Blaster III Download Cable, user need to install the drivers on your system and set up the hardware in the Altera Quartus® Prime software.

To program or configure the device, connect the host system to the device board using the Terasic USB Blaster III Download Cable and initiate the programming or configuration using the Altera Quartus Prime Programmer. You can also use the cable with the Quartus Prime Signal Tap Logic Analyzer for logic analysis. It also can be used with JTAG and debug tools supported by the JTAG server such as System Console, Nios® V debugger.

  • Install the Driver for windows

Altera_USB_Blaster_Driver_Installation_Instructions

  • Install the driver for Linux

Using USB Blaster Under Linux

USB Blaster Self Test

This section describes users how to test whether the on-board USB blaster or USB blaster cable is properly installed and operated

  1. Power on the FPGA board and connect USB blaster port or USB blaster cable to PC.
    Check if the Universal Serial Bus controllers in the Windows Device Manager has an Altera USB Blaster.
    If yes, users can use Quartus programmer and download FPGA code.
    Device Manger.png

  2. If Altera USB Blaster isn’t showed in Universal Serial Bus controllers, please check whether the Other devices has Unknown device.
    If yes, please install the USB blaster driver refer to this link:Altera USB Blaster Driver Installation Instructions
    Device Manger2.png.

  3. If no Unknown device:
i.Make sure the board power is on and the port on board which connected to PC is USB blaster port.
ii.If step i is OK:
a.Test with another PC to see if the OS can detect unknown device.
b.Test with another usb blaster cable.
Usb cable.png
c.If still with the same problem, please contact our technical support team via support@terasic.com and provide below information:
  • PC OS version: Win10-32bit or Win7-64bit or Linux-64bit.
  • Whether you tested follow the above processes.
  • The Quartus version you installed: Q16.1 or others.

FAQ

1. Q：What is the difference between UBT and AUB2?

A: The main difference is the JTAG circuit, the UBT(USB Blaster Download Cable) supports USB Blaster I circuit and JTAG Voltage: 2.5V ~ 3.3V. The AUB2 (USB-Blaster II Download Cable) supports USB Blaster II circuit and JTAG Voltage: 5.0-V TTL, 3.3-V LVTTL/LVCMOS ,Single-ended I/O standards from 1.5 V to 3.3 V.

Customers can refer to Intel Cyclone 10 LP device handbook: https://www.intel.com/content/www/us/en/programmable/documentation/sxm1481253171919.html?wapkw=cyclone+10+lp+handbook and check your board JTAG voltage to see which cable is compatible with their board.


2. Q: What is the TCK Clock Frequency for UBT and AUB2 respectively?

A: The USB Blaster Cable works with the Jtag clock 6M, while the USB Blaster II Cable works at 24M.


3. Q: What is the difference between the UBT and Altera USB Blaster Download Cable (UBA)?

A: The main difference is the JTAG circuit, Terasic UBT supports JTAG voltage 2.5v~3.3V, the Altera USB Blaster supports 1.8V~3.3V, they are compatible with other features.

Please note that UBT can't detect the JTAG chain on the Intel Arria 10 GX FPGA Development Kit.


4. Q: What is the operating temperature specification of the UBT?

A:The UBT is designed to operate in the commercial temperature range (0 to 85C).


5.Q: Will USB-Blaster work under Windows 10 64-bit?

A: Yes, the USB-Blaster work under Windows 10 64-bit. And you can use either of the Quartus software version later than 10.1 to work with the Windows 10 64-bit.


6. Q: When I used the UBT to download the .pof file to the MA10 device (for self-designed board), it failed and reported the following errors, why did this happen? Ubt download error.jpeg

A:It may be caused by the MAX10 device. Customer can try to download the .sof file to the MAX 10 device first, then download the pof file into the device with the board keeping powering on.

7.Q: How long is the UBT?

A: It is about two meters.

8. Q: I can the UBT to download the .pof file to his own board under Quartus II 11.0SP1 successfully，however, when he checked the Verify tab, it failed to download and reported that "verification failed for device number 1" ,how should I solve the problem?

A: You can try the following approaches to solve this problem:

1. Uninstall the current usb blaster driver, then try to update the driver to the higher version, such as usb blaster driver for 17.1 or later version.

2. If it is impossible to update the usb blaster driver ,we recommend you to modify the JTAG circuit on your board, and adjust the pull-up resistor of TCK TMS to modify jtag timing.

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