Terasic Host FPGA Board

From Terasic Wiki

Revision as of 17:55, 24 November 2017 (view source) Dongliu (Talk | contribs) ← Older edit		Revision as of 10:27, 3 April 2018 (view source) Admin (Talk | contribs) Newer edit →
Line 30:		Line 30:
	== Multi-Media Platform ==		== Multi-Media Platform ==
	*[[VEEK-MT2S_TopPage|VEEK-MT2S]]		*[[VEEK-MT2S_TopPage|VEEK-MT2S]]
		+
		+	== Robot ==
		+	*[[Self_Balancing_Robot_TopPage|Self_Balancing_Robot]]

---

Revision as of 10:27, 3 April 2018

Contents 1 High Profile PCIe Board 2 SoC Platform (With ARM or ATOM Processor) 3 ASIC Prototyping Board 4 Classic FPGA Development Board 5 Multi-Media Platform 6 Robot

High Profile PCIe Board

• DE5a-NET
• DE5-NET
• DE4

SoC Platform (With ARM or ATOM Processor)

• DE10-Standard
• DE10-Nano
• DE0-Nano-SOC/Atlas-SoC
• DE1-SoC
• SoCKit

• VPX-A5SOC
• DE10-Advanced

ASIC Prototyping Board

• TR5
• TR4
• Altera Arria V GX Starter Kit(A5SK)
• Cyclone V GT FPGA Development Kit(C5GT)

Classic FPGA Development Board

• DE2-115
• DE0-Nano
• DE10-Lite

Multi-Media Platform

• VEEK-MT2S

Robot

• Self_Balancing_Robot