DE10-Standard Reference FAQ
From Terasic Wiki
(Difference between revisions)
Bingxia (Talk | contribs)
(Created page with "*<font size="3"><font face="Times New Roman">Q：Why the FPGA side using SDRAM instead of DDR3?</font></font><br/><font size="3"><font face="Times New Roman">A：DE10-Standard is...")
Newer edit →
(Created page with "*<font size="3"><font face="Times New Roman">Q：Why the FPGA side using SDRAM instead of DDR3?</font></font><br/><font size="3"><font face="Times New Roman">A：DE10-Standard is...")
Newer edit →
Revision as of 15:37, 7 June 2017
- Q：Why the FPGA side using SDRAM instead of DDR3?
A：DE10-Standard is mostly for colleges, the board has six 7-segment dispalys, ten slide switches, 4 push-buttons and so on, so no pins assigned for DDR3.
- Q：Why DE10-Standard equipped with Cyclone V SX FPGA, but no transceiver on HSMC?
A： It requires fitted clock gen if add transceiver on HSMC, also more PCB material is needed and cost will increase, consider that most of users won't use transceiver, so the board isn't implement the transceiver.
Back
