From Terasic Wiki

Contents 1 Introduction 2 Supported Devices and Host System 3 Operating Conditions 4 Pin define

Introduction

The main function of the Terasic USB Blaster Download Cable (UBT) is to allow users to download configuration data to the system during prototype development, or to program data into the system during production. The UBT connects the Host and the FPGA on the user's board through the USB Port and 10-Pin cable. At the same time, it can support several target board voltage standards, allowing UBT to be widely used in various FPGA boards.

Supported Devices and Host System

The Intel FPGA , Serial configuration device and host systems that UBT supported are list in Table 1-1, Table 1-2 and Table 1-3

FPGA Serie	Deivce
Stratix Series	Stratix 10, Stratix V, Stratix IV, Stratix III, Stratix II GX and Stratix GX
Arria Series	Arria 10, Arria V, Arria II, Arria GX
Cyclone Series	Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II, Cyclone
MAX series	MAX10,MAX V, MAXII , MAX3000, MAX7000 and MAX9000
Other	FLEX10K, ACEX1K, APEX 20K

FPGA Serie
EPCS devices
EPCQ devices
EPCQ-L devices

Host System
Window
Linux

Operating Conditions

UBT can support several voltage standard of the target board. Table 1-4 shows the supported voltage. Users need to pay attention to whether the JTAG voltage standard of the Targer board is within the range of Table 1-4.

Support Target board supply voltage
1.2V (*1)
1.5V (*1)
1.8V (*1)
2.5V
3.3V

(*1) Only Rev .B can supoort .

Pin define

Pin Number	Pin Define	JTAG Mode Descriptions	PS Mode Descriptions
1	TRGTCK	Clock signal	Clock signal
2	GND	Signal ground	Signal ground
3	TRGTDO	Data from	Configuration done
4	TRGVCC	Target power supplied by the device board	Target power supplied by the device board
5	TRGTMS	JTAG state machine control.	Configuration control.
6	TRGNCE	-	-
7	TRGNST	-	Active serial data out
8	TRGNCSO	-	Serial configuration device chip select
9	TRGASDO	Data to device.	Active serial data in
10	GND	Signal ground.	Signal ground