DE10-Advanced revC demo: PCI Express Library API
From Terasic Wiki
(Difference between revisions)
(→1) |
|||
Line 166: | Line 166: | ||
=1= | =1= | ||
* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Read8'''</div> | * <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Read8'''</div> | ||
- | |||
- | |||
- | |||
{| style="border-spacing:0;width:15.251cm;" | {| style="border-spacing:0;width:15.251cm;" | ||
Line 178: | Line 175: | ||
|| '''Prototype:''' | || '''Prototype:''' | ||
- | bool PCIE_Read8( | + | :bool PCIE_Read8( |
- | PCIE_HANDLE hPCIE, | + | :PCIE_HANDLE hPCIE, |
- | PCIE_BAR PcieBar, | + | :PCIE_BAR PcieBar, |
- | PCIE_ADDRESS PcieAddress, | + | :PCIE_ADDRESS PcieAddress, |
- | uint8_t *pByte); | + | :uint8_t *pByte); |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Parameters:''' | || '''Parameters:''' | ||
- | hPCIE: | + | :hPCIE: |
- | A PCIe handle return by PCIE_Open function. | + | ::A PCIe handle return by PCIE_Open function. |
- | PcieBar: | + | :PcieBar: |
- | Specify the target BAR. | + | ::Specify the target BAR. |
- | PcieAddress: | + | :PcieAddress: |
- | Specify the target address in FPGA. | + | ::Specify the target address in FPGA. |
- | pByte: | + | :pByte: |
- | A buffer to retrieve the 8-bit data. | + | ::A buffer to retrieve the 8-bit data. |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Return Value:''' | || '''Return Value:''' | ||
- | Return '''true''' if read data is successful; otherwise '''false''' is returned. | + | :Return '''true''' if read data is successful; otherwise '''false''' is returned. |
|- | |- | ||
|} | |} | ||
<div style="margin-left:0cm;margin-right:0cm;"></div> | <div style="margin-left:0cm;margin-right:0cm;"></div> | ||
- | |||
- | |||
+ | * <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Write8'''</div> | ||
{| style="border-spacing:0;width:15.251cm;" | {| style="border-spacing:0;width:15.251cm;" | ||
Line 221: | Line 217: | ||
|| '''Function:''' | || '''Function:''' | ||
- | Write an 8-bit data to the FPGA Board. | + | :Write an 8-bit data to the FPGA Board. |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Prototype:''' | || '''Prototype:''' | ||
- | bool PCIE_Write8( | + | :bool PCIE_Write8( |
- | PCIE_HANDLE hPCIE, | + | :PCIE_HANDLE hPCIE, |
- | PCIE_BAR PcieBar, | + | :PCIE_BAR PcieBar, |
- | PCIE_ADDRESS PcieAddress, | + | :PCIE_ADDRESS PcieAddress, |
- | uint8_t Byte); | + | :uint8_t Byte); |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Parameters:''' | || '''Parameters:''' | ||
- | hPCIE: | + | :hPCIE: |
- | A PCIe handle return by PCIE_Open function. | + | ::A PCIe handle return by PCIE_Open function. |
- | PcieBar: | + | :PcieBar: |
- | Specify the target BAR. | + | ::Specify the target BAR. |
- | PcieAddress: | + | :PcieAddress: |
- | Specify the target address in FPGA. | + | ::Specify the target address in FPGA. |
- | Byte: | + | :Byte: |
- | Specify an 8-bit data which will be written to FPGA board. | + | ::Specify an 8-bit data which will be written to FPGA board. |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Return Value:''' | || '''Return Value:''' | ||
- | Return '''true''' if write data is successful; otherwise '''false''' is returned. | + | :Return '''true''' if write data is successful; otherwise '''false''' is returned. |
|- | |- | ||
|} | |} | ||
<div style="margin-left:0cm;margin-right:0cm;"></div> | <div style="margin-left:0cm;margin-right:0cm;"></div> | ||
- | |||
- | |||
+ | * <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_DmaRead'''</div> | ||
{| style="border-spacing:0;width:15.251cm;" | {| style="border-spacing:0;width:15.251cm;" | ||
Line 268: | Line 263: | ||
|| '''Function:''' | || '''Function:''' | ||
- | Read data from the memory-mapped memory of FPGA board in DMA. | + | :Read data from the memory-mapped memory of FPGA board in DMA. |
Maximal read size is (4GB-1) bytes. | Maximal read size is (4GB-1) bytes. | ||
Line 274: | Line 269: | ||
|| '''Prototype:''' | || '''Prototype:''' | ||
- | bool PCIE_DmaRead( | + | :bool PCIE_DmaRead( |
- | PCIE_HANDLE hPCIE, | + | ::PCIE_HANDLE hPCIE, |
- | PCIE_LOCAL_ADDRESS LocalAddress, | + | ::PCIE_LOCAL_ADDRESS LocalAddress, |
- | void *pBuffer, | + | ::void *pBuffer, |
- | uint32_t dwBufSize | + | ::uint32_t dwBufSize |
- | ); | + | :); |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Parameters:''' | || '''Parameters:''' | ||
- | hPCIE: | + | :hPCIE: |
- | A PCIe handle return by PCIE_Open function. | + | ::A PCIe handle return by PCIE_Open function. |
- | LocalAddress: | + | :LocalAddress: |
- | Specify the target memory-mapped address in FPGA. | + | ::Specify the target memory-mapped address in FPGA. |
- | pBuffer: | + | :pBuffer: |
- | A pointer to a memory buffer to retrieved the data from FPGA. The size of buffer should be equal or larger the dwBufSize. | + | ::A pointer to a memory buffer to retrieved the data from FPGA. The size of buffer should be equal or larger the dwBufSize. |
- | dwBufSize: | + | :dwBufSize: |
- | Specify the byte number of data retrieved from FPGA. | + | ::Specify the byte number of data retrieved from FPGA. |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Return Value:''' | || '''Return Value:''' | ||
Line 310: | Line 305: | ||
|} | |} | ||
<div style="margin-left:0cm;margin-right:0cm;"></div> | <div style="margin-left:0cm;margin-right:0cm;"></div> | ||
- | |||
- | |||
+ | * <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_DmaWrite'''</div> | ||
{| style="border-spacing:0;width:15.251cm;" | {| style="border-spacing:0;width:15.251cm;" | ||
Line 319: | Line 313: | ||
|| '''Function:''' | || '''Function:''' | ||
- | Write data to the memory-mapped memory of FPGA board in DMA. | + | :Write data to the memory-mapped memory of FPGA board in DMA. |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Prototype:''' | || '''Prototype:''' | ||
- | bool PCIE_DmaWrite( | + | :bool PCIE_DmaWrite( |
- | PCIE_HANDLE hPCIE, | + | ::PCIE_HANDLE hPCIE, |
- | PCIE_LOCAL_ADDRESS LocalAddress, | + | :PCIE_LOCAL_ADDRESS LocalAddress, |
- | void *pData, | + | :void *pData, |
- | uint32_t dwDataSize | + | ::uint32_t dwDataSize |
); | ); | ||
Line 337: | Line 331: | ||
|| '''Parameters:''' | || '''Parameters:''' | ||
- | hPCIE: | + | :hPCIE: |
- | A PCIe handle return by PCIE_Open function. | + | ::A PCIe handle return by PCIE_Open function. |
- | LocalAddress: | + | :LocalAddress: |
- | Specify the target memory mapped address in FPGA. | + | ::Specify the target memory mapped address in FPGA. |
- | pData: | + | :pData: |
- | A pointer to a memory buffer to store the data which will be written to FPGA. | + | ::A pointer to a memory buffer to store the data which will be written to FPGA. |
- | dwDataSize: | + | :dwDataSize: |
- | Specify the byte number of data which will be written to FPGA. | + | ::Specify the byte number of data which will be written to FPGA. |
|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | |- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;" | ||
|| '''Return Value:''' | || '''Return Value:''' | ||
Line 359: | Line 353: | ||
|} | |} | ||
* <div style="margin-left:0cm;margin-right:0cm;"></div> | * <div style="margin-left:0cm;margin-right:0cm;"></div> | ||
+ | |||
+ | =2= | ||
* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_ConfigRead32'''</div> | * <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_ConfigRead32'''</div> | ||
Revision as of 16:07, 27 August 2018
Below shows the exported API in the TERASIC_PCIE_AVMM.dll. The API prototype is defined in the TERASIC_PCIE_AVMM.h.
Note: the Linux library terasic_pcie_qsys.so also use the same API and header file.
Function:
|
Prototype:
|
Parameters:
|
Return Value:
|
Function:
|
Prototype:
void PCIE_Close(
|
Parameters:
|
Return Value:
|
- PCIE_Read32
Function:
|
Prototype:
|
Parameters:
|
Return Value:
|
- PCIE_Write32
Function:
|
Prototype:
uint32_t dwData); |
Parameters:
|
Return Value:
|
1
- PCIE_Read8
Function:
Read an 8-bit data from the FPGA board. |
Prototype:
|
Parameters:
|
Return Value:
|
- PCIE_Write8
Function:
|
Prototype:
|
Parameters:
|
Return Value:
|
- PCIE_DmaRead
Function:
Maximal read size is (4GB-1) bytes. |
Prototype:
|
Parameters:
|
Return Value:
Return true if read data is successful; otherwise false is returned. |
- PCIE_DmaWrite
Function:
|
Prototype:
); |
Parameters:
|
Return Value:
Return true if write data is successful; otherwise false is returned. |
2
- PCIE_ConfigRead32
Function:
Read PCIe Configuration Table. Read a 32-bit data by given a byte offset. |
Prototype:
bool PCIE_ConfigRead32 ( PCIE_HANDLE hPCIE, uint32_t Offset, uint32_t *pdwData ); |
Parameters:
hPCIE: A PCIe handle return by PCIE_Open function. Offset: Specify the target byte of offset in PCIe configuration table. pdwData: A 4-bytes buffer to retrieve the 32-bit data. |
Return Value:
Return true if read data is successful; otherwise false is returned.
|