DE10-Advanced revC demo: PCIe Reference Design - Fundamental

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<div style="color:#404040;">The folder includes following files:</div>
<div style="color:#404040;">The folder includes following files:</div>
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* FPGA Configuration File: PCIe_Fundamental.sof
* FPGA Configuration File: PCIe_Fundamental.sof
* Download Batch file: test.bat
* Download Batch file: test.bat
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=Demonstration Setup=
=Demonstration Setup=
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# Install the FPGA board on your PC as shown in [[#Figure73|Figure 7-3]].
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# Install the FPGA board on your PC as shown in [[#Figure73|Figure 1-1]].
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#:[[File:De10-advanced revc FPGA board connect to PC.jpg|600px]]
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#:
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#:::::'''Figure 1-1 FPGA board connect to PC'''
# Configure FPGA with PCIe_Fundamental.sof by executing the test.bat.
# Configure FPGA with PCIe_Fundamental.sof by executing the test.bat.
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# Install PCIe driver if necessary. The driver is located in the folder:
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# Install PCIe driver if necessary. The driver is located in the folder: CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver.
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# Restart Windows
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# Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in [[#Figure710|Figure 1-2]].
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#:[[Image: DE10-Advanced_revC_PCIE_pic_9.jpg|400px]]
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#:
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#:::::'''Figure 1-2 Screenshot for PCIe Driver'''
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#:
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# Goto windows_app folder, execute PCIE_FUNDAMENTAL.exe. A menu will appear as shown in [[#Figure711|Figure 1-3]].
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#:[[Image: DE10-Advanced_revC_PCIE_pic_10.png|700px]]
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#:
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#::::'''Figure 1-3 Screenshot of Program Menu'''
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# Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in [[#Figure712|Figure 1-4]]. If input 0 (hex 0x00), all led will be turn off.
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#:
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#:[[Image: DE10-Advanced_revC_PCIE_pic_11.png|700px]]
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#:
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#:::'''Figure 1-4 Screenshot of LED Control'''
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# Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in [[#Figure713|Figure 1-5]].
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#:[[Image: DE10-Advanced_revC_PCIE_pic_12.png|700px]]
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#:
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#:::::'''Figure 1-5 Screenshot of Button Status Report'''
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# Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in [[#Figure714|Figure 1-6]].
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#:
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#:[[Image: DE10-Advanced_revC_PCIE_pic_13.png|700px]]
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#:
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#:::::'''Figure 1-6 Screenshot of DMA Memory Test Result'''
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# Type 99 followed by an ENTER key to exit this test program
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=Development Tools=
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<div style="text-align:center;margin-left:0.635cm;margin-right:0cm;">CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver.</div># Restart Windows
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# Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in [[#Figure710|Figure 7-10]].
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_10.jpg|500px]]</div>
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<div style="text-align:center;">'''Figure 7-10 Screenshot for PCIe Driver'''</div># Goto windows_app folder, execute PCIE_FUNDAMENTAL.exe. A menu will appear as shown in [[#Figure711|Figure 7-11]].
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_11.jpg|500px]]</div>
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<div style="text-align:center;">'''Figure 7-11 Screenshot of Program Menu'''</div># Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in [[#Figure712|Figure 7-12]]. If input 0 (hex 0x00), all led will be turn off.
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_12.jpg|500px]]</div>
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<div style="text-align:center;">'''Figure 7-12 Screenshot of LED Control'''</div># Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in [[#Figure713|Figure 7-13]].
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_13.jpg|500px]]</div>
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<div style="text-align:center;"><span style="color:#404040;">'''Figure 7-13 Screenshot of Button Status Report'''</span></div># Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in [[#Figure714|Figure 7-14]].
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_14.jpg|500px]]</div>
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<div style="text-align:center;"><span style="color:#404040;">'''Figure 7-14 Screenshot of DMA Memory Test Result'''</span></div># Type 99 followed by an ENTER key to exit this test program
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* <div style="margin-left:0cm;margin-right:0cm;">'''Development Tools'''</div>
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* Quartus Prime 18.0 Standard Edition
* Quartus Prime 18.0 Standard Edition
* Visual C++ 2012
* Visual C++ 2012
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* <div style="margin-left:0cm;margin-right:0cm;"><span style="color:#404040;">'''Demonstration Source Code Location'''</span></div>
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=Demonstration Source Code Location=
* Quartus Project: Demonstrations\PCIe_Fundamental
* Quartus Project: Demonstrations\PCIe_Fundamental
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* <div style="margin-left:0cm;margin-right:0cm;">'''FPGA Application Design'''</div>
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=FPGA Application Design=
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[[#Figure715|Figure 7-15]] shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.
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[[#Figure715|Figure 1-7]] shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_15.jpg|500px]]</div>
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[[Image: DE10-Advanced_revC_PCIE_pic_14.jpg|600px]]
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<div style="text-align:center;">'''Figure 7-15 Hardware block diagram of the PCIe reference design'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Windows Based Application Software Design'''</div>
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::::'''Figure 1-7 Hardware block diagram of the PCIe reference design'''
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=Windows Based Application Software Design=
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{| align="center" style="border-spacing:0;width:14.633cm;"
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:{| class="wikitable"
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|- style="background-color:#666633;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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| align=center| <span style="color:#ffffff;">'''Name'''</span>
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| align=center| <span style="color:#ffffff;">'''Description'''</span>
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|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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| align=center| PCIE_FUNDAMENTAL.cpp
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|| Main program
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|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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| align=center| PCIE.c
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|| Implement dynamically load for TERAISC_PCIE_AVMM.DLL
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|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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| align=center| PCIE.h
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|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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| align=center| TERASIC_PCIE_AVMM.h
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|| SDK library file, defines constant and data structure
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|-
|-
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!NAME    !!Description
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|-
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|PCIE_FUNDAMENTAL.cpp   
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||Main program
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|-
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|PCIE.c   
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| rowspan="2"| Implement dynamically load for TERAISC_PCIE_AVMM.DLL
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|-
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|PCIE.h   
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|-
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|TERASIC_PCIE_AVMM.h
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||SDK library file, defines constant and data structure
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<div style="color:#404040;">The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.</div>
<div style="color:#404040;">The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.</div>
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<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_16.jpg|500px]]</div>
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[[Image: DE10-Advanced_revC_PCIE_pic_15.png|500px]]
<div style="color:#404040;">The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. </div>
<div style="color:#404040;">The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. </div>
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* The PCI express driver is loaded successfully.  
* The PCI express driver is loaded successfully.  
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The LED control is implemented by calling PCIE_Write32 API, as shown below:
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[[Image: DE10-Advanced_revC_PCIE_pic_16.png|900px]]
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<div style="color:#404040;">The LED control is implemented by calling PCIE_Write32 API, as shown below:</div>
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The button status query is implemented by calling the PCIE_Read32 API, as shown below:
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[[Image: DE10-Advanced_revC_PCIE_pic_17.png|900px]]
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{| align="center" style="border-spacing:0;width:15.333cm;"
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The memory-mapped memory read and write test is implemented by '''PCIE_DmaWrite''' and '''PCIE_DmaRead''' API, as shown below:
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|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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|| [[Image: DE10-Advanced_revC_PCIE_pic_17.jpg|500px]]
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|}
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<div style="color:#404040;">The button status query is implemented by calling the PCIE_Read32 API, as shown below:</div>
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[[Image: DE10-Advanced_revC_PCIE_pic_18.png|600px]]
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{| align="center" style="border-spacing:0;width:15.134cm;"
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'''[[DE10_Advance_revC_demo: PCI Express Design for Windows |Back]]'''
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|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
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|| [[Image: DE10-Advanced_revC_PCIE_pic_18.jpg|500px]]
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<div style="color:#404040;">The memory-mapped memory read and write test is implemented by '''PCIE_DmaWrite''' and '''PCIE_DmaRead''' API, as shown below:</div>
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Latest revision as of 10:45, 31 August 2018

The application reference design shows how to implement fundamental control and data transfer in DMA. In the design, basic I/O is used to control the BUTTON and LED on the FPGA board. High-speed data transfer is performed by DMA.

Contents

Demonstration Files Location

The demo file is located in the batch folder: CDROM\Demonstrations\ PCIe_Fundamental\demo_batch


The folder includes following files:
  • FPGA Configuration File: PCIe_Fundamental.sof
  • Download Batch file: test.bat
  • Windows Application Software folder : windows_app, includes
    • PCIE_FUNDAMENTAL.exe
    • TERASIC_PCIE_AVMM.DLL

Demonstration Setup

  1. Install the FPGA board on your PC as shown in Figure 1-1.
    De10-advanced revc FPGA board connect to PC.jpg
    Figure 1-1 FPGA board connect to PC
  2. Configure FPGA with PCIe_Fundamental.sof by executing the test.bat.
  3. Install PCIe driver if necessary. The driver is located in the folder: CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver.
  4. Restart Windows
  5. Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in Figure 1-2.
    DE10-Advanced revC PCIE pic 9.jpg
    Figure 1-2 Screenshot for PCIe Driver
  6. Goto windows_app folder, execute PCIE_FUNDAMENTAL.exe. A menu will appear as shown in Figure 1-3.
    DE10-Advanced revC PCIE pic 10.png
    Figure 1-3 Screenshot of Program Menu
  7. Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in Figure 1-4. If input 0 (hex 0x00), all led will be turn off.
    DE10-Advanced revC PCIE pic 11.png
    Figure 1-4 Screenshot of LED Control
  8. Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in Figure 1-5.
    DE10-Advanced revC PCIE pic 12.png
    Figure 1-5 Screenshot of Button Status Report
  9. Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in Figure 1-6.
    DE10-Advanced revC PCIE pic 13.png
    Figure 1-6 Screenshot of DMA Memory Test Result
  10. Type 99 followed by an ENTER key to exit this test program

Development Tools

  • Quartus Prime 18.0 Standard Edition
  • Visual C++ 2012

Demonstration Source Code Location

  • Quartus Project: Demonstrations\PCIe_Fundamental
  • C++ Project: Demonstrations\PCIe_SW_KIT\Windows\PCIE_FUNDAMENTAL


FPGA Application Design

Figure 1-7 shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.

DE10-Advanced revC PCIE pic 14.jpg

Figure 1-7 Hardware block diagram of the PCIe reference design

Windows Based Application Software Design

The application software project is built by Visual C++ 2012. The project includes the following major files:


NAME Description
PCIE_FUNDAMENTAL.cpp Main program
PCIE.c Implement dynamically load for TERAISC_PCIE_AVMM.DLL
PCIE.h
TERASIC_PCIE_AVMM.h SDK library file, defines constant and data structure
The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.

DE10-Advanced revC PCIE pic 15.png

The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller.


Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the TERASIC_PCIE_AVMM.dll. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:
* The FPGA is configured with the associated bit-stream file and the host is rebooted.
  • The PCI express driver is loaded successfully.

The LED control is implemented by calling PCIE_Write32 API, as shown below:

DE10-Advanced revC PCIE pic 16.png

The button status query is implemented by calling the PCIE_Read32 API, as shown below:

DE10-Advanced revC PCIE pic 17.png

The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below:

DE10-Advanced revC PCIE pic 18.png

Back

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