Terasic Host FPGA Board
From Terasic Wiki
(Difference between revisions)
| Line 5: | Line 5: | ||
*[[DE5-NET_TopPage|DE5-NET]] | *[[DE5-NET_TopPage|DE5-NET]] | ||
*[[DE4_TopPage|DE4]] | *[[DE4_TopPage|DE4]] | ||
| + | *[[TR10a-HL_TopPage|TR10a-HL]] | ||
| + | *[[TR10a-HL2_TopPage|TR10a-HL2]] | ||
| + | *[[TR10a-LPQ_TopPage|TR10a-LPQ]] | ||
*[[HERO_TopPage|HERO]] | *[[HERO_TopPage|HERO]] | ||
Revision as of 14:46, 12 August 2019
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