Terasic Host FPGA Board
From Terasic Wiki
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== High Profile PCIe Board == | == High Profile PCIe Board == | ||
| + | *[[Mercury_A2700_Accelerator_Cardt_TopPage|Mercury A2700 Accelerator Card(MA27)]] | ||
| + | *[[Agilex_7_FPGA_Starter_Kit_TopPage|Agilex 7 FPGA Starter Kit(A7SK)]] | ||
| + | *[[DE10-Agilex_TopPage|DE10-Agilex]] | ||
*[[DE10-Pro_TopPage|DE10-Pro]] | *[[DE10-Pro_TopPage|DE10-Pro]] | ||
*[[DE5a-NET_TopPage|DE5a-NET]] | *[[DE5a-NET_TopPage|DE5a-NET]] | ||
| Line 19: | Line 22: | ||
*[[VPX-A5SOC_TopPage|VPX-A5SOC]] | *[[VPX-A5SOC_TopPage|VPX-A5SOC]] | ||
| - | *[[DE10-Advanced_TopPage| | + | *[[DE10-Advanced_TopPage|HAN Pilot Platform]] |
*[[TSoM_TopPage|TSoM]] | *[[TSoM_TopPage|TSoM]] | ||
| + | *[[Apollo_S10_SoM_TopPage|Apollo_S10_SoM]] | ||
| + | *[[Apollo_Agilex_SoM_TopPage|Apollo_Agilex_SoM]] | ||
== ASIC Prototyping Board == | == ASIC Prototyping Board == | ||
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== Classic FPGA Development Board == | == Classic FPGA Development Board == | ||
| - | *[[ | + | *[[TSP_TopPage|TSP]] |
*[[DE0-CV_TopPage|DE0-CV]] | *[[DE0-CV_TopPage|DE0-CV]] | ||
*[[DE2-115_TopPage|DE2-115]] | *[[DE2-115_TopPage|DE2-115]] | ||
*[[DE0-Nano_TopPage|DE0-Nano]] | *[[DE0-Nano_TopPage|DE0-Nano]] | ||
*[[DE10-Lite_TopPage|DE10-Lite]] | *[[DE10-Lite_TopPage|DE10-Lite]] | ||
| - | *[[DE-Core_TopPage| | + | *[[DE-Core_TopPage|T-Core]] |
== Multi-Media Platform == | == Multi-Media Platform == | ||
*[[VEEK-MT2S_TopPage|VEEK-MT2S]] | *[[VEEK-MT2S_TopPage|VEEK-MT2S]] | ||
Latest revision as of 10:44, 26 February 2024
Contents |
High Profile PCIe Board
- Mercury A2700 Accelerator Card(MA27)
- Agilex 7 FPGA Starter Kit(A7SK)
- DE10-Agilex
- DE10-Pro
- DE5a-NET
- DE5a-NET-DDR4
- DE5-NET
- DE4
- TR10a-HL
- TR10a-HL2
- TR10a-LPQ
- HERO
