Preface
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VII |
Chapter 1 Digital Designs with EDA and FPGA
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1 |
1.1. Overview |
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3 |
1.2. Register Transfer Level |
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5 |
1.3. Electronic Design Automation and Hardware Description Language |
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6 |
1.4. Field Programmable Gate Arrays |
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8 |
1.5. DE1, DE1-SOC and DE2-115 Boards |
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9 |
1.6. Exercises |
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11 |
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Chapter 2 VHDL Primers
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13 |
2.1. Basic Modeling |
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14 |
2.1.1. Lexical Elements |
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14 |
2.1.2. VHDL Data Types |
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16 |
2.2. Packages in IEEE Library |
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23 |
2.2.1. Multi-Valued Logic System |
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24 |
2.2.2. Logic Operators/Functions |
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26 |
2.2.3. Arithmetic Operators/Functions |
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27 |
2.3. Concurrent Statements |
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27 |
2.3.1. Signal Assignments and Operators |
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28 |
2.3.2. WHEN-ELSE |
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28 |
2.3.3. Component Instantiation |
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32 |
2.3.4. Process |
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35 |
2.4. Sequential Statements |
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36 |
2.4.1. Assignments and Functions |
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36 |
2.4.2. IF Statements |
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36 |
2.4.3. CASE Statements |
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37 |
2.5. Exercises |
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40 |
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Chapter 3 RTL Digital Designs
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46 |
3.1. Combinational RTL Components |
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47 |
3.1.1. Signals and Numbers |
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47 |
3.1.2. Multiplexers |
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48 |
3.1.3. Adders |
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57 |
3.1.4. Multipliers |
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66 |
3.1.5. Comparators |
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67 |
3.2. Sequential RTL Components |
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70 |
3.2.1. VHDL Structure for Sequential Digital Circuits |
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70 |
3.2.2. Registers |
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74 |
3.2.3. Shift Registers |
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76 |
3.2.4. Counters |
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79 |
3.3. Memory Components |
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84 |
3.3.1. FPGA's Built-in RAMs |
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84 |
3.3.2. ROMs |
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87 |
3.3.3. SRAM |
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89 |
3.4. Finite State Machines |
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90 |
3.5. Exercises |
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94 |
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Chapter 4 Design of Digital Systems
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99 |
4.1. Digital System Modeling |
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100 |
4.1.1. Functional Block Diagrams |
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101 |
4.1.2. State Diagram |
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102 |
4.1.3. Flowchart |
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102 |
4.1.4. FSM VHDL Infrastructure |
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103 |
4.2. Design Example I: Sequence Detector |
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106 |
4.2.1. Combinational Case |
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106 |
4.2.2. Single Event Part I |
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107 |
4.2.3. Single Event Part II |
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109 |
4.2.4. Complex Sequence |
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110 |
4.2.5. Sequence with Time Constraint |
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112 |
4.3. Design Example II: Stopwatch |
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122 |
4.3.1. Frequency Generator |
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122 |
4.3.2. BCD Counter |
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124 |
4.3.3. Controller |
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127 |
4.3.4. Hex-to-Sevenseg and Debounce |
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132 |
4.3.5. Stopwatch Design Version 1 |
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135 |
4.3.6. Stopwatch Design Version 2 |
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136 |
4.4. Exercises |
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142 |
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Chapter 5 Personal System/2 (PS/2) Keyboard
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147 |
5.1. PS/2 Protocol |
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148 |
5.1.1. Physical Connectors |
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148 |
5.1.2. Serial Data Format |
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149 |
5.1.3. Keyboard Interface Design |
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150 |
5.2. Keyboard Scan Code |
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154 |
5.2.1. Make and Break Codes |
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155 |
5.2.2. Simple Interface Design Example |
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155 |
5.3. Handshaking and Decision Makings |
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159 |
5.3.1. Two-Wire Handshaking |
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159 |
5.3.2. Handshaking with Keyboard Interface |
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160 |
5.3.3. Using Shift Register to Detect Break Codes |
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165 |
5.4. Ticker Display Example |
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167 |
5.4.1. Modified Hex-to-Sevenseg |
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169 |
5.4.2. Slow Clock Generator |
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170 |
5.4.3. Keyboard Command Interpreter |
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171 |
5.4.4. Ticker Display Controller |
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177 |
5.4.5. Complete Design |
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180 |
5.5. Exercises |
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182 |
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Chapter 6 Video Graphics Array (VGA)
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188 |
6.1. VGA Interface Design |
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191 |
6.1.1. VGA Timing Specifications |
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191 |
6.1.2. Phase Lock Loop |
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194 |
6.1.3. VGA Hardware Supports on DE Boards |
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197 |
6.1.4. Basic VGA Interface |
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200 |
6.1.5. Screen Test Circuit |
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203 |
6.2. Video Memory |
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208 |
6.2.1. General Organization |
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209 |
6.2.2. Color Depth and Memory Space Utilization |
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210 |
6.2.3. VGA Interface with Video RAM Design |
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212 |
6.2.4. Bouncing Ball Example |
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217 |
6.3. Animation with Keyboard Controls |
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225 |
6.3.1. Design Overview |
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225 |
6.3.2. Keyboard Handler |
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226 |
6.3.3. Drawing Borders and Initial Paddle |
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227 |
6.3.4. Collision Detections |
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229 |
6.3.5. Main FSM Design |
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231 |
6.4. Exercises |
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242 |
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Chapter 7 Text Video
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246 |
7.1. VGA Interface with Hardware Font Table |
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247 |
7.1.1. Hardware Organization |
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247 |
7.1.2. Bitmap Font Construction |
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249 |
7.1.3. ROM: 1-Port |
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251 |
7.1.4. Design of VGA Interface with Built-in Font Table |
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252 |
7.1.5. Text Video Screen Test |
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256 |
7.1.6. In-System Memory Content Editor |
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259 |
7.2. Text Terminal Design Example |
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259 |
7.2.1. Design Overview |
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261 |
7.2.2. Converting Scan Codes to ASCII Codes |
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262 |
7.2.3. FSM Design |
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263 |
7.2.4. VHDL Codes |
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266 |
7.3. Multi-Colored Displays |
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273 |
7.3.1. Colored Text |
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273 |
7.3.2. Multiple Lookup tables |
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280 |
7.3.3. Single Lookup Table |
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284 |
7.4. Exercises |
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292 |
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Chapter 8 Digital Audio
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296 |
8.1. Audio Interface Design |
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300 |
8.1.1. I2
C Controller |
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301 |
8.1.2. Bit Clock and Left/Right Clock |
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311 |
8.1.3. Digital Audio Receiver/Transmitter |
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312 |
8.1.4. Echo Audio Effect |
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317 |
8.2. Digital Audio Signal Generations |
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323 |
8.2.1. Wavetable Synthesizer |
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323 |
8.2.2.Random Number Generators for White Noise Generations |
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328 |
8.2.3. Digital Audio Generator Test Circuit |
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332 |
8.3. Finite Impulse Response Filter |
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334 |
8.3.1. Altera's FIR Compiler |
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335 |
8.3.2. Avalon Bus Interface |
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338 |
8.3.3. FIR Filter Test Circuit |
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340 |
8.4. Exercises |
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343 |
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Chapter 9 Advanced Digital Design Examples
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349 |
9.1. PS/2 Mouse Interface Design |
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350 |
9.1.1. PS/2 Transmitter and Receiver |
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352 |
9.1.2. PS/2 Protocol for Mouse |
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355 |
9.1.3. Data Packet |
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358 |
9.2. Video Interface with Full VGA Resolution |
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365 |
9.2.1. SRAM Interface |
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366 |
9.2.2. Hardware Mouse Cursor |
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369 |
9.2.3. Video memory Constructed from Two Video RAMs |
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374 |
9.3. Mandelbrot Set |
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379 |
9.3.1. Mandelbrot Calculations |
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379 |
9.3.2. Zoom Functions |
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381 |
9.3.3. Fixed-Point Arithmetic |
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383 |
9.3.4. Mandelbrot with Fixed-Point Arithmetic Circuits |
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385 |
9.4. Mandelbrot with Double Precision Floating-Point Numbers |
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390 |
9.4.1. Floating-Point Number Standard |
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390 |
9.4.2. Altera's FP Megafunctions |
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392 |
9.4.3. Datapaths |
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395 |
9.4.4. Mandelbrot with Floating-Point Arithmetic Circuits |
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398 |
9.5. Multiple Clock Domains |
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408 |
9.5.1. DE1 and DE2-115 Examples |
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408 |
9.5.2. DE1-SOC Examples |
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410 |
9.5.3. Hardware Resource Utilizations |
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410 |
9.6. Exercises |
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412 |
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Chapter 10 More About VHDL
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416 |
10.1. Compiler Directives |
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417 |
10.1.1. ASSERT and REPORT |
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418 |
10.1.2. Data Related |
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419 |
10.1.3. Simulation Related |
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420 |
10.2. Attributes |
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421 |
10.2.1. For Scalar Types |
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422 |
10.2.2. For Array Types |
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422 |
10.2.3. For Signals |
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423 |
10.2.4. For Entities |
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423 |
10.3. Synthesizable Statements |
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424 |
10.3.1. Combinational Ststements |
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424 |
10.3.2. Sequential Statements |
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429 |
10.3.3. Configuration Specifications |
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431 |
10.4. Iterative Structures |
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431 |
10.4.1. FOR-GENERATE |
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431 |
10.4.2. IF-GENERATE |
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433 |
10.4.3. LOOP |
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437 |
10.5. Subprograms |
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441 |
10.5.1 Functions |
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441 |
10.5.2. Procedures |
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443 |
10.6. Library and Package |
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445 |
10.6.1. Package Declaration |
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445 |
10.6.2. Create a Package |
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449 |
10.6.3. Create a Library |
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451 |
10.7. Exercises |
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454 |
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APPENDIX A Operators and Functions Overloading
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458 |
A.1. From STD_LOGIC_1164 |
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459 |
A.2. From NUMERIC_STD |
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459 |
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APPENDIX B IEEE Packages
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462 |
B.1. Standard (Built-In) |
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463 |
B.2. STD_LOGIC_1164 |
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465 |
B.3. NUMERIC_STD |
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470 |
B.4. NUMERIC_BIT |
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473 |
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APPENDIX C Additional EDA Tools
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479 |
C.1. Programmer |
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480 |
C.2. ModelSim-Altera |
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486 |
C.3. SignalTap II Logic Analyzer |
|
495 |
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INDEX
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501 |