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Revision as of 14:07, 14 May 2020

Chpater1 Introduction

The F2G board is designed to convert a FPGA Mezzanine Card(FMC) or FPGA Mezzanine Card Plus(FMC+) interface to four 2x20pin expansion prototype(GPIO) headers, which are compatible with the expansion headers of the Terasic DE-Series board(Such as DE2-115/DE10-Standard). Users can connect up to four GPIO headers onto a FMC-interfaced host board via a F2G board.

1-1 Kit Contents

Figure 1-1 shows a photograph of the F2G package.

1. F2G Card
2. Screw & Copper Pillar Pakage
3. CD Download Guide

1-2 Features

Figure 1-2 shows the photo of a F2G board. The important functions of the F2G are listed below:

• FMC High-Pin Count Interface
• I/O standard follows the definition of the mainboard without level shift
• Vcc power supply is 3.3V or adjustable according to the mainboard
• Four 2x20 GPIO Headers
• 2x6 TMD Header
• SMA Clock Input
• Button x2
• Switch x2
• LED x2

1-3 Layout and Components

This section presents the features and design characteristics of the board. A photograph of the board is shown in Figure 1-3 and Figure 1-4 It depicts the layout of the board and indicates the location of the connectors and key components.

1-4 Block Diagram

Figure 1-5 gives the block diagram of the board. According to the FMC Vita 57 specification, the FMC connector can be divided into two specifications by I/O pin numbers: high pin count and low pin count. Therefore, in the figure, we list 3 groups I/O pin in the FMC connector such as LA, HA and HB. Pins with a L prefix (LA) shall have connector contacts populated in the low-pin and high-pin count connectors.

Pins with a H prefix (HA and HB) shall have connector contacts populated only in the high-pin count connector. This will allow users to understand which F2G board interfaces can be used for their FPGA motherboard.

1-5 Mechanical Specifications

Figure 1-6 is the Mechanical Layout of F2G board.

1-6 Getting Help

Contact us via the following methods for further technical assistance:

• Terasic Inc.9F, No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, Taiwan 300-70
• Email : support@terasic.com
• Web : www.terasic.com

Chpater 2 Board Components

This chapter provides instructions to use the board and the peripherals description.

2-1 2x20 GPIO Headers

The 2x20 GPIO header is the most important interface on the F2G board. Most of the pins on the GPIO headr is directly connected to the FMC connector, allowing users to convert the FPGA I/O on the mother board from FMC connector to 2.54mm GPIO headr pin, which is more convenient to develop and debug.

Pin Out Of the GPIO Header

There are four 2x20 GPIO headers on the F2G board(See Figure 2-1). The pin distribution and power of each GPIO header is almost the same as the GPIO of Teraic DE series board(See Figure 2-2 and Figure 2-3). Each GPIO header can provide 36 user I / O and two sets of power supply and ground pin.

Only on pin 29: Power pin is a little different. On the F2G board, user can choose to provide 3.3V or VADJ (from motherboard through FMC) via 3-pin header. For example, pin 29 on GPIO0 is VCC_GPIO0, and this power is controlled by JP6. If pin1 and pin2 of JP6 are short-circuited, then VCC_GPIO0 will be 3.3V. If short Pin 2 and Pin3, VCC_GPIO0 will be VADJ. The default setting of all the 3-pin header is short pin 1 and 2, i.e. 3.3V is provided. The control header corresponding to each GPIO header is shown in Table 2-1.

I/O standard of the GPIO headers

Because the GPIO header is directly connected to the I/O of the FMC connector and has not been converted by any level translator. Therefore, the I / O standard of the GPIO header depends on the voltage settings on the FPGA motherboard. So, before using or connectting any circuit to the GPIO header, please check whetherhe logic level matches the FPGA mother board.

Support status for HPC and LPC of FMC connector

The number of pin I / O of the FMC connector is divided into two specifications: high pin count(HPC) and low pin count(LPC). As shown in Figure 1-5, If the FMC connector on the user's mother board is low pin count, type, you can only use the two headers : GPIO_0 and GPIO1 on F2G board. It should be noted that there are two I / O(GPIO_1_D8 and GPIO_1_D9) on GPIO_1 that are connected to the pin group of high pin count, so these two I/O will also be unavailable(See Figure 2-2). If the user's mother board is HPC type, the four GPIO headers on F2G board are all can be used.

In addition, it should be noted that many FPGA motherboards may place some terminal resistors on the FMC I/O for differential I/O standard or clock I/O. To use the GPIO header pin on F2G, you may need to remove these resistors between the I/O first to avoid interfere with each other. For example, GPIO_0_D0/GPIO_0_D1 on GPIO_0 header are connected to the CLK0_M2C_P/CLK0_M2C_N pin of the FMC connector. On many FPGA motherboards, a terminal resistor may be reserved for this pair of I/O. If users want to use both GPIO_0_D0 and GPIO_0_D1, you may need to check and remove the resistance on the motherboard first to avoid the two I/O interfere with each other.

Pin Mappings for GPIO and FMC

Table 2-2, Table 2-3,Table 2-4 and Table 2-5 list the list each GPIO header pin number and signal name and the connected FMC pin.

(*1) : VCCIO_GPIO0/VCCIO_GPIO1/VCCIO_GPIO2/VCCIO_GPIO3 is determined by 3-pin headers for 3.3V or VADJ, please refer to section: Pin Out Of the GPIO Header for details

2-2 2x6 TMD Headers