DE10 Advance revC demo: RTL DDR4 SDRAM Test

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=Function Block Diagram=
=Function Block Diagram=
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Figure 6-2 shows the function block diagram of this demonstration. There are two DDR4 SDRAM controllers. The controller uses 266.667 MHz as a reference clock. It generates one 1066MHz clock as memory clock from the FPGA to the memory and the controller itself runs at quarter-rate in the FPGA i.e. 266.667 MHz.
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Figure 1-1 shows the function block diagram of this demonstration. There are two DDR4 SDRAM controllers. The controller uses 266.667 MHz as a reference clock. It generates one 1066MHz clock as memory clock from the FPGA to the memory and the controller itself runs at quarter-rate in the FPGA i.e. 266.667 MHz.
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[[File:De10 advanced revc ddr4 rtl block diagram.jpg|600px]]
   
   
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Figure 6-2 Block diagram of DDR4 x2 demonstration
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::::'''Figure 1-1 Block diagram of DDR4 x2 demonstration'''
=Design Tools=
=Design Tools=
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Quartus Prime 18.0.0 Standard Edition  
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*Quartus Prime 18.0.0 Standard Edition  
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Demonstration Source Code:  
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*Demonstration Source Code:  
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Project Directory: Demonstration\RTL_DDR4  
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**Project Directory: Demonstration\RTL_DDR4  
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Bit Stream: RTL_DDR4.sof
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**Bit Stream: RTL_DDR4.sof
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Demonstration Batch File:
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=Demonstration Batch File=
Demo Batch File Folder: RTL_DDR4 \demo_batch
Demo Batch File Folder: RTL_DDR4 \demo_batch
The demo batch file includes following files:
The demo batch file includes following files:
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Batch File: test.bat
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*Batch File: test.bat
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FPGA Configuration File: RTL_DDR4.sof
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*FPGA Configuration File: RTL_DDR4.sof
=Demonstration Setup=
=Demonstration Setup=
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#Make sure Quartus Prime is installed on the host PC.
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#Connect DE10-Advanced board to the host PC via USB cable. Install the USB-Blaster II driver if necessary.
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#Power on the DE10-Advanced.
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#Execute the demo batch file “test.bat” under the batch file folder \ RTL_DDR4\demo_batch.
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#Press KEY0 on DE10-Advanced to start the verification process. When KEY0 is released, LED0, LED1 should start blinking. After approximately 2 seconds, LED1 and LED2 should stop blinking and stay on to indicate the DDR4 (A) and DDR4 (B) have passed the test, respectively. Table 6-2 lists the LED indicators.
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#If LED0 or LED1 does not start blinking upon releasing KEY0, it indicates local_cal_success of the corresponding DDR4 fails.
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#If LED0 or LED1 fail to remain on after 2 seconds, the corresponding DDR4 test has failed.
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#Press KEY0 again to regenerate the test control signals for a repeat test.
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:'''Table 1-1 LED Indicators'''
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:{| class="wikitable"
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  |-
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!NAME !!Description
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|-
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|LED0 ||DDR4 (A) test result
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|-
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|LED1 ||DDR4 (B) test result
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|}
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 Make sure Quartus Prime is installed on the host PC.
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'''[[DE10-Advance_Demonstration_Manual_revC#Chapter 2 Examples For FPGA|Back]]'''
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 Connect DE10-Advanced board to the host PC via USB cable. Install the USB-Blaster II driver if necessary.
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 Power on the DE10-Advanced.
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 Execute the demo batch file “test.bat” under the batch file folder \ RTL_DDR4\demo_batch.
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 Press KEY0 on DE10-Advanced to start the verification process. When KEY0 is released, LED0, LED1 should start blinking. After approximately 2 seconds, LED1 and LED2 should stop blinking and stay on to indicate the DDR4 (A) and DDR4 (B) have passed the test, respectively. Table 6-2 lists the LED indicators.
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 If LED0 or LED1 does not start blinking upon releasing KEY0, it indicates local_cal_success of the corresponding DDR4 fails.
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 If LED0 or LED1 fail to remain on after 2 seconds, the corresponding DDR4 test has failed.
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 Press KEY0 again to regenerate the test control signals for a repeat test.
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Table 6-2 LED Indicators
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NAME Description
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LED0 DDR4 (A) test result
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LED1 DDR4 (B) test result
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Latest revision as of 16:27, 24 August 2018

This demonstration performs a memory test function on the one DDR4 SO-DIMM (DDR4A) and one DDR4 Component (DDR4B) on the DE10-Advanced. The memory size of DDR4 SO-DIMM is 4GB and DDR4 Component is 1GB.

Contents

Function Block Diagram

Figure 1-1 shows the function block diagram of this demonstration. There are two DDR4 SDRAM controllers. The controller uses 266.667 MHz as a reference clock. It generates one 1066MHz clock as memory clock from the FPGA to the memory and the controller itself runs at quarter-rate in the FPGA i.e. 266.667 MHz.

De10 advanced revc ddr4 rtl block diagram.jpg

Figure 1-1 Block diagram of DDR4 x2 demonstration

Design Tools

  • Quartus Prime 18.0.0 Standard Edition
  • Demonstration Source Code:
    • Project Directory: Demonstration\RTL_DDR4
    • Bit Stream: RTL_DDR4.sof

Demonstration Batch File

Demo Batch File Folder: RTL_DDR4 \demo_batch

The demo batch file includes following files:

  • Batch File: test.bat
  • FPGA Configuration File: RTL_DDR4.sof

Demonstration Setup

  1. Make sure Quartus Prime is installed on the host PC.
  2. Connect DE10-Advanced board to the host PC via USB cable. Install the USB-Blaster II driver if necessary.
  3. Power on the DE10-Advanced.
  4. Execute the demo batch file “test.bat” under the batch file folder \ RTL_DDR4\demo_batch.
  5. Press KEY0 on DE10-Advanced to start the verification process. When KEY0 is released, LED0, LED1 should start blinking. After approximately 2 seconds, LED1 and LED2 should stop blinking and stay on to indicate the DDR4 (A) and DDR4 (B) have passed the test, respectively. Table 6-2 lists the LED indicators.
  6. If LED0 or LED1 does not start blinking upon releasing KEY0, it indicates local_cal_success of the corresponding DDR4 fails.
  7. If LED0 or LED1 fail to remain on after 2 seconds, the corresponding DDR4 test has failed.
  8. Press KEY0 again to regenerate the test control signals for a repeat test.


Table 1-1 LED Indicators
NAME Description
LED0 DDR4 (A) test result
LED1 DDR4 (B) test result

Back

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