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Customer Success with Terasic FPGA platform

DE1 DE2 DE2-70 DE3 NEEK


 

Altera DE1 Board
  • Zet processor (IA-32 architecture) on DE1  
  • Space Invaders Game   
  • FPGA Cyclone II Synthesizer   
  • Tetris using FPGA   
  • Touchscreen Clock VHDL Project   

 

Altera DE2 Board
  • Apple2fpga: Reconstructing an Apple II+ on an FPGA (using DE2)   
  • Pacman Game      
  • SNES .SPC Player on FPGA   
  • Speech Recognition using FPGA    
  • Altera DE2 FPGA Keyboard   
  • Frogger Game on Altera DE2    
  • Edge Detection with DE2-Board    
  • FPGA MD5 Cracker    Part 1    Part 2
  • VHDL Project: InfraRed Remote controlled Smart Home with DE2 Board  

 

Altera DE2-70 Board
  • Fpga game console  
  • Arkanoid on FPGA  
  • FPGA-Paint: Fingerpainting with a hardware chip  
  • Final Project   
  • Image editor with JPEG/JPEG2000 compressor
    • Creating a new image  
    • Editing an Image  
    • Taking and editing a photo  

 

Altera DE3 Development System
  • Stanford University
    • A Highly Scalable Restricted Boltzmann Machine FPGA Implementation   
  • University of Toronto
    • Vector Extended Soft Processor Architecture (VESPA)  
    • FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy 
    • Hardware-accelerated MC Simulation for PDT Treatment Planning using FPGAs and GPUs  
  • Imperial University London
    • Performance Comparison of GPU and FPGA architectures for the SVM Training Problem  
  • University of Massachusetts - Amherst
    • APPLICATION-SPECIFIC CUSTOMIZATION AND SCALABILITY OF SOFT MULTIPROCESSORS  

 

Nios II Embedded Evaluation Kit

 

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