DE10-Agilex board modifycation item from rev.A to rev.B
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- Add power protection switch (SW1) feature on Rev. B board. This switch can avoid damage to the components on the board due to insufficient power supply of the board.When the switch is switched to "ON" position, the board will detect whether the external power is connected to the 2x4 power connector. If it is not connected, the DE10-Agilex board will not power on when the user turns on the power of the Host. This can avoid DE10-Agilex Insufficient power supply of board occurs.
- Add QSPI Flash on Rev. B board for storing user data and nios code
- Add a System MAX10 Jtag bypass dip switch (SW9) that allow the System MAX10 FPGA can be bypass in the JTAG chain of the DE10-Agilex board. This can increase the JTAG scan speed.
- Reserve an OCXO Oscillators (Not installed, reserved for CPRI application)
- Change the reference clock of the si5340, from crystall(Rev.A) to TCXO Oscillator(Rev.B)
- Change the core power IC (U15) from LT4680(Rev.A) to LT4700(Rev.B) , the output current of the core power can be increased from 60A(Rev.A) to 100A(Rev.B)
- Modify the DDR4 reference clock source frequency. In version B, the DDR4 clock source frequency is fixed at 33.33Mhz (clock switch SW5 is not installed ). In version A, using SW5 can select 266.66Mhz or 300Mhz.
- Change the orientation of the external 2x4 pin power connector from up to right.
- A slight modification of the heatsink due to the Layout modifucation.
- Modify pin assignments (Please see Table 2)
The following table shows the summary of the changes:
Table 1 summary of the changes from Rev.A to Rev.B
| Function | Rev. A | Rev. B | |
| 1 | Power protection switch (SW1) feature | Not Support | Support |
| 2 | QSPI Flash (For storing user data or NIOS software code) | Not Support | Support |
| 3 | OCXO Oscillators for CPRI application | Not Support | Reserved |
| 4 | Reference clock of the SI5340 | Crystal | TCXO Oscillator |
| 5 | Core Power IC | LT4680 (60A) | LT4700 (100A) |
| 6 | DDR4 reference clock source frequency | 266.66Mhz or 300Mhz (select by SW5) | 33.333Mhz (Fixed) |
| 7 | The orientation of the external 2x4 pin power connector | Up | Right |
| 8 | Heat sink solution | Modify the heat sink of the core power IC | |
| 9 | Modify pin assignment | See the Table 2 | See the Table 2 |
Table 2 Pin Assignments modify list from Rev.A to Rev.B
(*1) New net in Rev.B
| Net | Rev.A Pin Assignment | Rev.B Pin Assignment |
| PCIE_SMBCLK | F59 | G50 |
| PCIE_CLKREQ_n | J58 | F55 |
| PCIE_WAKE_n | G58 | J50 |
| DDR4B_SDA | H57 | B19 |
| GPIO_CLK0 | CU24 | DA22 |
| GPIO_P0 | DA22 | CY21 |
| INFO_SPI_MISO | CY21 | CU26 |
| CLK_30M72 (*1) | -- | CU24 |
| EXP_EN(*1) | -- | A20 |
| QSPI_CLK(*1) | -- | CT53 |
| QSPI_nCSO(*1) | -- | CV53 |
| QSPI_DATA0(*1) | -- | CT55 |
| QSPI_DATA1(*1) | -- | CV57 |
| QSPI_DATA2(*1) | -- | DC56 |
| QSPI_DATA3(*1) | -- | DA56 |
