DE10-Advance usermanual revB
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==4.5 PCIe== | ==4.5 PCIe== | ||
| + | The DE10-Advanced development board features one PCIe Express downstream interfaces (x4 lane) which are designed to interface with a PC motherboard x4 slot via PCIe cable and PCIe adapter card. Utilizing built-in transceivers on a Arria 10 SoC device, it is able to provide a fully integrated PCI Express compliant solution for multi-lane (x4) applications. With the PCI Express hard IP block incorporated in the Arria 10 SoC device, it will allow users to implement simple and fast protocols, as well as saving logic resources for logic applications. | ||
| + | |||
| + | The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane, Gen2 at 5.0Gbps/lane, and Gen3 at 8.0Gbps/lane protocol stack solution compliant to PCI Express base specification 3.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks. | ||
| + | |||
| + | To use PCIe interface, two external associated devices will be needed to establish a link with PC. First, a PCIe half-height add-in host card with a PCIe x4 cable connector called PCA (PCIe Cabling Adapter Card and see Figure 4-5, it will be used to plug into the PCIe slot on a mother board.<br/> | ||
| + | ::::[[File:PCA.jpg|200px]]<br/> | ||
| + | ::::Figure 4-5 PCIe Cabling Adaptor(PCA) card<br/> | ||
| + | |||
| + | Then,a PCIe x4 cable(See Figure 4-6) will be used to connect DE10-Advanced board and PCIe add-in card, the longest length is up to 3 meters.These two associated devices are not included in DE10-Advanced board. To purchase the PCA card as well as the external cable, please refer to Terasic website [http://pca.terasic.com PCIe x4 Cable Adapter]and [http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=77&No=687 PCIe x4 Gen.2 Cable].Table 4-8 summarizes the PCI Express pin assignments of the signal names relative to the Arria 10 SoC FPGA.PCIe pin connection is showed in Figure 4-7.<br/> | ||
| + | ::::[[File:PCA Cable.jpg|300px]]<br/> | ||
| + | ::::::Figure 4-6 PCIe External Cable<br/> | ||
| + | |||
| + | |||
| + | |||
| + | [[File:PCIe.jpg|500px]]<br/> | ||
| + | :::::Figure 4-7 PCI Express Pin Connection | ||
| + | |||
| + | |||
| + | ::::Table 4-8 PCIe Pin Assignments,Signal Names and Functions | ||
| + | :{| class="wikitable" | ||
| + | |- | ||
| + | !Signal Name!!FPGA Pin Number!!Description!!I/O Standard | ||
| + | |- | ||
| + | |PCIE_REFCLK_p||PIN_AH31||PCIe reference clock||LVDS | ||
| + | |- | ||
| + | |PCIE_TX_p[0]||PIN_AR37||PCIe Transmitter data p0||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_TX_p[1]||PIN_AP39||PCIe Transmitter data p1||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_TX_p[2]||PIN_AN37||PCIe Transmitter data p2||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_TX_p[3]||PIN_AM39||PCIe Transmitter data p3||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_RX_p[0]||PIN_AL33||PCIe Receiver data p0||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_RX_p[1]||PIN_AM35||PCIe Receiver data p1||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_RX_p[2]||PIN_AJ33||PCIe Receiver data p2||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_RX_p[3]||PIN_AK35||PCIe Receiver data p3||HSSI DIFFERENTIAL I/O | ||
| + | |- | ||
| + | |PCIE_PERST_n||PIN_AW20||PCIe present,active low||1.8 V | ||
| + | |- | ||
| + | |PCIE_WAKE_n||PIN_AL19||PCIe wake||1.8 V | ||
| + | |} | ||
| + | |||
==<span style="color:#ff0000;">4.6 DDR4</span>== | ==<span style="color:#ff0000;">4.6 DDR4</span>== | ||
== <span style="color:#ff0000;">4.7 HDMI TX</span>== | == <span style="color:#ff0000;">4.7 HDMI TX</span>== | ||
Revision as of 09:39, 25 June 2018
Chapter 1 DE10-Advanced Development Kit
1.1 Package Contents
1.2 DE10-Advanced System CD
1.3 Getting Help
Chapter 2 Introduction of the DE10-Advanced Board
2.1 Layout and Components
2.2 Block Diagram of the DE10-Advanced Board
3 Chapter 3 Board Setting and Status component
3.1 Board Setting Switches
3.1.1 USB Type C Connector Setting Switches
3.1.2 Mode Select Switches
3.2 Board Setting Headers
3.2.1 JTAG Interface Header
3.2.2 FMC_VCCIO Select Header
3.2.3 DDR4 VCCIO Select Header
3.2.4 External USB Blaster Header
3.3 Status LED
3.3.1 System MAX
3.3.2 UART Interface
3.3.3 SFP Interface
3.3.4 Ethernet Interface
3.3.5 Power
3.4 JTAG Interface
Chapter 4 FPGA Fabric component
4.1 USB Type C Port
4.2 Display Port
4.3 SFP+ Connector
The development board has four independent 10G SFP+ connectors that use one transceiver channel each from the Arria 10 SoC FPGA device. These modules take in serial data from the Arria 10 SoC FPGA device and transform them to optical signals. The board includes cage assemblies for the SFP+ connectors.Figure 4-3 shows the connections between the SFP+ and Arria 10 SoC FPGA.
- Figure 4-3 Connection between the SFP+ and Arria 10 SoC FPGA
- Figure 4-3 Connection between the SFP+ and Arria 10 SoC FPGA
Table 4-3, Table 4-4, Table 4-5 and Table 4-6 list the four QSF+ connectors assignments and signal names relative to the Arria 10 SoC FPGA
- Table 4-3 SFP+ A Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPA_TXDISABLE PIN_AR28 Turns off and disables the transmitter output 1.2V SFPA_TXFAULT PIN_AP28 Transmitter fault 1.2V SFPA_TX_p PIN_AG37 Transmiter data HSSI DIFFERENTIAL I/O SFPA_RX_p PIN_AD35 Receiver data HSSI DIFFERENTIAL I/O SFPA_LOS PIN_AN6 Signal loss indicator 1.2V SFPA_MOD0_PRSNT_n PIN_AU4 Module present 1.2V SFPA_RATESEL0 PIN_AM19 Rate select 0 3.3V SFPA_RATESEL1 PIN_AN17 Rate select 1 3.3V SFPA_TX_n PIN_AG36 Transmitter data HSSI DIFFERENTIAL I/O SFPA_RX_n PIN_AD34 Receiver data HSSI DIFFERENTIAL I/O
- Table 4-4 SFP+ B Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPB_TXDISABLE PIN_AU5 Turns off and disables the transmitter output 1.2V SFPB_TXFAULT PIN_AE10 Transmitter fault 1.2V SFPB_TX_p PIN_AF39 Transmiter data HSSI DIFFERENTIAL I/O SFPB_RX_p PIN_AC37 Receiver data HSSI DIFFERENTIAL I/O SFPB_LOS PIN_AN12 Signal loss indicator 1.2V SFPB_MOD0_PRSNT_n PIN_AT5 Module present 1.2V SFPB_RATESEL0 PIN_AR18 Rate select 0 3.3V SFPB_RATESEL1 PIN_AP18 Rate select 1 3.3V SFPB_TX_n PIN_AF38 Transmitter data HSSI DIFFERENTIAL I/O SFPB_RX_n PIN_AC36 Receiver data HSSI DIFFERENTIAL I/O
- Table 4-5 SFP+ C Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPC_TXDISABLE PIN_AP30 Turns off and disables the transmitter output 1.2V SFPC_TXFAULT PIN_AP28 Transmitter fault 1.2V SFPC_TX_p PIN_AE37 Transmiter data HSSI DIFFERENTIAL I/O SFPC_RX_p PIN_AC33 Receiver data HSSI DIFFERENTIAL I/O SFPC_LOS PIN_AN28 Signal loss indicator 1.2V SFPC_MOD0_PRSNT_n PIN_B27 Module present 1.2V SFPC_RATESEL0 PIN_AK18 Rate select 0 3.3V SFPC_RATESEL1 PIN_AR17 Rate select 1 3.3V SFPC_TX_n PIN_AE36 Transmitter data HSSI DIFFERENTIAL I/O SFPC_RX_n PIN_AC32 Receiver data HSSI DIFFERENTIAL I/O
- Table 4-6 SFP+ D Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPD_TXDISABLE PIN_AR28 Turns off and disables the transmitter output 1.2V SFPD_TXFAULT PIN_AP21 Transmitter fault 1.2V SFPD_TX_p PIN_AD39 Transmiter data HSSI DIFFERENTIAL I/O SFPD_RX_p PIN_AB35 Receiver data HSSI DIFFERENTIAL I/O SFPD_LOS PIN_D26 Signal loss indicator 1.2V SFPD_MOD0_PRSNT_n PIN_AL28 Module present 1.2V SFPD_RATESEL0 PIN_AH18 Rate select 0 3.3V SFPD_RATESEL1 PIN_AW19 Rate select 1 3.3V SFPD_TX_n PIN_AD38 Transmitter data HSSI DIFFERENTIAL I/O SFPD_RX_n PIN_AB34 Receiver data HSSI DIFFERENTIAL I/O
4.4 SATA
Four Serial ATA (SATA) ports are available on the FPGA development board which are computer bus standard with a primary function of transferring data between the motherboard and mass storage devices (such as hard drives, optical drives, and solid-state disks). Supporting a storage interface is just one of many different applications an FPGA can be used in storage appliances. The Arria 10 SoC device can bridge different protocols such as bridging simple bus I/Os like PCI Express (PCIe) to SATA or network interfaces such as Gigabit Ethernet (GbE) to SATA. The SATA interface supports SATA 3.0 standard with connection speed of 6 Gbps based on Arria 10 SoC device with integrated transceivers compliant to SATA electrical standards.
The four Serial ATA (SATA) ports include two available ports for device and two available ports for host capable of implementing SATA solution with a design that consists of both host and target(device side) functions.Figure 4-4 depicts the host and device design examples.
- Figure 4-4 PC and storage device connection to the Arria 10 SoC FPGA
- Figure 4-4 PC and storage device connection to the Arria 10 SoC FPGA
The transmitter and receiver signals of the SATA ports are connected directly to the Arria 10 SoC transceiver channels to provide SATA IO connectivity to both host and target devices. To verify the functionality of the SATA host/device ports, a connection can be established between the two ports by using a SATA cable as Figure 4-5 depicts the associated signals connected.Table 4-7 lists the SATA pin assignments, signal names and functions.
- Figure 4-5 Pin connection between SATA connectors
- Figure 4-5 Pin connection between SATA connectors
- Table 4-7 SATA Pin Assignments,Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard Device SATA_DEVICE_REFCLK_p PIN_M31 SATA Device reference clock LVDS SATA_DEVICE_REFCLK_n PIN_M30 SATA Device reference clock LVDS SATA_DEVICE_RX_n0 PIN_D34 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_RX_n1 PIN_B34 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_n0 PIN_B38 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_n1 PIN_A36 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_p0 PIN_B39 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_p1 PIN_A37 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_RX_p0 PIN_D35 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_RX_p1 PIN_B35 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O Host SATA_HOST_REFCLK_p PIN_AF31 SATA Host reference clock LVDS SATA_HOST_REFCLK_n PIN_AF30 SATA Host reference clock LVDS SATA_HOST_TX_p0 PIN_AJ37 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_TX_p1 PIN_AH39 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_p0 PIN_AE33 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_p1 PIN_AF35 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_TX_n0 PIN_AJ36 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_TX_n1 PIN_AH38 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_n0 PIN_AE32 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_n1 PIN_AF34 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O
4.5 PCIe
The DE10-Advanced development board features one PCIe Express downstream interfaces (x4 lane) which are designed to interface with a PC motherboard x4 slot via PCIe cable and PCIe adapter card. Utilizing built-in transceivers on a Arria 10 SoC device, it is able to provide a fully integrated PCI Express compliant solution for multi-lane (x4) applications. With the PCI Express hard IP block incorporated in the Arria 10 SoC device, it will allow users to implement simple and fast protocols, as well as saving logic resources for logic applications.
The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane, Gen2 at 5.0Gbps/lane, and Gen3 at 8.0Gbps/lane protocol stack solution compliant to PCI Express base specification 3.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks.
To use PCIe interface, two external associated devices will be needed to establish a link with PC. First, a PCIe half-height add-in host card with a PCIe x4 cable connector called PCA (PCIe Cabling Adapter Card and see Figure 4-5, it will be used to plug into the PCIe slot on a mother board.
- Figure 4-5 PCIe Cabling Adaptor(PCA) card
Then,a PCIe x4 cable(See Figure 4-6) will be used to connect DE10-Advanced board and PCIe add-in card, the longest length is up to 3 meters.These two associated devices are not included in DE10-Advanced board. To purchase the PCA card as well as the external cable, please refer to Terasic website PCIe x4 Cable Adapterand PCIe x4 Gen.2 Cable.Table 4-8 summarizes the PCI Express pin assignments of the signal names relative to the Arria 10 SoC FPGA.PCIe pin connection is showed in Figure 4-7.
- Figure 4-6 PCIe External Cable
- Figure 4-6 PCIe External Cable
- Figure 4-7 PCI Express Pin Connection
- Table 4-8 PCIe Pin Assignments,Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard PCIE_REFCLK_p PIN_AH31 PCIe reference clock LVDS PCIE_TX_p[0] PIN_AR37 PCIe Transmitter data p0 HSSI DIFFERENTIAL I/O PCIE_TX_p[1] PIN_AP39 PCIe Transmitter data p1 HSSI DIFFERENTIAL I/O PCIE_TX_p[2] PIN_AN37 PCIe Transmitter data p2 HSSI DIFFERENTIAL I/O PCIE_TX_p[3] PIN_AM39 PCIe Transmitter data p3 HSSI DIFFERENTIAL I/O PCIE_RX_p[0] PIN_AL33 PCIe Receiver data p0 HSSI DIFFERENTIAL I/O PCIE_RX_p[1] PIN_AM35 PCIe Receiver data p1 HSSI DIFFERENTIAL I/O PCIE_RX_p[2] PIN_AJ33 PCIe Receiver data p2 HSSI DIFFERENTIAL I/O PCIE_RX_p[3] PIN_AK35 PCIe Receiver data p3 HSSI DIFFERENTIAL I/O PCIE_PERST_n PIN_AW20 PCIe present,active low 1.8 V PCIE_WAKE_n PIN_AL19 PCIe wake 1.8 V
