DE10-Advance usermanual revB
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For applications requiring faster communications, the sensor and interrupt registers may be read using | For applications requiring faster communications, the sensor and interrupt registers may be read using | ||
SPI at 20MHz. For more detailed information of better using this chip, please refer to its datasheet | SPI at 20MHz. For more detailed information of better using this chip, please refer to its datasheet | ||
| - | which is available on manufacturer‟s website or under the /datasheet folder of the system CD. Table | + | which is available on manufacturer‟s website or under the /datasheet folder of the system CD. Table 4-13 |
gives the pin assignment information of the LCD touch panel. For more detailed information of better | gives the pin assignment information of the LCD touch panel. For more detailed information of better | ||
using this chip, please refer to its datasheet which is available on manufacturer‟s website or under the | using this chip, please refer to its datasheet which is available on manufacturer‟s website or under the | ||
Revision as of 17:16, 25 June 2018
Chapter 1 DE10-Advanced Development Kit
1.1 Package Contents
1.2 DE10-Advanced System CD
1.3 Getting Help
Chapter 2 Introduction of the DE10-Advanced Board
2.1 Layout and Components
2.2 Block Diagram of the DE10-Advanced Board
3 Chapter 3 Board Setting and Status component
3.1 Board Setting Switches
3.1.1 USB Type C Connector Setting Switches
3.1.2 Mode Select Switches
3.2 Board Setting Headers
3.2.1 JTAG Interface Header
3.2.2 FMC_VCCIO Select Header
3.2.3 DDR4 VCCIO Select Header
3.2.4 External USB Blaster Header
3.3 Status LED
3.3.1 System MAX
3.3.2 UART Interface
3.3.3 SFP Interface
3.3.4 Ethernet Interface
3.3.5 Power
3.4 JTAG Interface
Chapter 4 FPGA Fabric component
4.1 USB Type C Port
4.2 Display Port
4.3 SFP+ Connector
The development board has four independent 10G SFP+ connectors that use one transceiver channel each from the Arria 10 SoC FPGA device. These modules take in serial data from the Arria 10 SoC FPGA device and transform them to optical signals. The board includes cage assemblies for the SFP+ connectors.Figure 4-3 shows the connections between the SFP+ and Arria 10 SoC FPGA.
- Figure 4-3 Connection between the SFP+ and Arria 10 SoC FPGA
- Figure 4-3 Connection between the SFP+ and Arria 10 SoC FPGA
Table 4-3, Table 4-4, Table 4-5 and Table 4-6 list the four QSF+ connectors assignments and signal names relative to the Arria 10 SoC FPGA
- Table 4-3 SFP+ A Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPA_TXDISABLE PIN_AR28 Turns off and disables the transmitter output 1.2V SFPA_TXFAULT PIN_AP28 Transmitter fault 1.2V SFPA_TX_p PIN_AG37 Transmiter data HSSI DIFFERENTIAL I/O SFPA_RX_p PIN_AD35 Receiver data HSSI DIFFERENTIAL I/O SFPA_LOS PIN_AN6 Signal loss indicator 1.2V SFPA_MOD0_PRSNT_n PIN_AU4 Module present 1.2V SFPA_RATESEL0 PIN_AM19 Rate select 0 3.3V SFPA_RATESEL1 PIN_AN17 Rate select 1 3.3V SFPA_TX_n PIN_AG36 Transmitter data HSSI DIFFERENTIAL I/O SFPA_RX_n PIN_AD34 Receiver data HSSI DIFFERENTIAL I/O
- Table 4-4 SFP+ B Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPB_TXDISABLE PIN_AU5 Turns off and disables the transmitter output 1.2V SFPB_TXFAULT PIN_AE10 Transmitter fault 1.2V SFPB_TX_p PIN_AF39 Transmiter data HSSI DIFFERENTIAL I/O SFPB_RX_p PIN_AC37 Receiver data HSSI DIFFERENTIAL I/O SFPB_LOS PIN_AN12 Signal loss indicator 1.2V SFPB_MOD0_PRSNT_n PIN_AT5 Module present 1.2V SFPB_RATESEL0 PIN_AR18 Rate select 0 3.3V SFPB_RATESEL1 PIN_AP18 Rate select 1 3.3V SFPB_TX_n PIN_AF38 Transmitter data HSSI DIFFERENTIAL I/O SFPB_RX_n PIN_AC36 Receiver data HSSI DIFFERENTIAL I/O
- Table 4-5 SFP+ C Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPC_TXDISABLE PIN_AP30 Turns off and disables the transmitter output 1.2V SFPC_TXFAULT PIN_AP28 Transmitter fault 1.2V SFPC_TX_p PIN_AE37 Transmiter data HSSI DIFFERENTIAL I/O SFPC_RX_p PIN_AC33 Receiver data HSSI DIFFERENTIAL I/O SFPC_LOS PIN_AN28 Signal loss indicator 1.2V SFPC_MOD0_PRSNT_n PIN_B27 Module present 1.2V SFPC_RATESEL0 PIN_AK18 Rate select 0 3.3V SFPC_RATESEL1 PIN_AR17 Rate select 1 3.3V SFPC_TX_n PIN_AE36 Transmitter data HSSI DIFFERENTIAL I/O SFPC_RX_n PIN_AC32 Receiver data HSSI DIFFERENTIAL I/O
- Table 4-6 SFP+ D Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard SFPD_TXDISABLE PIN_AR28 Turns off and disables the transmitter output 1.2V SFPD_TXFAULT PIN_AP21 Transmitter fault 1.2V SFPD_TX_p PIN_AD39 Transmiter data HSSI DIFFERENTIAL I/O SFPD_RX_p PIN_AB35 Receiver data HSSI DIFFERENTIAL I/O SFPD_LOS PIN_D26 Signal loss indicator 1.2V SFPD_MOD0_PRSNT_n PIN_AL28 Module present 1.2V SFPD_RATESEL0 PIN_AH18 Rate select 0 3.3V SFPD_RATESEL1 PIN_AW19 Rate select 1 3.3V SFPD_TX_n PIN_AD38 Transmitter data HSSI DIFFERENTIAL I/O SFPD_RX_n PIN_AB34 Receiver data HSSI DIFFERENTIAL I/O
4.4 SATA
Four Serial ATA (SATA) ports are available on the FPGA development board which are computer bus standard with a primary function of transferring data between the motherboard and mass storage devices (such as hard drives, optical drives, and solid-state disks). Supporting a storage interface is just one of many different applications an FPGA can be used in storage appliances. The Arria 10 SoC device can bridge different protocols such as bridging simple bus I/Os like PCI Express (PCIe) to SATA or network interfaces such as Gigabit Ethernet (GbE) to SATA. The SATA interface supports SATA 3.0 standard with connection speed of 6 Gbps based on Arria 10 SoC device with integrated transceivers compliant to SATA electrical standards.
The four Serial ATA (SATA) ports include two available ports for device and two available ports for host capable of implementing SATA solution with a design that consists of both host and target(device side) functions.Figure 4-4 depicts the host and device design examples.
- Figure 4-4 PC and storage device connection to the Arria 10 SoC FPGA
- Figure 4-4 PC and storage device connection to the Arria 10 SoC FPGA
The transmitter and receiver signals of the SATA ports are connected directly to the Arria 10 SoC transceiver channels to provide SATA IO connectivity to both host and target devices. To verify the functionality of the SATA host/device ports, a connection can be established between the two ports by using a SATA cable as Figure 4-5 depicts the associated signals connected.Table 4-7 lists the SATA pin assignments, signal names and functions.
- Figure 4-5 Pin connection between SATA connectors
- Figure 4-5 Pin connection between SATA connectors
- Table 4-7 SATA Pin Assignments,Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard Device SATA_DEVICE_REFCLK_p PIN_M31 SATA Device reference clock LVDS SATA_DEVICE_REFCLK_n PIN_M30 SATA Device reference clock LVDS SATA_DEVICE_RX_n0 PIN_D34 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_RX_n1 PIN_B34 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_n0 PIN_B38 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_n1 PIN_A36 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_p0 PIN_B39 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_TX_p1 PIN_A37 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_RX_p0 PIN_D35 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_DEVICE_RX_p1 PIN_B35 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O Host SATA_HOST_REFCLK_p PIN_AF31 SATA Host reference clock LVDS SATA_HOST_REFCLK_n PIN_AF30 SATA Host reference clock LVDS SATA_HOST_TX_p0 PIN_AJ37 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_TX_p1 PIN_AH39 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_p0 PIN_AE33 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_p1 PIN_AF35 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_TX_n0 PIN_AJ36 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_TX_n1 PIN_AH38 Differential transmit data output before DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_n0 PIN_AE32 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O SATA_HOST_RX_n1 PIN_AF34 Differential receive data input after DC blocking capacitor HSSI DIFFERENTIAL I/O
4.5 PCIe
The DE10-Advanced development board features one PCIe Express downstream interfaces (x4 lane) which are designed to interface with a PC motherboard x4 slot via PCIe cable and PCIe adapter card. Utilizing built-in transceivers on a Arria 10 SoC device, it is able to provide a fully integrated PCI Express compliant solution for multi-lane (x4) applications. With the PCI Express hard IP block incorporated in the Arria 10 SoC device, it will allow users to implement simple and fast protocols, as well as saving logic resources for logic applications.
The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane, Gen2 at 5.0Gbps/lane, and Gen3 at 8.0Gbps/lane protocol stack solution compliant to PCI Express base specification 3.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks.
To use PCIe interface, two external associated devices will be needed to establish a link with PC. First, a PCIe half-height add-in host card with a PCIe x4 cable connector called PCA (PCIe Cabling Adapter Card and see Figure 4-5, it will be used to plug into the PCIe slot on a mother board.
- Figure 4-5 PCIe Cabling Adaptor(PCA) card
Then,a PCIe x4 cable(See Figure 4-6) will be used to connect DE10-Advanced board and PCIe add-in card, the longest length is up to 3 meters.These two associated devices are not included in DE10-Advanced board. To purchase the PCA card as well as the external cable, please refer to Terasic website PCIe x4 Cable Adapterand PCIe x4 Gen.2 Cable.Table 4-8 summarizes the PCI Express pin assignments of the signal names relative to the Arria 10 SoC FPGA.PCIe pin connection is showed in Figure 4-7.
- Figure 4-6 PCIe External Cable
- Figure 4-6 PCIe External Cable
- Figure 4-7 PCI Express Pin Connection
- Table 4-8 PCIe Pin Assignments,Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard PCIE_REFCLK_p PIN_AH31 PCIe reference clock LVDS PCIE_TX_p[0] PIN_AR37 PCIe Transmitter data p0 HSSI DIFFERENTIAL I/O PCIE_TX_p[1] PIN_AP39 PCIe Transmitter data p1 HSSI DIFFERENTIAL I/O PCIE_TX_p[2] PIN_AN37 PCIe Transmitter data p2 HSSI DIFFERENTIAL I/O PCIE_TX_p[3] PIN_AM39 PCIe Transmitter data p3 HSSI DIFFERENTIAL I/O PCIE_RX_p[0] PIN_AL33 PCIe Receiver data p0 HSSI DIFFERENTIAL I/O PCIE_RX_p[1] PIN_AM35 PCIe Receiver data p1 HSSI DIFFERENTIAL I/O PCIE_RX_p[2] PIN_AJ33 PCIe Receiver data p2 HSSI DIFFERENTIAL I/O PCIE_RX_p[3] PIN_AK35 PCIe Receiver data p3 HSSI DIFFERENTIAL I/O PCIE_PERST_n PIN_AW20 PCIe present,active low 1.8 V PCIE_WAKE_n PIN_AL19 PCIe wake 1.8 V
4.6 DDR4
4.7 HDMI TX
4.8 HDMI RX
4.9 Gigabit Ethernet
The development board supports one RJ45 10/100/1000 base-T Ethernet using Marvell 88E1111. SGMII AC coupling interface is used between PHY and FPGA transceiver.The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Arria 10 SoC FPGA can communicate with the LVDS interfaces at up to 1.6 Gbps, which is faster than 1.25 Gbps for SGMII. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.1-V power rails and requires a 25MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 with internal magnetics for driving copper lines with Ethernet traffic.Figure 4-2 shows the SGMII interface between the FPGA and Marvell 88E1111 PHY. Table 4-2 lists the Ethernet PHY interface pin assignments.
- Figure 4-2 SGMII Interface between FPGA and Marvell 88E1111 PHY
- Table 4-2 Ethernet PHY Pin Assignments, Signal Names and Functions
Signal Name FPGA Pin Number Description I/O Standard ETH_TX_p PIN_AP19 SGMII TX data LVDS ETH_RX_p PIN_AM20 SGMII RX data LVDS ETH_INT_n PIN_AU19 Management bus interrupt 1.8V ETH_MDC PIN_AT19 Management bus control 1.8V ETH_MDIO PIN_AJ20 Management bus data 1.8V ETH_RST_n PIN_AK20 Device reset 1.8V
4.10 FMC Connector
The FPGA Mezzanine Card (FMC) interface provides a mechanism to extend the peripheral-set of an FPGA host board by means of add-on daughter cards, which can address today’s high speed signaling requirements as well as low-speed device interface support.The FMC interfaces support JTAG,clock outputs and inputs,high-speed serial I/O (transceivers),and single-ended or differential signaling.
There is one FMC connector on the DE10-Advanced board,it is a High Pin Count (HPC) size of connector,The HPC connector on DE10-Advanced board can provides 172 user-define,single-ended signals (include clock signals) and 10 serial transceiver pairs.Figure 4-10 is the FMC connector on DE10-Advanced board
- Figure 4-10 FMC connector on DE10-Advanced board
- Table 4-11 FMC Connector Pin Assignments, Signal Names and Functions
- Figure 4-10 FMC connector on DE10-Advanced board
Signal Name FPGA Pin Number Description I/O Standard FMC_CLK2_BIDIR_p PIN_AW18 FMC bidirection Clock signal 1.8 V FMC_CLK2_BIDIR_n PIN_AV17 FMC bidirection Clock signal 1.8 V FMC_CLK3_BIDIR_p PIN_C1 FMC bidirection Clock signal 1.8 V FMC_CLK3_BIDIR_n PIN_D1 FMC bidirection Clock signal 1.8 V FMC_CLK_M2C_p[0] PIN_K5 Clock input 0 1.8 V FMC_CLK_M2C_p[1] PIN_AW14 Clock input 1 1.8 V FMC_CLK_M2C_n[0] PIN_L5 Clock input 0 1.8 V FMC_CLK_M2C_n[1] PIN_AW15 Clock input 1 1.8 V FMC_HA_p[0] PIN_K12 FMC data bus 1.8 V FMC_HA_p[1] PIN_M12 FMC data bus 1.8 V FMC_HA_p[2] PIN_D10 FMC data bus 1.8 V FMC_HA_p[3] PIN_E12 FMC data bus 1.8 V FMC_HA_p[4] PIN_H13 FMC data bus 1.8 V FMC_HA_p[5] PIN_J11 FMC data bus 1.8 V FMC_HA_p[6] PIN_N13 FMC data bus 1.8 V FMC_HA_p[7] PIN_L13 FMC data bus 1.8 V FMC_HA_p[8] PIN_J14 FMC data bus 1.8 V FMC_HA_p[9] PIN_F13 FMC data bus 1.8 V FMC_HA_p[10] PIN_D13 FMC data bus 1.8 V FMC_HA_p[11] PIN_G14 FMC data bus 1.8 V FMC_HA_p[12] PIN_A10 FMC data bus 1.8 V FMC_HA_p[13] PIN_G12 FMC data bus 1.8 V FMC_HA_p[14] PIN_A12 FMC data bus 1.8 V FMC_HA_p[15] PIN_A7 FMC data bus 1.8 V FMC_HA_p[16] PIN_A9 FMC data bus 1.8 V FMC_HA_p[17] PIN_C12 FMC data bus 1.8 V FMC_HA_p[18] PIN_B11 FMC data bus 1.8 V FMC_HA_p[19] PIN_M7 FMC data bus 1.8 V FMC_HA_p[20] PIN_F10 FMC data bus 1.8 V FMC_HA_p[21] PIN_C9 FMC data bus 1.8 V FMC_HA_p[22] PIN_C8 FMC data bus 1.8 V FMC_HA_p[23] PIN_G11 FMC data bus 1.8 V FMC_HA_n[0] PIN_L12 FMC data bus 1.8 V FMC_HA_n[1] PIN_N12 FMC data bus 1.8 V FMC_HA_n[2] PIN_E10 FMC data bus 1.8 V FMC_HA_n[3] PIN_F12 FMC data bus 1.8 V FMC_HA_n[4] PIN_J13 FMC data bus 1.8 V FMC_HA_n[5] PIN_K11 FMC data bus 1.8 V FMC_HA_n[6] PIN_P13 FMC data bus 1.8 V FMC_HA_n[7] PIN_L14 FMC data bus 1.8 V FMC_HA_n[8] PIN_K13 FMC data bus 1.8 V FMC_HA_n[9] PIN_F14 FMC data bus 1.8 V FMC_HA_n[10] PIN_E13 FMC data bus 1.8 V FMC_HA_n[11] PIN_H14 FMC data bus 1.8 V FMC_HA_n[12] PIN_B10 FMC data bus 1.8 V FMC_HA_n[13] PIN_H12 FMC data bus 1.8 V FMC_HA_n[14] PIN_B12 FMC data bus 1.8 V FMC_HA_n[15] PIN_A8 FMC data bus 1.8 V FMC_HA_n[16] PIN_B9 FMC data bus 1.8 V FMC_HA_n[17] PIN_C13 FMC data bus 1.8 V FMC_HA_n[18] PIN_C11 FMC data bus 1.8 V FMC_HA_n[19] PIN_N7 FMC data bus 1.8 V FMC_HA_n[20] PIN_G10 FMC data bus 1.8 V FMC_HA_n[21] PIN_D9 FMC data bus 1.8 V FMC_HA_n[22] PIN_D8 FMC data bus 1.8 V FMC_HA_n[23] PIN_H11 FMC data bus 1.8 V FMC_HB_p[0] PIN_E1 FMC data bus 1.8 V FMC_HB_p[1] PIN_G4 FMC data bus 1.8 V FMC_HB_p[2] PIN_N8 FMC data bus 1.8 V FMC_HB_p[3] PIN_J4 FMC data bus 1.8 V FMC_HB_p[4] PIN_H2 FMC data bus 1.8 V FMC_HB_p[5] PIN_G5 FMC data bus 1.8 V FMC_HB_p[6] PIN_D3 FMC data bus 1.8 V FMC_HB_p[7] PIN_A2 FMC data bus 1.8 V FMC_HB_p[8] PIN_B1 FMC data bus 1.8 V FMC_HB_p[9] PIN_AT13 FMC data bus 1.8 V FMC_HB_p[10] PIN_AM17 FMC data bus 1.8 V FMC_HB_p[11] PIN_AJ16 FMC data bus 1.8 V FMC_HB_p[12] PIN_AW13 FMC data bus 1.8 V FMC_HB_p[13] PIN_AV14 FMC data bus 1.8 V FMC_HB_p[14] PIN_AP14 FMC data bus 1.8 V FMC_HB_p[15] PIN_AK16 FMC data bus 1.8 V FMC_HB_p[16] PIN_AU16 FMC data bus 1.8 V FMC_HB_p[17] PIN_AT17 FMC data bus 1.8 V FMC_HB_p[18] PIN_AM15 FMC data bus 1.8 V FMC_HB_p[19] PIN_AR15 FMC data bus 1.8 V FMC_HB_p[20] PIN_AP16 FMC data bus 1.8 V FMC_HB_p[21] PIN_AV18 FMC data bus 1.8 V FMC_HB_n[0] PIN_E2 FMC data bus 1.8 V FMC_HB_n[1] PIN_H4 FMC data bus 1.8 V FMC_HB_n[2] PIN_P8 FMC data bus 1.8 V FMC_HB_n[3] PIN_J5 FMC data bus 1.8 V FMC_HB_n[4] PIN_H3 FMC data bus 1.8 V FMC_HB_n[5] PIN_H6 FMC data bus 1.8 V FMC_HB_n[6] PIN_E3 FMC data bus 1.8 V FMC_HB_n[7] PIN_B2 FMC data bus 1.8 V FMC_HB_n[8] PIN_C2 FMC data bus 1.8 V FMC_HB_n[9] PIN_AT14 FMC data bus 1.8 V FMC_HB_n[10] PIN_AL17 FMC data bus 1.8 V FMC_HB_n[11] PIN_AH16 FMC data bus 1.8 V FMC_HB_n[12] PIN_AV13 FMC data bus 1.8 V FMC_HB_n[13] PIN_AU14 FMC data bus 1.8 V FMC_HB_n[14] PIN_AP15 FMC data bus 1.8 V FMC_HB_n[15] PIN_AK17 FMC data bus 1.8 V FMC_HB_n[16] PIN_AU17 FMC data bus 1.8 V FMC_HB_n[17] PIN_AT18 FMC data bus 1.8 V FMC_HB_n[18] PIN_AM16 FMC data bus 1.8 V FMC_HB_n[19] PIN_AR16 FMC data bus 1.8 V FMC_HB_n[20] PIN_AN16 FMC data bus 1.8 V FMC_HB_n[21] PIN_AV19 FMC data bus 1.8 V FMC_LA_p[0] PIN_A3 FMC data bus 1.8 V FMC_LA_p[1] PIN_B4 FMC data bus 1.8 V FMC_LA_p[2] PIN_T9 FMC data bus 1.8 V FMC_LA_p[3] PIN_M10 FMC data bus 1.8 V FMC_LA_p[4] PIN_U9 FMC data bus 1.8 V FMC_LA_p[5] PIN_J10 FMC data bus 1.8 V FMC_LA_p[6] PIN_H8 FMC data bus 1.8 V FMC_LA_p[7] PIN_L9 FMC data bus 1.8 V FMC_LA_p[8] PIN_M9 FMC data bus 1.8 V FMC_LA_p[9] PIN_G6 FMC data bus 1.8 V FMC_LA_p[10] PIN_E8 FMC data bus 1.8 V FMC_LA_p[11] PIN_B6 FMC data bus 1.8 V FMC_LA_p[12] PIN_A5 FMC data bus 1.8 V FMC_LA_p[13] PIN_D5 FMC data bus 1.8 V FMC_LA_p[14] PIN_B7 FMC data bus 1.8 V FMC_LA_p[15] PIN_E6 FMC data bus 1.8 V FMC_LA_p[16] PIN_E5 FMC data bus 1.8 V FMC_LA_p[17] PIN_F9 FMC data bus 1.8 V FMC_LA_p[18] PIN_K8 FMC data bus 1.8 V FMC_LA_p[19] PIN_R8 FMC data bus 1.8 V FMC_LA_p[20] PIN_F7 FMC data bus 1.8 V FMC_LA_p[21] PIN_C4 FMC data bus 1.8 V FMC_LA_p[22] PIN_U11 FMC data bus 1.8 V FMC_LA_p[23] PIN_V11 FMC data bus 1.8 V FMC_LA_p[24] PIN_R11 FMC data bus 1.8 V FMC_LA_p[25] PIN_F2 FMC data bus 1.8 V FMC_LA_p[26] PIN_R7 FMC data bus 1.8 V FMC_LA_p[27] PIN_T12 FMC data bus 1.8 V FMC_LA_p[28] PIN_J6 FMC data bus 1.8 V FMC_LA_p[29] PIN_G1 FMC data bus 1.8 V FMC_LA_p[30] PIN_K7 FMC data bus 1.8 V FMC_LA_p[31] PIN_P10 FMC data bus 1.8 V FMC_LA_p[32] PIN_M6 FMC data bus 1.8 V FMC_LA_p[33] PIN_N11 FMC data bus 1.8 V FMC_LA_n[0] PIN_A4 FMC data bus 1.8 V FMC_LA_n[1] PIN_C3 FMC data bus 1.8 V FMC_LA_n[2] PIN_T10 FMC data bus 1.8 V FMC_LA_n[3] PIN_M11 FMC data bus 1.8 V FMC_LA_n[4] PIN_U10 FMC data bus 1.8 V FMC_LA_n[5] PIN_K10 FMC data bus 1.8 V FMC_LA_n[6] PIN_J8 FMC data bus 1.8 V FMC_LA_n[7] PIN_L10 FMC data bus 1.8 V FMC_LA_n[8] PIN_N9 FMC data bus 1.8 V FMC_LA_n[9] PIN_H7 FMC data bus 1.8 V FMC_LA_n[10] PIN_F8 FMC data bus 1.8 V FMC_LA_n[11] PIN_C6 FMC data bus 1.8 V FMC_LA_n[12] PIN_B5 FMC data bus 1.8 V FMC_LA_n[13] PIN_D6 FMC data bus 1.8 V FMC_LA_n[14] PIN_C7 FMC data bus 1.8 V FMC_LA_n[15] PIN_E7 FMC data bus 1.8 V FMC_LA_n[16] PIN_F5 FMC data bus 1.8 V FMC_LA_n[17] PIN_G9 FMC data bus 1.8 V FMC_LA_n[18] PIN_L8 FMC data bus 1.8 V FMC_LA_n[19] PIN_P9 FMC data bus 1.8 V FMC_LA_n[20] PIN_G7 FMC data bus 1.8 V FMC_LA_n[21] PIN_D4 FMC data bus 1.8 V FMC_LA_n[22] PIN_U12 FMC data bus 1.8 V FMC_LA_n[23] PIN_V12 FMC data bus 1.8 V FMC_LA_n[24] PIN_R12 FMC data bus 1.8 V FMC_LA_n[25] PIN_G2 FMC data bus 1.8 V FMC_LA_n[26] PIN_T8 FMC data bus 1.8 V FMC_LA_n[27] PIN_T13 FMC data bus 1.8 V FMC_LA_n[28] PIN_K6 FMC data bus 1.8 V FMC_LA_n[29] PIN_H1 FMC data bus 1.8 V FMC_LA_n[30] PIN_L7 FMC data bus 1.8 V FMC_LA_n[31] PIN_R10 FMC data bus 1.8 V FMC_LA_n[32] PIN_N6 FMC data bus 1.8 V FMC_LA_n[33] PIN_P11 FMC data bus 1.8 V FMC_GBTCLK_M2C_p[0] PIN_P31 LVDS input from the installed FMC card to dedicated reference clock inputs LVDS FMC_GBTCLK_M2C_p[1] PIN_K31 LVDS input from the installed FMC card to dedicated reference clock inputs LVDS FMC_REFCLK_p PIN_T31 Reference Clock LVDS FMC_DP_C2M_p[0] PIN_M39 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[1] PIN_L37 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[2] PIN_K39 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[3] PIN_J37 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[4] PIN_H39 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[5] PIN_G37 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[6] PIN_F39 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[7] PIN_E37 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[8] PIN_D39 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_C2M_p[9] PIN_C37 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[0] PIN_P35 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[1] PIN_R33 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[2] PIN_M35 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[3] PIN_N33 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[4] PIN_K35 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[5] PIN_L33 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[6] PIN_H35 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[7] PIN_J33 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[8] PIN_F35 Transmit channel HSSI DIFFERENTIAL I/O FMC_DP_M2C_p[9] PIN_G33 Transmit channel HSSI DIFFERENTIAL I/O FMC_GA[0] PIN_E11 FMC geographical address 0 1.8 V FMC_GA[1] PIN_AL18 FMC geographical address 1 1.8 V FMC_SCL PIN_J9 Management serial clock line 1.8 V FMC_SDA PIN_F4 Management serial data line 1.8 V
4.11 Temperature Sensor,Fan Control and Power Monitor
The FPGA board is equipped with a temperature sensor, TMP441AIDCNT, which provides temperature sensing.This functions is accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Arria 10 SoC device. The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two-wire SMBus, which is connected to the Arria 10 SoC FPGA. In addition, the 7-bit POR slave address for this sensor is set to‘0011100b'.
A 3-pin +12V fan located on J22 of the FPGA board is intended to reduce the temperature of the FPGA.The board is equipped with a Fan-Speed regulator and monitor MAX6650 with an I2C/SMBus interfaces,Users regulate and monitor the speed of fan depending on the measured system temperature.
The DE10-Advanced has implemented a power monitor chip to monitor the board input power voltage and current.Figure 4-10 shows the connection between the power monitor chip and the Arria 10 SoC FPGA.The power monitor chip monitors both shunt voltage drops and board input power voltage allows user to monitor the total board power consumption. Programmable calibration value,conversion times,and averaging,combined with an internal multiplier,enable direct readouts of current in amperes and power in watts.Note that,the temperature sensor,fan control and power monitor share the same I2C/SMBUS.
Figure 4-10 Connections between the temperature sensor/fan control/power monitor and the Arria 10 SoC FPGA
- Table 4-12 Temperature Sensor and Fan Speed Control Pin Assignments,Schematic Signal Names and Functions
Schematic Signal Name Description I/O Standard Arria 10 SoC Pin Number TEMPDIODEp Positive pin of temperature diode in Arria 10 -- -- TEMPDIODEn Negative pin of temperature diode in Arria 10 -- -- FPGA_I2C_SCL SMBus clock 1.8V M1 FPGA_I2C_SDA SMBus data 1.8V M4 FAN_ALERT Active-low ALERT input 1.8V E25
4.12 Gyroscope, Accelerometer and Magnetometer
The VEEK-MT2 is equipped with a Motion-Tracking device named MPU-9250. The MPU-9250 is a 9-axis Motion-Tracking device that combines a 3-axis gyroscope, 3-axis accelerometer and 3-axis magnetometer. Detail features of these sensors are listed below.
Gyroscope
The MPU-9250 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a wide range of cut-off frequencies.
Accelerometer
The MPU-9250‟s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The MPU-9250‟s architecture reduces the accelerometers‟ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers‟ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
Magnetometer
The 3-axis magnetometer uses highly sensitive Hall sensor technology. The magnetometer portion of the IC incorporates magnetic sensors for detecting terrestrial magnetism in the X-, Y-, and Z- Axes, a sensor driving circuit, a signal amplifier chain, and an arithmetic circuit for processing the signal from each sensor. Each ADC has a 16-bit resolution and a full scale range of ±4800 μT. Communication with all registers of the device is performed using either I2C at 400kHz or SPI at 1MHz. For applications requiring faster communications, the sensor and interrupt registers may be read using SPI at 20MHz. For more detailed information of better using this chip, please refer to its datasheet which is available on manufacturer‟s website or under the /datasheet folder of the system CD. Table 4-13 gives the pin assignment information of the LCD touch panel. For more detailed information of better using this chip, please refer to its datasheet which is available on manufacturer‟s website or under the /datasheet folder of the system CD.
