From Terasic Wiki

Contents 1 Chapter 1 DE10-Advanced Development Kit 1.1 1.1 Package Contents 1.2 1.2 DE10-Advanced System CD 1.3 1.3 Getting Help 2 Chapter 2 Introduction of the DE10-Advanced Board 2.1 2.1 Layout and Components 2.2 2.2 Block Diagram of the DE10-Advanced Board 3 3 Chapter 3 Board Setting and Status component 3.1 3.1 Board Setting Switches 3.1.1 3.1.1 USB Type C Connector Setting Switches 3.1.2 3.1.2 Mode Select Switches 3.2 3.2 Board Setting Headers 3.2.1 3.2.1 JTAG Interface Header 3.2.2 3.2.2 FMC_VCCIO Select Header 3.2.3 3.2.3 DDR4 VCCIO Select Header 3.2.4 3.2.4 External USB Blaster Header 3.3 3.3 Status LED 3.3.1 3.3.1 System MAX 3.3.2 3.3.2 UART Interface 3.3.3 3.3.3 SFP Interface 3.3.4 3.3.4 Ethernet Interface 3.3.5 3.3.5 Power 3.4 3.4 JTAG Interface 4 Chapter 4 FPGA Fabric component 4.1 4.1 USB Type C Port 4.2 4.2 Display Port 4.3 4.3 SFP+ Connector 4.4 4.4 SATA 4.5 4.5 PCIe 4.6 4.6 DDR4 4.7 4.7 HDMI TX 4.8 4.8 HDMI RX 4.9 4.9 Gigabit Ethernet 4.10 4.10 FMC Connector 4.11 4.11 Temperature Sensor,Fan Control and Power Monitor 4.12 4.12 Gyroscope, Accelerometer and Magnetometer 4.12.1 Gyroscope 4.12.2 Accelerometer 4.12.3 Magnetometer 4.13 4.13 User Interface (LED/7-SEG/Button/Switch) 5 Chapter 5 HPS Fabric Component 5.1 5.1 User Push-buttons and LEDs 5.2 5.2 Gigabit Ethernet 5.3 5.3 UART to USB 5.4 5.4 Micro SD Card Socket 5.5 5.5 USB OTG 6 Chapter 6 System Clocks 7 Chapter 7 Power and Reset 7.1 7.1 Power Supply 7.2 7.2 Power Tree 7.3 7.3 Reset 7.3.1 7.3.1 HPS Reset 7.3.2 7.3.2 PCIe Reset 7.3.3 7.3.3 MAX V Reset 7.3.4 7.3.4 HPS USB Reset

Chapter 1 DE10-Advanced Development Kit

1.1 Package Contents

1.2 DE10-Advanced System CD

1.3 Getting Help

Chapter 2 Introduction of the DE10-Advanced Board

2.1 Layout and Components

2.2 Block Diagram of the DE10-Advanced Board

3 Chapter 3 Board Setting and Status component

3.1 Board Setting Switches

3.1.1 USB Type C Connector Setting Switches

3.1.2 Mode Select Switches

3.2 Board Setting Headers

3.2.1 JTAG Interface Header

3.2.2 FMC_VCCIO Select Header

3.2.3 DDR4 VCCIO Select Header

3.2.4 External USB Blaster Header

3.3 Status LED

3.3.1 System MAX

3.3.2 UART Interface

3.3.3 SFP Interface

3.3.4 Ethernet Interface

3.3.5 Power

3.4 JTAG Interface

Chapter 4 FPGA Fabric component

4.1 USB Type C Port

4.2 Display Port

4.3 SFP+ Connector

The development board has four independent 10G SFP+ connectors that use one transceiver channel each from the Arria 10 SoC FPGA device. These modules take in serial data from the Arria 10 SoC FPGA device and transform them to optical signals. The board includes cage assemblies for the SFP+ connectors.Figure 4-3 shows the connections between the SFP+ and Arria 10 SoC FPGA.

Figure 4-3 Connection between the SFP+ and Arria 10 SoC FPGA

Table 4-3, Table 4-4, Table 4-5 and Table 4-6 list the four QSF+ connectors assignments and signal names relative to the Arria 10 SoC FPGA

Table 4-3 SFP+ A Pin Assignments, Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
SFPA_TXDISABLE	PIN_AR28	Turns off and disables the transmitter output	1.2V
SFPA_TXFAULT	PIN_AP28	Transmitter fault	1.2V
SFPA_TX_p	PIN_AG37	Transmiter data	HSSI DIFFERENTIAL I/O
SFPA_RX_p	PIN_AD35	Receiver data	HSSI DIFFERENTIAL I/O
SFPA_LOS	PIN_AN6	Signal loss indicator	1.2V
SFPA_MOD0_PRSNT_n	PIN_AU4	Module present	1.2V
SFPA_RATESEL0	PIN_AM19	Rate select 0	3.3V
SFPA_RATESEL1	PIN_AN17	Rate select 1	3.3V
SFPA_TX_n	PIN_AG36	Transmitter data	HSSI DIFFERENTIAL I/O
SFPA_RX_n	PIN_AD34	Receiver data	HSSI DIFFERENTIAL I/O

Table 4-4 SFP+ B Pin Assignments, Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
SFPB_TXDISABLE	PIN_AU5	Turns off and disables the transmitter output	1.2V
SFPB_TXFAULT	PIN_AE10	Transmitter fault	1.2V
SFPB_TX_p	PIN_AF39	Transmiter data	HSSI DIFFERENTIAL I/O
SFPB_RX_p	PIN_AC37	Receiver data	HSSI DIFFERENTIAL I/O
SFPB_LOS	PIN_AN12	Signal loss indicator	1.2V
SFPB_MOD0_PRSNT_n	PIN_AT5	Module present	1.2V
SFPB_RATESEL0	PIN_AR18	Rate select 0	3.3V
SFPB_RATESEL1	PIN_AP18	Rate select 1	3.3V
SFPB_TX_n	PIN_AF38	Transmitter data	HSSI DIFFERENTIAL I/O
SFPB_RX_n	PIN_AC36	Receiver data	HSSI DIFFERENTIAL I/O

Table 4-5 SFP+ C Pin Assignments, Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
SFPC_TXDISABLE	PIN_AP30	Turns off and disables the transmitter output	1.2V
SFPC_TXFAULT	PIN_AP28	Transmitter fault	1.2V
SFPC_TX_p	PIN_AE37	Transmiter data	HSSI DIFFERENTIAL I/O
SFPC_RX_p	PIN_AC33	Receiver data	HSSI DIFFERENTIAL I/O
SFPC_LOS	PIN_AN28	Signal loss indicator	1.2V
SFPC_MOD0_PRSNT_n	PIN_B27	Module present	1.2V
SFPC_RATESEL0	PIN_AK18	Rate select 0	3.3V
SFPC_RATESEL1	PIN_AR17	Rate select 1	3.3V
SFPC_TX_n	PIN_AE36	Transmitter data	HSSI DIFFERENTIAL I/O
SFPC_RX_n	PIN_AC32	Receiver data	HSSI DIFFERENTIAL I/O

Table 4-6 SFP+ D Pin Assignments, Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
SFPD_TXDISABLE	PIN_AR28	Turns off and disables the transmitter output	1.2V
SFPD_TXFAULT	PIN_AP21	Transmitter fault	1.2V
SFPD_TX_p	PIN_AD39	Transmiter data	HSSI DIFFERENTIAL I/O
SFPD_RX_p	PIN_AB35	Receiver data	HSSI DIFFERENTIAL I/O
SFPD_LOS	PIN_D26	Signal loss indicator	1.2V
SFPD_MOD0_PRSNT_n	PIN_AL28	Module present	1.2V
SFPD_RATESEL0	PIN_AH18	Rate select 0	3.3V
SFPD_RATESEL1	PIN_AW19	Rate select 1	3.3V
SFPD_TX_n	PIN_AD38	Transmitter data	HSSI DIFFERENTIAL I/O
SFPD_RX_n	PIN_AB34	Receiver data	HSSI DIFFERENTIAL I/O

4.4 SATA

Four Serial ATA (SATA) ports are available on the FPGA development board which are computer bus standard with a primary function of transferring data between the motherboard and mass storage devices (such as hard drives, optical drives, and solid-state disks). Supporting a storage interface is just one of many different applications an FPGA can be used in storage appliances. The Arria 10 SoC device can bridge different protocols such as bridging simple bus I/Os like PCI Express (PCIe) to SATA or network interfaces such as Gigabit Ethernet (GbE) to SATA. The SATA interface supports SATA 3.0 standard with connection speed of 6 Gbps based on Arria 10 SoC device with integrated transceivers compliant to SATA electrical standards.
The four Serial ATA (SATA) ports include two available ports for device and two available ports for host capable of implementing SATA solution with a design that consists of both host and target(device side) functions.Figure 4-4 depicts the host and device design examples.

Figure 4-4 PC and storage device connection to the Arria 10 SoC FPGA

The transmitter and receiver signals of the SATA ports are connected directly to the Arria 10 SoC transceiver channels to provide SATA IO connectivity to both host and target devices. To verify the functionality of the SATA host/device ports, a connection can be established between the two ports by using a SATA cable as Figure 4-5 depicts the associated signals connected.Table 4-7 lists the SATA pin assignments, signal names and functions.

Figure 4-5 Pin connection between SATA connectors

Table 4-7 SATA Pin Assignments,Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
Device
SATA_DEVICE_REFCLK_p	PIN_M31	SATA Device reference clock	LVDS
SATA_DEVICE_REFCLK_n	PIN_M30	SATA Device reference clock	LVDS
SATA_DEVICE_RX_n0	PIN_D34	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_RX_n1	PIN_B34	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_TX_n0	PIN_B38	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_TX_n1	PIN_A36	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_TX_p0	PIN_B39	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_TX_p1	PIN_A37	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_RX_p0	PIN_D35	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_DEVICE_RX_p1	PIN_B35	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
Host
SATA_HOST_REFCLK_p	PIN_AF31	SATA Host reference clock	LVDS
SATA_HOST_REFCLK_n	PIN_AF30	SATA Host reference clock	LVDS
SATA_HOST_TX_p0	PIN_AJ37	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_TX_p1	PIN_AH39	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_RX_p0	PIN_AE33	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_RX_p1	PIN_AF35	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_TX_n0	PIN_AJ36	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_TX_n1	PIN_AH38	Differential transmit data output before DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_RX_n0	PIN_AE32	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O
SATA_HOST_RX_n1	PIN_AF34	Differential receive data input after DC blocking capacitor	HSSI DIFFERENTIAL I/O

4.5 PCIe

The DE10-Advanced development board features one PCIe Express downstream interfaces (x4 lane) which are designed to interface with a PC motherboard x4 slot via PCIe cable and PCIe adapter card. Utilizing built-in transceivers on a Arria 10 SoC device, it is able to provide a fully integrated PCI Express compliant solution for multi-lane (x4) applications. With the PCI Express hard IP block incorporated in the Arria 10 SoC device, it will allow users to implement simple and fast protocols, as well as saving logic resources for logic applications.

The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane, Gen2 at 5.0Gbps/lane, and Gen3 at 8.0Gbps/lane protocol stack solution compliant to PCI Express base specification 3.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks.

To use PCIe interface, two external associated devices will be needed to establish a link with PC. First, a PCIe half-height add-in host card with a PCIe x4 cable connector called PCA (PCIe Cabling Adapter Card and see Figure 4-5, it will be used to plug into the PCIe slot on a mother board.

Figure 4-5 PCIe Cabling Adaptor(PCA) card

Then,a PCIe x4 cable(See Figure 4-6) will be used to connect DE10-Advanced board and PCIe add-in card, the longest length is up to 3 meters.These two associated devices are not included in DE10-Advanced board. To purchase the PCA card as well as the external cable, please refer to Terasic website PCIe x4 Cable Adapterand PCIe x4 Gen.2 Cable.Table 4-8 summarizes the PCI Express pin assignments of the signal names relative to the Arria 10 SoC FPGA.PCIe pin connection is showed in Figure 4-7.

Figure 4-6 PCIe External Cable

Figure 4-7 PCI Express Pin Connection

Table 4-8 PCIe Pin Assignments,Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
PCIE_REFCLK_p	PIN_AH31	PCIe reference clock	LVDS
PCIE_TX_p[0]	PIN_AR37	PCIe Transmitter data p0	HSSI DIFFERENTIAL I/O
PCIE_TX_p[1]	PIN_AP39	PCIe Transmitter data p1	HSSI DIFFERENTIAL I/O
PCIE_TX_p[2]	PIN_AN37	PCIe Transmitter data p2	HSSI DIFFERENTIAL I/O
PCIE_TX_p[3]	PIN_AM39	PCIe Transmitter data p3	HSSI DIFFERENTIAL I/O
PCIE_RX_p[0]	PIN_AL33	PCIe Receiver data p0	HSSI DIFFERENTIAL I/O
PCIE_RX_p[1]	PIN_AM35	PCIe Receiver data p1	HSSI DIFFERENTIAL I/O
PCIE_RX_p[2]	PIN_AJ33	PCIe Receiver data p2	HSSI DIFFERENTIAL I/O
PCIE_RX_p[3]	PIN_AK35	PCIe Receiver data p3	HSSI DIFFERENTIAL I/O
PCIE_PERST_n	PIN_AW20	PCIe present,active low	1.8 V
PCIE_WAKE_n	PIN_AL19	PCIe wake	1.8 V

4.6 DDR4

The board supports 1GB of DDR4 SDRAM comprising of two x32bit DDR4 devices on FPGA side. The DDR4 signals are connected to the vertical I/O banks on the bottom edge of the FPGA. The DDR4 devices shipped with this board are running at 1067 MHz, for a total theoretical bandwidth of over 66Gbps. Figure 4-8 shows the connections between the DDR4 and Arria 10 SoC FPGA. Table 4-9 lists the pin assignments of DDR4 and its description with I/O standard.

Figure 4-8 The connection between DDR4 and Arria 10 SoC FPGA

Table 4-9 The pin assignments of DDR4 component and its description with I/O standard

FPGA Pin Number	Signal Name	Description	I/O Standard
PIN_AU7	DDR4B_REFCLK_p	DDR4 A port Reference Clock p	LVDS
PIN_AJ11	DDR4B_A[0]	Address [0]	SSTL-12
PIN_AH12	DDR4B_A[1]	Address [1]	SSTL-12
PIN_AP11	DDR4B_A[2]	Address [2]	SSTL-12
PIN_AN11	DDR4B_A[3]	Address [3]	SSTL-12
PIN_AM10	DDR4B_A[4]	Address [4]	SSTL-12
PIN_AM11	DDR4B_A[5]	Address [5]	SSTL-12
PIN_AP9	DDR4B_A[6]	Address [6]	SSTL-12
PIN_AN9	DDR4B_A[7]	Address [7]	SSTL-12
PIN_AR10	DDR4B_A[8]	Address [8]	SSTL-12
PIN_AP10	DDR4B_A[9]	Address [9]	SSTL-12
PIN_AM9	DDR4B_A[10]	Address [10]	SSTL-12
PIN_AL10	DDR4B_A[11]	Address [11]	SSTL-12
PIN_AV8	DDR4B_A[12]	Address [12]	SSTL-12
PIN_AT8	DDR4B_A[13]	Address [13]	SSTL-12
PIN_AT9	DDR4B_A[14]	Address [14]/WE_n	SSTL-12
PIN_AR7	DDR4B_A[15]	Address [15]/CAS_n	SSTL-12
PIN_AR8	DDR4B_A[16]	Address [16]/RAS_n	SSTL-12
PIN_AU6	DDR4B_BA[0]	Bank Select [0]	SSTL-12
PIN_AP8	DDR4B_BA[1]	Bank Select [1]	SSTL-12
PIN_AN8	DDR4B_BG[0]	Bank Group Select[0]	SSTL-12
PIN_AJ14	DDR4B_BG[1]	Bank Group Select[1]	SSTL-12
PIN_AL13	DDR4B_CK	Clock p0	DIFFERENTIAL 1.2-V SSTL
PIN_AK13	DDR4B_CK_n	Clock n0	DIFFERENTIAL 1.2-V SSTL
PIN_AK10	DDR4B_CKE	Clock Enable pin	SSTL-12
PIN_AE12	DDR4B_DQS[0]	Data Strobe p[0]	DIFFERENTIAL 1.2-V POD
PIN_AL7	DDR4B_DQS[1]	Data Strobe p[1]	DIFFERENTIAL 1.2-V POD
PIN_AR6	DDR4B_DQS[2]	Data Strobe p[2]	DIFFERENTIAL 1.2-V POD
PIN_AT2	DDR4B_DQS[3]	Data Strobe p[3]	DIFFERENTIAL 1.2-V POD
PIN_AF13	DDR4B_DQS_n[0]	Data Strobe n[0]	DIFFERENTIAL 1.2-V POD
PIN_AK8	DDR4B_DQS_n[1]	Data Strobe n[1]	DIFFERENTIAL 1.2-V POD
PIN_AP6	DDR4B_DQS_n[2]	Data Strobe n[2]	DIFFERENTIAL 1.2-V POD
PIN_AT3	DDR4B_DQS_n[3]	Data Strobe n[3]	DIFFERENTIAL 1.2-V POD
PIN_AJ9	DDR4B_DQ[0]	Data [0]	1.2-V POD
PIN_AG11	DDR4B_DQ[1]	Data [1]	1.2-V POD
PIN_AF9	DDR4B_DQ[2]	Data [2]	1.2-V POD
PIN_AG12	DDR4B_DQ[3]	Data [3]	1.2-V POD
PIN_AG9	DDR4B_DQ[4]	Data [4]	1.2-V POD
PIN_AF12	DDR4B_DQ[5]	Data [5]	1.2-V POD
PIN_AJ10	DDR4B_DQ[6]	Data [6]	1.2-V POD
PIN_AG10	DDR4B_DQ[7]	Data [7]	1.2-V POD
PIN_AL9	DDR4B_DQ[8]	Data [8]	1.2-V POD
PIN_AH9	DDR4B_DQ[9]	Data [9]	1.2-V POD
PIN_AK6	DDR4B_DQ[10]	Data [10]	1.2-V POD
PIN_AK7	DDR4B_DQ[11]	Data [11]	1.2-V POD
PIN_AH8	DDR4B_DQ[12]	Data [12]	1.2-V POD
PIN_AH7	DDR4B_DQ[13]	Data [13]	1.2-V POD
PIN_AJ8	DDR4B_DQ[14]	Data [14]	1.2-V POD
PIN_AE11	DDR4B_DQ[15]	Data [15]	1.2-V POD
PIN_AT4	DDR4B_DQ[16]	Data [16]	1.2-V POD
PIN_AM7	DDR4B_DQ[17]	Data [17]	1.2-V POD
PIN_AP5	DDR4B_DQ[18]	Data [18]	1.2-V POD
PIN_AL5	DDR4B_DQ[19]	Data [19]	1.2-V POD
PIN_AM5	DDR4B_DQ[20]	Data [20]	1.2-V POD
PIN_AM6	DDR4B_DQ[21]	Data [21]	1.2-V POD
PIN_AM4	DDR4B_DQ[22]	Data [22]	1.2-V POD
PIN_AR5	DDR4B_DQ[23]	Data [23]	1.2-V POD
PIN_AP1	DDR4B_DQ[24]	Data [24]	1.2-V POD
PIN_AR3	DDR4B_DQ[25]	Data [25]	1.2-V POD
PIN_AN3	DDR4B_DQ[26]	Data [26]	1.2-V POD
PIN_AR1	DDR4B_DQ[27]	Data [27]	1.2-V POD
PIN_AU2	DDR4B_DQ[28]	Data [28]	1.2-V POD
PIN_AP4	DDR4B_DQ[29]	Data [29]	1.2-V POD
PIN_AR2	DDR4B_DQ[30]	Data [30]	1.2-V POD
PIN_AU1	DDR4B_DQ[31]	Data [31]	1.2-V POD
PIN_AF10	DDR4B_DM[0]	DDR3 Data Mask[0]	1.2-V POD
PIN_AL8	DDR4B_DM[1]	DDR3 Data Mask[1]	1.2-V POD
PIN_AN7	DDR4B_DM[2]	DDR3 Data Mask[2]	1.2-V POD
PIN_AN4	DDR4B_DM[3]	DDR3 Data Mask[3]	1.2-V POD
PIN_AJ13	DDR4B_CS_n[0]	Chip Select	SSTL-12
PIN_AH14	DDR4B_RESET_n	Chip Reset	1.2 V
PIN_AL12	DDR4A_ODT[0]	On Die Termination	SSTL-12
PIN_AM12	DDR4A_PAR	Command and Address Parity Input	SSTL-12
PIN_AH11	DDR4A_ALERT_n	Register ALERT_n output	SSTL-12
PIN_AH13	DDR4A_ACT_n	Activation Command Input	SSTL-12
PIN_AW8	DDR4A_RZQ	External reference ball for output drive calibration	1.2 V

The development board also supports one bank of DDR4 SDRAM SO-DIMM on FPGA side. It is wired to support a maximum capacity of 8GB with a 72-bit data bus. Using differential DQS signaling for the DDR4 SDRAM interfaces, it is capable of running at up to 1067MHz memory clock for a maximum theoretical bandwidth up to 132Gbps. Figure 4-9 shows the connections between the DDR4 SDRAM SODIMM and Arria 10 SoC FPGA. The pin assignments for DDR4 SDRAM SO-DIMM are listed in Table 4-10.

Figure 4-9 The connection between the DDR4 SDRAM SO-DIMM and Arria 10 SoC FPGA

Table 4-10 The pin assignments for DDR4 SDRAM SO-DIMM

FPGA Pin Number	Signal Name	Description	I/O Standard
PIN_AB12	DDR4A_REFCLK_p	DDR4 A port Reference Clock p	LVDS
PIN_AC1	DDR4A_A[0]	Address [0]	SSTL-12
PIN_AB1	DDR4A_A[1]	Address [1]	SSTL-12
PIN_AB4	DDR4A_A[2]	Address [2]	SSTL-12
PIN_AA5	DDR4A_A[3]	Address [3]	SSTL-12
PIN_AA3	DDR4A_A[4]	Address [4]	SSTL-12
PIN_AA4	DDR4A_A[5]	Address [5]	SSTL-12
PIN_Y2	DDR4A_A[6]	Address [6]	SSTL-12
PIN_AA2	DDR4A_A[7]	Address [7]	SSTL-12
PIN_AB5	DDR4A_A[8]	Address [8]	SSTL-12
PIN_AB6	DDR4A_A[9]	Address [9]	SSTL-12
PIN_W5	DDR4A_A[10]	Address [10]	SSTL-12
PIN_Y5	DDR4A_A[11]	Address [11]	SSTL-12
PIN_AA9	DDR4A_A[12]	Address [12]	SSTL-12
PIN_AB7	DDR4A_A[13]	Address [13]	SSTL-12
PIN_AA7	DDR4A_A[14]	Address [14]/WE_n	SSTL-12
PIN_AB10	DDR4A_A[15]	Address [15]/CAS_n	SSTL-12
PIN_AB11	DDR4A_A[16]	Address [16]/RAS_n	SSTL-12
PIN_Y7	DDR4A_BA[0]	Bank Select [0]	SSTL-12
PIN_AB9	DDR4A_BA[1]	Bank Select [1]	SSTL-12
PIN_AA10	DDR4A_BG[0]	Bank Group Select[0]	SSTL-12
PIN_AE2	DDR4A_BG[1]	Bank Group Select[1]	SSTL-12
PIN_AD3	DDR4A_CK	Clock p0	DIFFERENTIAL 1.2-V SSTL
PIN_AD4	DDR4A_CK_n	Clock n0	DIFFERENTIAL 1.2-V SSTL
PIN_AC2	DDR4A_CKE	Clock Enable pin	SSTL-12
PIN_AE8	DDR4A_DQS[0]	Data Strobe p[0]	DIFFERENTIAL 1.2-V POD
PIN_AF7	DDR4A_DQS[1]	Data Strobe p[1]	DIFFERENTIAL 1.2-V POD
PIN_AN1	DDR4A_DQS[2]	Data Strobe p[2]	DIFFERENTIAL 1.2-V POD
PIN_AH2	DDR4A_DQS[3]	Data Strobe p[3]	DIFFERENTIAL 1.2-V POD
PIN_P1	DDR4A_DQS[4]	Data Strobe p[4]	DIFFERENTIAL 1.2-V POD
PIN_J3	DDR4A_DQS[5]	Data Strobe p[5]	DIFFERENTIAL 1.2-V POD
PIN_R5	DDR4A_DQS[6]	Data Strobe p[6]	DIFFERENTIAL 1.2-V POD
PIN_V9	DDR4A_DQS[7]	Data Strobe p[7]	DIFFERENTIAL 1.2-V POD
PIN_V2	DDR4A_DQS[8]	Data Strobe p[8]	DIFFERENTIAL 1.2-V POD
PIN_AD8	DDR4A_DQS_n[0]	Data Strobe n[0]	DIFFERENTIAL 1.2-V POD
PIN_AE7	DDR4A_DQS_n[1]	Data Strobe n[1]	DIFFERENTIAL 1.2-V POD
PIN_AN2	DDR4A_DQS_n[2]	Data Strobe n[2]	DIFFERENTIAL 1.2-V POD
PIN_AH3	DDR4A_DQS_n[3]	Data Strobe n[3]	DIFFERENTIAL 1.2-V POD
PIN_R1	DDR4A_DQS_n[4]	Data Strobe n[4]	DIFFERENTIAL 1.2-V POD
PIN_K3	DDR4A_DQS_n[5]	Data Strobe n[5]	DIFFERENTIAL 1.2-V POD
PIN_R6	DDR4A_DQS_n[6]	Data Strobe n[6]	DIFFERENTIAL 1.2-V POD
PIN_W9	DDR4A_DQS_n[7]	Data Strobe n[7]	DIFFERENTIAL 1.2-V POD
PIN_V3	DDR4A_DQS_n[8]	Data Strobe n[8]	DIFFERENTIAL 1.2-V POD
PIN_AC11	DDR4A_DQ[0]	Data [0]	1.2-V POD
PIN_AD10	DDR4A_DQ[1]	Data [1]	1.2-V POD
PIN_AC9	DDR4A_DQ[2]	Data [2]	1.2-V POD
PIN_AG7	DDR4A_DQ[3]	Data [3]	1.2-V POD
PIN_AD13	DDR4A_DQ[4]	Data [4]	1.2-V POD
PIN_AD11	DDR4A_DQ[5]	Data [5]	1.2-V POD
PIN_AC8	DDR4A_DQ[6]	Data [6]	1.2-V POD
PIN_AF8	DDR4A_DQ[7]	Data [7]	1.2-V POD
PIN_AE6	DDR4A_DQ[8]	Data [8]	1.2-V POD
PIN_AJ6	DDR4A_DQ[9]	Data [9]	1.2-V POD
PIN_AG6	DDR4A_DQ[10]	Data [10]	1.2-V POD
PIN_AD6	DDR4A_DQ[11]	Data [11]	1.2-V POD
PIN_AG5	DDR4A_DQ[12]	Data [12]	1.2-V POD
PIN_AK5	DDR4A_DQ[13]	Data [13]	1.2-V POD
PIN_AC7	DDR4A_DQ[14]	Data [14]	1.2-V POD
PIN_AH6	DDR4A_DQ[15]	Data [15]	1.2-V POD
PIN_AK1	DDR4A_DQ[16]	Data [16]	1.2-V POD
PIN_AL4	DDR4A_DQ[17]	Data [17]	1.2-V POD
PIN_AJ4	DDR4A_DQ[18]	Data [18]	1.2-V POD
PIN_AM1	DDR4A_DQ[19]	Data [19]	1.2-V POD
PIN_AK3	DDR4A_DQ[20]	Data [20]	1.2-V POD
PIN_AL2	DDR4A_DQ[21]	Data [21]	1.2-V POD
PIN_AJ3	DDR4A_DQ[22]	Data [22]	1.2-V POD
PIN_AM2	DDR4A_DQ[23]	Data [23]	1.2-V POD
PIN_AF2	DDR4A_DQ[24]	Data [24]	1.2-V POD
PIN_AH1	DDR4A_DQ[25]	Data [25]	1.2-V POD
PIN_AG4	DDR4A_DQ[26]	Data [26]	1.2-V POD
PIN_AE5	DDR4A_DQ[27]	Data [27]	1.2-V POD
PIN_AF3	DDR4A_DQ[28]	Data [28]	1.2-V POD
PIN_AH4	DDR4A_DQ[29]	Data [29]	1.2-V POD
PIN_AG1	DDR4A_DQ[30]	Data [30]	1.2-V POD
PIN_AF4	DDR4A_DQ[31]	Data [31]	1.2-V POD
PIN_K1	DDR4A_DQ[32]	Data [32]	1.2-V POD
PIN_P4	DDR4A_DQ[33]	Data [33]	1.2-V POD
PIN_N2	DDR4A_DQ[34]	Data [34]	1.2-V POD
PIN_K2	DDR4A_DQ[35]	Data [35]	1.2-V POD
PIN_M2	DDR4A_DQ[36]	Data [36]	1.2-V POD
PIN_P3	DDR4A_DQ[37]	Data [37]	1.2-V POD
PIN_N1	DDR4A_DQ[38]	Data [38]	1.2-V POD
PIN_J1	DDR4A_DQ[39]	Data [39]	1.2-V POD
PIN_N3	DDR4A_DQ[40]	Data [40]	1.2-V POD
PIN_P5	DDR4A_DQ[41]	Data [41]	1.2-V POD
PIN_M5	DDR4A_DQ[42]	Data [42]	1.2-V POD
PIN_R2	DDR4A_DQ[43]	Data [43]	1.2-V POD
PIN_N4	DDR4A_DQ[44]	Data [44]	1.2-V POD
PIN_P6	DDR4A_DQ[45]	Data [45]	1.2-V POD
PIN_L4	DDR4A_DQ[46]	Data [46]	1.2-V POD
PIN_R3	DDR4A_DQ[47]	Data [47]	1.2-V POD
PIN_V6	DDR4A_DQ[48]	Data [48]	1.2-V POD
PIN_T7	DDR4A_DQ[49]	Data [49]	1.2-V POD
PIN_U5	DDR4A_DQ[50]	Data [50]	1.2-V POD
PIN_U7	DDR4A_DQ[51]	Data [51]	1.2-V POD
PIN_T4	DDR4A_DQ[52]	Data [52]	1.2-V POD
PIN_W6	DDR4A_DQ[53]	Data [53]	1.2-V POD
PIN_T3	DDR4A_DQ[54]	Data [54]	1.2-V POD
PIN_U6	DDR4A_DQ[55]	Data [55]	1.2-V POD
PIN_W8	DDR4A_DQ[56]	Data [56]	1.2-V POD
PIN_Y12	DDR4A_DQ[57]	Data [57]	1.2-V POD
PIN_Y11	DDR4A_DQ[58]	Data [58]	1.2-V POD
PIN_W10	DDR4A_DQ[59]	Data [59]	1.2-V POD
PIN_Y13	DDR4A_DQ[60]	Data [60]	1.2-V POD
PIN_Y8	DDR4A_DQ[61]	Data [61]	1.2-V POD
PIN_Y10	DDR4A_DQ[62]	Data [62]	1.2-V POD
PIN_W11	DDR4A_DQ[63]	Data [63]	1.2-V POD
PIN_V1	DDR4A_DQ[64]	Data [64]	1.2-V POD
PIN_Y1	DDR4A_DQ[65]	Data [65]	1.2-V POD
PIN_W3	DDR4A_DQ[66]	Data [66]	1.2-V POD
PIN_W1	DDR4A_DQ[67]	Data [67]	1.2-V POD
PIN_Y3	DDR4A_DQ[68]	Data [68]	1.2-V POD
PIN_W4	DDR4A_DQ[69]	Data [69]	1.2-V POD
PIN_U1	DDR4A_DQ[70]	Data [70]	1.2-V POD
PIN_U2	DDR4A_DQ[71]	Data [71]	1.2-V POD
PIN_AD9	DDR4A_DBI_n[0]	Data Bus Inversion [0]	1.2-V POD
PIN_AJ5	DDR4A_DBI_n[1]	Data Bus Inversion [1]	1.2-V POD
PIN_AK2	DDR4A_DBI_n[2]	Data Bus Inversion [2]	1.2-V POD
PIN_AG2	DDR4A_DBI_n[3]	Data Bus Inversion [3]	1.2-V POD
PIN_L2	DDR4A_DBI_n[4]	Data Bus Inversion [4]	1.2-V POD
PIN_L3	DDR4A_DBI_n[5]	Data Bus Inversion [5]	1.2-V POD
PIN_U4	DDR4A_DBI_n[6]	Data Bus Inversion [6]	1.2-V POD
PIN_V8	DDR4A_DBI_n[7]	Data Bus Inversion [7]	1.2-V POD
PIN_V4	DDR4A_DBI_n[8]	Data Bus Inversion [8]	1.2-V POD
PIN_AE1	DDR4A_CS_n	Chip Select	SSTL-12
PIN_AE3	DDR4A_RESET_n	Chip Reset	1.2 V
PIN_AC3	DDR4A_ODT	On Die Termination	SSTL-12
PIN_AC6	DDR4A_PAR	Command and Address Parity Input	SSTL-12
PIN_AC12	DDR4A_ALERT_n	Register ALERT_n output	SSTL-12
PIN_AD1	DDR4A_ACT_n	Activation Command Input	SSTL-12
PIN_T5	DDR4A_EVENT_n	Chip Temperature Event	1.2 V
PIN_AD5	DDR4A_AC_R[0]	Reserved for QDRII+/RLDRAM3	SSTL-12
PIN_Y6	DDR4A_AC_R[1]	Reserved for QDRII+/RLDRAM3	SSTL-12
PIN_AC4	DDR4A_C[0]	Reserved for QDRII+/RLDRAM3	SSTL-12
PIN_AB2	DDR4A_C[1]	Reserved for QDRII+/RLDRAM3	SSTL-12
PIN_AA8	DDR4A_RZQ	External reference ball for output drive calibration	1.2 V

The DDR4 SDRAM SO-DIMM socket can support many kinds of memory devices, such as standard DDR4 SO-DIMM with ECC up to 8GB at 1067MHz, Terasic QDRII+ module with DDR4 SO-DIMM interface, Terasic RLDRAM3 module with DDR4 SO-DIMM interface, as shown in Figure 4-10, Figure 4-11 and Figure 4-12.

  
Figure 4-10 Standard DDR4 SO-DIMM with ECC                Figure 4-11 Terasic QDRII+ module with DDR4 SO-DIMM interface


Figure 4-12 Terasic RLDRAM3 module with DDR4 SO-DIMM interface

4.7 HDMI TX

4.8 HDMI RX

4.9 Gigabit Ethernet

The development board supports one RJ45 10/100/1000 base-T Ethernet using Marvell 88E1111. SGMII AC coupling interface is used between PHY and FPGA transceiver.The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Arria 10 SoC FPGA can communicate with the LVDS interfaces at up to 1.6 Gbps, which is faster than 1.25 Gbps for SGMII. The MAC function must be provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.1-V power rails and requires a 25MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 with internal magnetics for driving copper lines with Ethernet traffic.Figure 4-2 shows the SGMII interface between the FPGA and Marvell 88E1111 PHY. Table 4-2 lists the Ethernet PHY interface pin assignments.

Figure 4-2 SGMII Interface between FPGA and Marvell 88E1111 PHY

Table 4-2 Ethernet PHY Pin Assignments, Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
ETH_TX_p	PIN_AP19	SGMII TX data	LVDS
ETH_RX_p	PIN_AM20	SGMII RX data	LVDS
ETH_INT_n	PIN_AU19	Management bus interrupt	1.8V
ETH_MDC	PIN_AT19	Management bus control	1.8V
ETH_MDIO	PIN_AJ20	Management bus data	1.8V
ETH_RST_n	PIN_AK20	Device reset	1.8V

4.10 FMC Connector

The FPGA Mezzanine Card (FMC) interface provides a mechanism to extend the peripheral-set of an FPGA host board by means of add-on daughter cards, which can address today’s high speed signaling requirements as well as low-speed device interface support.The FMC interfaces support JTAG,clock outputs and inputs,high-speed serial I/O (transceivers),and single-ended or differential signaling.
There is one FMC connector on the DE10-Advanced board,it is a High Pin Count (HPC) size of connector,The HPC connector on DE10-Advanced board can provides 172 user-define,single-ended signals (include clock signals) and 10 serial transceiver pairs.Figure 4-10 is the FMC connector on DE10-Advanced board

Figure 4-10 FMC connector on DE10-Advanced board

Table 4-11 FMC Connector Pin Assignments, Signal Names and Functions

Signal Name	FPGA Pin Number	Description	I/O Standard
FMC_CLK2_BIDIR_p	PIN_AW18	FMC bidirection Clock signal	1.8 V
FMC_CLK2_BIDIR_n	PIN_AV17	FMC bidirection Clock signal	1.8 V
FMC_CLK3_BIDIR_p	PIN_C1	FMC bidirection Clock signal	1.8 V
FMC_CLK3_BIDIR_n	PIN_D1	FMC bidirection Clock signal	1.8 V
FMC_CLK_M2C_p[0]	PIN_K5	Clock input 0	1.8 V
FMC_CLK_M2C_p[1]	PIN_AW14	Clock input 1	1.8 V
FMC_CLK_M2C_n[0]	PIN_L5	Clock input 0	1.8 V
FMC_CLK_M2C_n[1]	PIN_AW15	Clock input 1	1.8 V
FMC_HA_p[0]	PIN_K12	FMC data bus	1.8 V
FMC_HA_p[1]	PIN_M12	FMC data bus	1.8 V
FMC_HA_p[2]	PIN_D10	FMC data bus	1.8 V
FMC_HA_p[3]	PIN_E12	FMC data bus	1.8 V
FMC_HA_p[4]	PIN_H13	FMC data bus	1.8 V
FMC_HA_p[5]	PIN_J11	FMC data bus	1.8 V
FMC_HA_p[6]	PIN_N13	FMC data bus	1.8 V
FMC_HA_p[7]	PIN_L13	FMC data bus	1.8 V
FMC_HA_p[8]	PIN_J14	FMC data bus	1.8 V
FMC_HA_p[9]	PIN_F13	FMC data bus	1.8 V
FMC_HA_p[10]	PIN_D13	FMC data bus	1.8 V
FMC_HA_p[11]	PIN_G14	FMC data bus	1.8 V
FMC_HA_p[12]	PIN_A10	FMC data bus	1.8 V
FMC_HA_p[13]	PIN_G12	FMC data bus	1.8 V
FMC_HA_p[14]	PIN_A12	FMC data bus	1.8 V
FMC_HA_p[15]	PIN_A7	FMC data bus	1.8 V
FMC_HA_p[16]	PIN_A9	FMC data bus	1.8 V
FMC_HA_p[17]	PIN_C12	FMC data bus	1.8 V
FMC_HA_p[18]	PIN_B11	FMC data bus	1.8 V
FMC_HA_p[19]	PIN_M7	FMC data bus	1.8 V
FMC_HA_p[20]	PIN_F10	FMC data bus	1.8 V
FMC_HA_p[21]	PIN_C9	FMC data bus	1.8 V
FMC_HA_p[22]	PIN_C8	FMC data bus	1.8 V
FMC_HA_p[23]	PIN_G11	FMC data bus	1.8 V
FMC_HA_n[0]	PIN_L12	FMC data bus	1.8 V
FMC_HA_n[1]	PIN_N12	FMC data bus	1.8 V
FMC_HA_n[2]	PIN_E10	FMC data bus	1.8 V
FMC_HA_n[3]	PIN_F12	FMC data bus	1.8 V
FMC_HA_n[4]	PIN_J13	FMC data bus	1.8 V
FMC_HA_n[5]	PIN_K11	FMC data bus	1.8 V
FMC_HA_n[6]	PIN_P13	FMC data bus	1.8 V
FMC_HA_n[7]	PIN_L14	FMC data bus	1.8 V
FMC_HA_n[8]	PIN_K13	FMC data bus	1.8 V
FMC_HA_n[9]	PIN_F14	FMC data bus	1.8 V
FMC_HA_n[10]	PIN_E13	FMC data bus	1.8 V
FMC_HA_n[11]	PIN_H14	FMC data bus	1.8 V
FMC_HA_n[12]	PIN_B10	FMC data bus	1.8 V
FMC_HA_n[13]	PIN_H12	FMC data bus	1.8 V
FMC_HA_n[14]	PIN_B12	FMC data bus	1.8 V
FMC_HA_n[15]	PIN_A8	FMC data bus	1.8 V
FMC_HA_n[16]	PIN_B9	FMC data bus	1.8 V
FMC_HA_n[17]	PIN_C13	FMC data bus	1.8 V
FMC_HA_n[18]	PIN_C11	FMC data bus	1.8 V
FMC_HA_n[19]	PIN_N7	FMC data bus	1.8 V
FMC_HA_n[20]	PIN_G10	FMC data bus	1.8 V
FMC_HA_n[21]	PIN_D9	FMC data bus	1.8 V
FMC_HA_n[22]	PIN_D8	FMC data bus	1.8 V
FMC_HA_n[23]	PIN_H11	FMC data bus	1.8 V
FMC_HB_p[0]	PIN_E1	FMC data bus	1.8 V
FMC_HB_p[1]	PIN_G4	FMC data bus	1.8 V
FMC_HB_p[2]	PIN_N8	FMC data bus	1.8 V
FMC_HB_p[3]	PIN_J4	FMC data bus	1.8 V
FMC_HB_p[4]	PIN_H2	FMC data bus	1.8 V
FMC_HB_p[5]	PIN_G5	FMC data bus	1.8 V
FMC_HB_p[6]	PIN_D3	FMC data bus	1.8 V
FMC_HB_p[7]	PIN_A2	FMC data bus	1.8 V
FMC_HB_p[8]	PIN_B1	FMC data bus	1.8 V
FMC_HB_p[9]	PIN_AT13	FMC data bus	1.8 V
FMC_HB_p[10]	PIN_AM17	FMC data bus	1.8 V
FMC_HB_p[11]	PIN_AJ16	FMC data bus	1.8 V
FMC_HB_p[12]	PIN_AW13	FMC data bus	1.8 V
FMC_HB_p[13]	PIN_AV14	FMC data bus	1.8 V
FMC_HB_p[14]	PIN_AP14	FMC data bus	1.8 V
FMC_HB_p[15]	PIN_AK16	FMC data bus	1.8 V
FMC_HB_p[16]	PIN_AU16	FMC data bus	1.8 V
FMC_HB_p[17]	PIN_AT17	FMC data bus	1.8 V
FMC_HB_p[18]	PIN_AM15	FMC data bus	1.8 V
FMC_HB_p[19]	PIN_AR15	FMC data bus	1.8 V
FMC_HB_p[20]	PIN_AP16	FMC data bus	1.8 V
FMC_HB_p[21]	PIN_AV18	FMC data bus	1.8 V
FMC_HB_n[0]	PIN_E2	FMC data bus	1.8 V
FMC_HB_n[1]	PIN_H4	FMC data bus	1.8 V
FMC_HB_n[2]	PIN_P8	FMC data bus	1.8 V
FMC_HB_n[3]	PIN_J5	FMC data bus	1.8 V
FMC_HB_n[4]	PIN_H3	FMC data bus	1.8 V
FMC_HB_n[5]	PIN_H6	FMC data bus	1.8 V
FMC_HB_n[6]	PIN_E3	FMC data bus	1.8 V
FMC_HB_n[7]	PIN_B2	FMC data bus	1.8 V
FMC_HB_n[8]	PIN_C2	FMC data bus	1.8 V
FMC_HB_n[9]	PIN_AT14	FMC data bus	1.8 V
FMC_HB_n[10]	PIN_AL17	FMC data bus	1.8 V
FMC_HB_n[11]	PIN_AH16	FMC data bus	1.8 V
FMC_HB_n[12]	PIN_AV13	FMC data bus	1.8 V
FMC_HB_n[13]	PIN_AU14	FMC data bus	1.8 V
FMC_HB_n[14]	PIN_AP15	FMC data bus	1.8 V
FMC_HB_n[15]	PIN_AK17	FMC data bus	1.8 V
FMC_HB_n[16]	PIN_AU17	FMC data bus	1.8 V
FMC_HB_n[17]	PIN_AT18	FMC data bus	1.8 V
FMC_HB_n[18]	PIN_AM16	FMC data bus	1.8 V
FMC_HB_n[19]	PIN_AR16	FMC data bus	1.8 V
FMC_HB_n[20]	PIN_AN16	FMC data bus	1.8 V
FMC_HB_n[21]	PIN_AV19	FMC data bus	1.8 V
FMC_LA_p[0]	PIN_A3	FMC data bus	1.8 V
FMC_LA_p[1]	PIN_B4	FMC data bus	1.8 V
FMC_LA_p[2]	PIN_T9	FMC data bus	1.8 V
FMC_LA_p[3]	PIN_M10	FMC data bus	1.8 V
FMC_LA_p[4]	PIN_U9	FMC data bus	1.8 V
FMC_LA_p[5]	PIN_J10	FMC data bus	1.8 V
FMC_LA_p[6]	PIN_H8	FMC data bus	1.8 V
FMC_LA_p[7]	PIN_L9	FMC data bus	1.8 V
FMC_LA_p[8]	PIN_M9	FMC data bus	1.8 V
FMC_LA_p[9]	PIN_G6	FMC data bus	1.8 V
FMC_LA_p[10]	PIN_E8	FMC data bus	1.8 V
FMC_LA_p[11]	PIN_B6	FMC data bus	1.8 V
FMC_LA_p[12]	PIN_A5	FMC data bus	1.8 V
FMC_LA_p[13]	PIN_D5	FMC data bus	1.8 V
FMC_LA_p[14]	PIN_B7	FMC data bus	1.8 V
FMC_LA_p[15]	PIN_E6	FMC data bus	1.8 V
FMC_LA_p[16]	PIN_E5	FMC data bus	1.8 V
FMC_LA_p[17]	PIN_F9	FMC data bus	1.8 V
FMC_LA_p[18]	PIN_K8	FMC data bus	1.8 V
FMC_LA_p[19]	PIN_R8	FMC data bus	1.8 V
FMC_LA_p[20]	PIN_F7	FMC data bus	1.8 V
FMC_LA_p[21]	PIN_C4	FMC data bus	1.8 V
FMC_LA_p[22]	PIN_U11	FMC data bus	1.8 V
FMC_LA_p[23]	PIN_V11	FMC data bus	1.8 V
FMC_LA_p[24]	PIN_R11	FMC data bus	1.8 V
FMC_LA_p[25]	PIN_F2	FMC data bus	1.8 V
FMC_LA_p[26]	PIN_R7	FMC data bus	1.8 V
FMC_LA_p[27]	PIN_T12	FMC data bus	1.8 V
FMC_LA_p[28]	PIN_J6	FMC data bus	1.8 V
FMC_LA_p[29]	PIN_G1	FMC data bus	1.8 V
FMC_LA_p[30]	PIN_K7	FMC data bus	1.8 V
FMC_LA_p[31]	PIN_P10	FMC data bus	1.8 V
FMC_LA_p[32]	PIN_M6	FMC data bus	1.8 V
FMC_LA_p[33]	PIN_N11	FMC data bus	1.8 V
FMC_LA_n[0]	PIN_A4	FMC data bus	1.8 V
FMC_LA_n[1]	PIN_C3	FMC data bus	1.8 V
FMC_LA_n[2]	PIN_T10	FMC data bus	1.8 V
FMC_LA_n[3]	PIN_M11	FMC data bus	1.8 V
FMC_LA_n[4]	PIN_U10	FMC data bus	1.8 V
FMC_LA_n[5]	PIN_K10	FMC data bus	1.8 V
FMC_LA_n[6]	PIN_J8	FMC data bus	1.8 V
FMC_LA_n[7]	PIN_L10	FMC data bus	1.8 V
FMC_LA_n[8]	PIN_N9	FMC data bus	1.8 V
FMC_LA_n[9]	PIN_H7	FMC data bus	1.8 V
FMC_LA_n[10]	PIN_F8	FMC data bus	1.8 V
FMC_LA_n[11]	PIN_C6	FMC data bus	1.8 V
FMC_LA_n[12]	PIN_B5	FMC data bus	1.8 V
FMC_LA_n[13]	PIN_D6	FMC data bus	1.8 V
FMC_LA_n[14]	PIN_C7	FMC data bus	1.8 V
FMC_LA_n[15]	PIN_E7	FMC data bus	1.8 V
FMC_LA_n[16]	PIN_F5	FMC data bus	1.8 V
FMC_LA_n[17]	PIN_G9	FMC data bus	1.8 V
FMC_LA_n[18]	PIN_L8	FMC data bus	1.8 V
FMC_LA_n[19]	PIN_P9	FMC data bus	1.8 V
FMC_LA_n[20]	PIN_G7	FMC data bus	1.8 V
FMC_LA_n[21]	PIN_D4	FMC data bus	1.8 V
FMC_LA_n[22]	PIN_U12	FMC data bus	1.8 V
FMC_LA_n[23]	PIN_V12	FMC data bus	1.8 V
FMC_LA_n[24]	PIN_R12	FMC data bus	1.8 V
FMC_LA_n[25]	PIN_G2	FMC data bus	1.8 V
FMC_LA_n[26]	PIN_T8	FMC data bus	1.8 V
FMC_LA_n[27]	PIN_T13	FMC data bus	1.8 V
FMC_LA_n[28]	PIN_K6	FMC data bus	1.8 V
FMC_LA_n[29]	PIN_H1	FMC data bus	1.8 V
FMC_LA_n[30]	PIN_L7	FMC data bus	1.8 V
FMC_LA_n[31]	PIN_R10	FMC data bus	1.8 V
FMC_LA_n[32]	PIN_N6	FMC data bus	1.8 V
FMC_LA_n[33]	PIN_P11	FMC data bus	1.8 V
FMC_GBTCLK_M2C_p[0]	PIN_P31	LVDS input from the installed FMC card to dedicated reference clock inputs	LVDS
FMC_GBTCLK_M2C_p[1]	PIN_K31	LVDS input from the installed FMC card to dedicated reference clock inputs	LVDS
FMC_REFCLK_p	PIN_T31	Reference Clock	LVDS
FMC_DP_C2M_p[0]	PIN_M39	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[1]	PIN_L37	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[2]	PIN_K39	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[3]	PIN_J37	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[4]	PIN_H39	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[5]	PIN_G37	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[6]	PIN_F39	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[7]	PIN_E37	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[8]	PIN_D39	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_C2M_p[9]	PIN_C37	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[0]	PIN_P35	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[1]	PIN_R33	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[2]	PIN_M35	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[3]	PIN_N33	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[4]	PIN_K35	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[5]	PIN_L33	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[6]	PIN_H35	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[7]	PIN_J33	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[8]	PIN_F35	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_DP_M2C_p[9]	PIN_G33	Transmit channel	HSSI DIFFERENTIAL I/O
FMC_GA[0]	PIN_E11	FMC geographical address 0	1.8 V
FMC_GA[1]	PIN_AL18	FMC geographical address 1	1.8 V
FMC_SCL	PIN_J9	Management serial clock line	1.8 V
FMC_SDA	PIN_F4	Management serial data line	1.8 V

4.11 Temperature Sensor,Fan Control and Power Monitor

The FPGA board is equipped with a temperature sensor, TMP441AIDCNT, which provides temperature sensing.This functions is accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Arria 10 SoC device. The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two-wire SMBus, which is connected to the Arria 10 SoC FPGA. In addition, the 7-bit POR slave address for this sensor is set to‘0011100b'.

A 3-pin +12V fan located on J22 of the FPGA board is intended to reduce the temperature of the FPGA.The board is equipped with a Fan-Speed regulator and monitor MAX6650 with an I2C/SMBus interfaces,Users regulate and monitor the speed of fan depending on the measured system temperature.

The DE10-Advanced has implemented a power monitor chip to monitor the board input power voltage and current.Figure 4-10 shows the connection between the power monitor chip and the Arria 10 SoC FPGA.The power monitor chip monitors both shunt voltage drops and board input power voltage allows user to monitor the total board power consumption. Programmable calibration value,conversion times,and averaging,combined with an internal multiplier,enable direct readouts of current in amperes and power in watts.Note that,the temperature sensor,fan control and power monitor share the same I2C/SMBUS.

Figure 4-10 Connections between the temperature sensor/fan control/power monitor and the Arria 10 SoC FPGA

Table 4-12 Temperature Sensor and Fan Speed Control Pin Assignments,Schematic Signal Names and Functions

Schematic Signal Name	Description	I/O Standard	Arria 10 SoC Pin Number
TEMPDIODEp	Positive pin of temperature diode in Arria 10	--	--
TEMPDIODEn	Negative pin of temperature diode in Arria 10	--	--
FPGA_I2C_SCL	SMBus clock	1.8V	M1
FPGA_I2C_SDA	SMBus data	1.8V	M4
FAN_ALERT	Active-low ALERT input	1.8V	E25

4.12 Gyroscope, Accelerometer and Magnetometer

The VEEK-MT2 is equipped with a Motion-Tracking device named MPU-9250. The MPU-9250 is a 9-axis Motion-Tracking device that combines a 3-axis gyroscope, 3-axis accelerometer and 3-axis magnetometer. Detail features of these sensors are listed below.

Gyroscope

The MPU-9250 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a wide range of cut-off frequencies.

Accelerometer

The MPU-9250‟s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The MPU-9250‟s architecture reduces the accelerometers‟ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers‟ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.

Magnetometer

The 3-axis magnetometer uses highly sensitive Hall sensor technology. The magnetometer portion of the IC incorporates magnetic sensors for detecting terrestrial magnetism in the X-, Y-, and Z- Axes, a sensor driving circuit, a signal amplifier chain, and an arithmetic circuit for processing the signal from each sensor. Each ADC has a 16-bit resolution and a full scale range of ±4800 μT. Communication with all registers of the device is performed using either I2C at 400kHz or SPI at 1MHz. For applications requiring faster communications, the sensor and interrupt registers may be read using SPI at 20MHz. For more detailed information of better using this chip, please refer to its datasheet which is available on manufacturer‟s website or under the /datasheet folder of the system CD. Table 4-13 gives the pin assignment information of the LCD touch panel. For more detailed information of better using this chip, please refer to its datasheet which is available on manufacturer‟s website or under the /datasheet folder of the system CD.

Table 4-13 Pin names and descriptions of the MPU-9250

Signal Name	FPGA Pin Number	Description	I/O Standard
MPU_INT	PIN_E26	Interrupt digital output	1.8V

4.13 User Interface (LED/7-SEG/Button/Switch)

The board has two push-buttons connected to the FPGA, as shown in Figure 4-11. Connections between the push-buttons and the Arria 10 SoC FPGA. The two push-buttons named KEY0 and KEY1 are connected directly to the Arria 10 SoC FPGA. Table 4-15 list the pin assignment of user push-buttons.

Figure 4-11 Connections between the push-buttons and the Arria 10 SoC FPGA

Table 4-15 Pin Assignment of Push-buttons

Signal Name	FPGA Pin Number	Description	I/O Standard
KEY[0]	PIN_A24	Push-button[0]	1.8 V
KEY[1]	PIN_A25	Push-button[1]	1.8 V

There are two slide switches connected to the FPGA, as shown in Figure 4-12. These switches are not debounced and to be used as level-sensitive data inputs to a circuit. Each switch is connected directly and individually to the FPGA. When the switch is set to the DOWN position (towards the edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic level is generated to the FPGA. Table 4-16 list the pin assignment of switches.

Figure 4-12 Connections between the switches and the Arria 10 SoC FPGA

Table 4-16 Pin Assignment of Switches

Signal Name	FPGA Pin Number	Description	I/O Standard
SW[0]	PIN_B25	Slide Switch[0]	1.8 V
SW[1]	PIN_B26	Slide Switch[1]	1.8 V

There are also two user-controllable LEDs connected to the FPGA. Each LED is driven directly and individually by the Arria 10 SoC FPGA; driving its associated pin to a high logic level or low level to turn the LED on or off, respectively. Figure 4-13 shows the connections between LEDs and Arria 10 SoC FPGA. Table 4-17 list the pin assignment of LEDs.

Figure 4-13 Connections between the LEDs and the Arria 10 SoC FPGA

Table 4-17 Pin Assignment of LEDs

Signal Name	FPGA Pin Number	Description	I/O Standard
LEDG[0]	PIN_C26	LED [0]	1.8 V
LEDG[1]	PIN_B24	LED [1]	1.8 V

The DE10-Advanced board has two 7-segment displays. These displays are paired to display numbers in various sizes. Figure 4-14 shows the connection of seven segments (common anode) to pins on Arria 10 SoC FPGA. The segment can be turned on or off by applying a low logic level or high logic level from the FPGA, respectively. Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure 4-14. Table 4-18 shows the pin assignment of FPGA to the 7-segment displays.

Figure 4-14 Connections between the 7-segment and the Arria 10 SoC FPGA

Table 4-18 Pin Assignment of 7-segment

Signal Name	FPGA Pin Number	Description	I/O Standard
HEX0[0]	PIN_AT32	Seven Segment Digit 0[0]	1.8V
HEX0[1]	PIN_AR32	Seven Segment Digit 0[1]	1.8V
HEX0[2]	PIN_AU32	Seven Segment Digit 0[2]	1.8V
HEX0[3]	PIN_AU30	Seven Segment Digit 0[3]	1.8V
HEX0[4]	PIN_AT30	Seven Segment Digit 0[4]	1.8V
HEX0[5]	PIN_AU29	Seven Segment Digit 0[5]	1.8V
HEX0[6]	PIN_AV29	Seven Segment Digit 0[6]	1.8V
HEX1[0]	PIN_AT28	Seven Segment Digit 1[0]	1.8V
HEX1[1]	PIN_AT29	Seven Segment Digit 1[1]	1.8V
HEX1[2]	PIN_AR30	Seven Segment Digit 1[2]	1.8V
HEX1[3]	PIN_AM27	Seven Segment Digit 1[3]	1.8V
HEX1[4]	PIN_AL27	Seven Segment Digit 1[4]	1.8V
HEX1[5]	PIN_AK27	Seven Segment Digit 1[5]	1.8V
HEX1[6]	PIN_AM26	Seven Segment Digit 1[6]	1.8V

Chapter 5 HPS Fabric Component

5.1 User Push-buttons and LEDs

5.2 Gigabit Ethernet

5.3 UART to USB

5.4 Micro SD Card Socket

5.5 USB OTG

Chapter 6 System Clocks

Chapter 7 Power and Reset

7.1 Power Supply

7.2 Power Tree

7.3 Reset

7.3.1 HPS Reset

7.3.2 PCIe Reset

7.3.3 MAX V Reset

7.3.4 HPS USB Reset