DE10-Agilex Rev.A to Rev.B Revision List

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Rev. A to Rev. B

  1. Add Force External Power Switch (SW1) to Enable/Disable External Power Requirement when connected to the HOST PC.
    De ag sw1.jpg
  2. Add System MAX10 Jtag bypass switch (SW9) for increase JTAG sacn speed.
    De ag sw9.jpg
  3. Modify the direction of the external power connector.
    De ag ex pwr.jpg
  4. Remove DDR4 Clock Source Switch (SW5) and change the DDR4 source clock oscillator (Y2) from dual clock OSC (166.667/300.0MHz) to 33.333Mhz OSC.
    De ag ddr4 clock osc.jpg
  5. Move the user switch and key from the front of the board to the back.
    De ag user switch.jpg
  6. Modify the reference clock source(Y1) of the SI5340 clock generator(U13) to TCXO to increase the quality of the QSFPDD reference clock.
    De ag si5340 ref.jpg
  7. Improve the core power chip(U15, VCC_CORE) from LT4680(rev.A) to LT4700(rev.B) , the power can be improve from 60A to 100A
  8. Rev.B board add a 30.72Mhz OCXO(U161) but it is not installed, reserved for CPRI application.
    De ag ocxo.jpg
  9. Add external power connection detection I/O(EXP_EN) to FPGA.
    De ag exp en.jpg
  10. Pin Assignment change.
Net Name Rev.A Pin Assignment Rev.B Pin Assignment
PCIE_SMBCLK F59 G50
PCIE_CLKREQ_n J58 F55
PCIE_WAKE_n G58 J50
DDR4B_SDA H57 B19
GPIO_CLK0 CU24 DA22
GPIO_P0 DA22 CY21
INFO_SPI_MISO CY21 CU26
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