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Revision as of 10:40, 4 December 2019 (view source) Admin (Talk | contribs) (→1.2 Key Features) ← Older edit		Revision as of 10:46, 4 December 2019 (view source) Admin (Talk | contribs) (→1.2 Key Features) Newer edit →
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	*'''FPGA Fabric'''		*'''FPGA Fabric'''
		+	**1024Mbit QSPI Flash (EPCQL1024 Compliant)
		+	**2 independent DDR4 banks with ECC.
		+	***Each 16GB Dual Rank DDR4-2666.
		+	***One bank is shared with FPGA and HPS
		+	**FMC (Vita57.1) connector with 10 transceivers
		+	**FMC+(Vita57.4) connector with 24 transceivers

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Revision as of 10:46, 4 December 2019

This chapter provides an overview of the Apollo S10 Development Board and installation guide.

1.1 General Description

待寫

1.2 Key Features

• FPGA Device
  • Intel Stratix ® 10 SoC FPGA : 1SX280HU2F50
    • 2,800K logic elements (LEs)
    • 229 Mbits embedded memory(M20K)
    • 96 transceivers (up to 28.3Gbps)
    • 11,520 18-bit x 19-bit multipliers
    • 5,760 Variable-precision DSP blocks

• FPGA Configuration
  • On-Board USB Blaster II for FPGA programming and Debug
  • AS Mode configuration from QSPI Flash

• FPGA Fabric
  • 1024Mbit QSPI Flash (EPCQL1024 Compliant)
  • 2 independent DDR4 banks with ECC.
    • Each 16GB Dual Rank DDR4-2666.
    • One bank is shared with FPGA and HPS
  • FMC (Vita57.1) connector with 10 transceivers
  • FMC+(Vita57.4) connector with 24 transceivers