Apollo S10 User Manual revA CH1
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***Each 16GB Dual Rank DDR4-2666. | ***Each 16GB Dual Rank DDR4-2666. | ||
***One bank is shared with FPGA and HPS | ***One bank is shared with FPGA and HPS | ||
| + | ***DDR4A REFCLK Selection | ||
**FMC (Vita57.1) connector with 10 transceivers | **FMC (Vita57.1) connector with 10 transceivers | ||
| + | ***FMC VADJ 1.8V/1.5V/1.2V Selection | ||
**FMC+(Vita57.4) connector with 24 transceivers | **FMC+(Vita57.4) connector with 24 transceivers | ||
| + | ***FMC+ VADJ 1.8V/1.5V/1.2V Selection | ||
| + | **Four 50Mhz Single-ended Clock Source | ||
| + | **One 100Mhz Single-ended Clock Source | ||
| + | **Clock Generator Si5341 | ||
| + | **LED x2, Button x2, Dip Switch x2, CPU Reset | ||
Revision as of 10:49, 4 December 2019
This chapter provides an overview of the Apollo S10 Development Board and installation guide.
1.1 General Description
待寫
1.2 Key Features
- FPGA Device
- Intel Stratix ® 10 SoC FPGA : 1SX280HU2F50
- 2,800K logic elements (LEs)
- 229 Mbits embedded memory(M20K)
- 96 transceivers (up to 28.3Gbps)
- 11,520 18-bit x 19-bit multipliers
- 5,760 Variable-precision DSP blocks
- Intel Stratix ® 10 SoC FPGA : 1SX280HU2F50
- FPGA Configuration
- On-Board USB Blaster II for FPGA programming and Debug
- AS Mode configuration from QSPI Flash
- FPGA Fabric
- 1024Mbit QSPI Flash (EPCQL1024 Compliant)
- 2 independent DDR4 banks with ECC.
- Each 16GB Dual Rank DDR4-2666.
- One bank is shared with FPGA and HPS
- DDR4A REFCLK Selection
- FMC (Vita57.1) connector with 10 transceivers
- FMC VADJ 1.8V/1.5V/1.2V Selection
- FMC+(Vita57.4) connector with 24 transceivers
- FMC+ VADJ 1.8V/1.5V/1.2V Selection
- Four 50Mhz Single-ended Clock Source
- One 100Mhz Single-ended Clock Source
- Clock Generator Si5341
- LED x2, Button x2, Dip Switch x2, CPU Reset
