DE10 Advance revC demo: AXI bridges in Intel SoC FPGA

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In Intel SoC FPGA, the HPS logic and FPGA fabric are connected through the AXI (Advanced eXtensible Interface) bridge. For HPS logic to communicate with FPGA fabric, Intel system integration tool Platform Designer should be used for the system design to add HPS component. From the AXI master port of the HPS component, HPS can access those Qsys components whose memory-mapped slave ports are connected to the master port.
The HPS contains the following HPS-FPGA AXI bridges.

  • FPGA-to-HPS Bridge
  • HPS-to-FPGA Bridge
  • Lightweight HPS-to-FPGA Bridge

Figure 4-1 shows a block diagram of the AXI bridges in the context of the FPGA fabric and the L3 interconnect to the HPS. Each master (M) and slave (S) interface is shown with its data width(s). The clock domain for each interconnect is noted in parentheses.

AXI Bridge Block Diagram.jpg
Figure 4-1 AXI Bridge Block Diagram

The HPS-to-FPGA bridge is mastered by the level 3 (L3) main switch and the lightweight HPS-to-FPGA bridge is mastered by the L3 slave peripheral switch.
The FPGA-to-HPS bridge masters the L3 main switch, allowing any master implemented in the FPGA fabric to access most slaves in the HPS. For example, the FPGA-to-HPS bridge can access the accelerator coherency.
All three bridges contain global programmer view GPV register. The GPV register control the behavior of the bridge. It is able to access to the GPV registers of all three bridges through the lightweight HPS-to-FPGA bridge.
This Demo introduces to users how to use the HPS/ARM to communicate with FPGA. This project includes GHRD project for the DE10-Advanced one ARM C Project which demonstrates how HPS/ARM program controls the LEDs connected to FPGA.


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