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This demonstration uses the Intel® FPGA HDMI IP core to implement the HDMI Retransmit function in the FPGA of the DE10-Advanced. As shown in Figure 1-1, User can connect an HDMI video player to the to input video and audio data to HDMI RX port of the DE10-Advanced. After the HDMI video data is received in the FPGA, it will be instantly transferred to the HDMI TX port. The user only needs to connect an HDMI screen to the DE10-advaned. User only needs to connect an HDMI screen to the DE10-advanced, then you can watch the images output by the HDMI Player. This demonstration supports image resolution up to 4K60P. If you want to learn HDMI high-performance related image processing, this demo can help you learn quickly.

System Block Diagram

Figure 1-2 shows the system block diagram of this example. It shows that the Intel® FPGA HDMI IP core is used in the FPGA. It is divided into two parts: Transmitter and Receiver. These two IPs can be directly used by Transition-minimized differential signaling (TMDS) interface connection, only need HDMI repeater or redrive IC as an intermediary to connect HDMI devices, no need to use special HDMI Transmitter and Receiver IC. For details about HDMI IP, please refer to HDMI Intel® FPGA IP User Guide and Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices.

This demonstration first needs to connect the DE10-Advanced to the HDMI interface screen. Because this demo can support various screen resolutions. When the DE10-Advanced connect to the monitor, the HDMI RX block in the FPGA will first read the supporting resolution of the monitor from the it's EDID and stored in the EDID RAM in the HDMI RX block. The NIOS handles the control signals between the EDID and the HDMI IP in this demo.

The HDMI Video player is then connected to the HDMI RX port of the DE10-Advanced. When the RX instance in the FPGA receives a video source from the external video generator, the video and audio data then goes through a loopback FIFO before it is transmitted to the TX instance. The final image and sound data will be displayed on the monitor connected to the TX end. For a more detailed IP block diagram in the example, refer to Figure 1-3.