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| - | This guide describes how to program the serial configuration (EPCS) device with Serial Flash Loader (SFL) function via the JTAG interface. Users can program EPCS devices with a JTAG indirect configuration (.jic) file, which is converted from a user-specified SRAM object file (.sof) in Quartus. The .sof file is generated after the project compilation is successful. The steps of converting .sof to .jic in Quartus II are listed below.
| + | *[[TSoM_Programming_the_EPCS_Device_revA|Rev A]] |
| | + | *[[TSoM_Programming_the_EPCS_Device_revB|Rev B]] |
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| - | | + | [[TSoM_Document|Back]] |
| - | == <span style="color:#000080;">1.1 Before Programming Begins</span> ==
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| - | The FPGA should be set to AS x1 mode i.e. MSEL[4..0] = “10010” to use the Flash as a FPGA configuration device.
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| - | Please install the 10K ohm resistors in the red resistor position in the figure belowㄡ
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| - | confirm that the red resistor position in the figure below does not have any resistors installed.
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| - | == <span style="color:#000080;">1.2 8.2 Convert .SOF File to .JIC File</span> ==
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| - | To programme the design file into the EPCS device, a .jic file is required. Here's how to convert the .sof file generated by Quartus compile to .jic.
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Latest revision as of 11:06, 24 July 2019
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