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Chpater1 Chapter 7PCI Express Design for Windows =

PCI Express is commonly used in consumer, server, and industrial applications, to link motherboard-mounted peripherals. From this demonstration, it will show how the PC Windows and FPGA communicate with each other through the PCI Express interface. Arria 10 Hard IP for PCI Express with Avalon-MM DMA IP is used in this demonstration. For detail about this IP, please refer to Altera document ug_a10_pcie_avmm_dma.pdf.

1-0-1 7.1 PCI Express System Infrastructure

Figure 7-1 shows the infrastructure of the PCI Express System in this demonstration. It consists of two primary components: FPGA System and PC System. The FPGA System is developed based on Arria 10 Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Altera’s PCIe kernel mode driver.

Figure 7-1 Infrastructure of PCI Express System

1-0-2 7.2 PC PCI Express Software SDK

The FPGA System CD contains a PC Windows based SDK to allow users to develop their 64-bit software application on 64-bits Windows XP/7/10. The SDK is located in the "CDROM\Demonstrations\PCIe_SW_KIT\Windows" folder which includes:

* PCI Express Driver

PCI Express Library
PCI Express Examples

The kernel mode driver assumes the PCIe vendor ID (VID) is 0x1172 and the device ID (DID) is 0xE003. If different VID and DID are used in the design, users need to modify the PCIe vendor ID (VID) and device ID (DID) in the driver INF file accordingly.

The PCI Express Library is implemented as a single DLL named TERASIC_PCIE_AVMM.DLL.This file is a 64-bit DLL. With the DLL is exported to the software API, users can easily communicate with the FPGA. The library provides the following functions:

* Basic data read and write

Data read and write by DMA

For high performance data transmission, Altera AVMM DMA is required as the read and write operations are specified under the hardware design on the FPGA.

1-0-3 7.3 PCI Express Software Stack

Figure 7-2 shows the software stack for the PCI Express application software on 64-bit Windows. The PCIe library module TERASIC_PCIE_AVMM.dll provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this DLL. The altera_pcie_win_driver.sys kernel driver is provided by Altera.

Figure 7-2 PCI Express Software Stack

*

Install PCI Express Driver on Windows

The PCIe driver is locate in the folder:

"CDROM\Demonstrations\PCIe_SW_KIT\Windows\PCIe_Driver"

The folder includes the following four files:

* Altera_pcie_win_driver.cat

Altera_pcie_win_driver.inf
Altera_pcie_win_driver.sys
WdfCoinstaller01011.dll

To install the PCI Express driver, please execute the steps below:

# Make sure the DE10-Advanced and the PC are both powered off.

Plug the PCIe adapter card into the PCIe slot on the PC motherboard. Use the PCIe cable to connect to the DE10-Advanced PCIE connector and the PCIe adapter card (See Figure 7-3)

Figure 7-3 FPGA board connect to PC

# Power on your DE10-Advanced board and the host PC

Make sure Altera Programmer and USB-Blaster II driver are installed
Execute test.bat in "CDROM\Demonstrations\PCIe_Fundamental\demo_batch" to configure the FPGA
Restart windows operation system
Click Control Panel menu from Windows Start menu. Click Hardware and Sound item before clicking the Device Manager to launch the Device Manager dialog. There will be a PCI Device item in the dialog, as shown in Figure 7-4. Move the mouse cursor to the PCI Device item and right click it to select the Update Driver Software... item.

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Figure 7-4 Screenshot of launching Update Driver Software… dialog

# In the How do you want to search for driver software dialog, click Browse my computer for driver software item, as shown in Figure 7-5.

500px. Click the Next button.

500px, click the Install button.

500px. Click the Close button.

500px.

Figure 7-9 Altera PCI API Driver in Device Manager

Create a Software Application

All the files needed to create a PCIe software application are located in the directory CDROM\demonstration\PCIe_SW_KIT\Windows\PCIe_Library. It includes the following files:

* TERASIC_PCIE_AVMM.h

TERASIC_PCIE_AVMM.dll (64-bit dll)

Below lists the procedures to use the SDK files in users’ C/C++ project :

# Create a 64-bit C/C++ project.

Include TERASIC_PCIE_AVMM.h in the C/C++ project.
Copy TERASIC_PCIE_AVMM.dll to the folder where the project.exe is located.
Dynamically load TERASIC_PCIE_AVMM.dll in C/C++ program. To load the dll, please refer to the PCIe fundamental example below.
Call the SDK API to implement the desired application.

Users can easily communicate with the FPGA through the PCIe bus through the TERASIC_PCIE_AVMM.dll API. The details of API are described below:

1-0-4 7.4 PCI Express Library API

Below shows the exported API in the TERASIC_PCIE_AVMM.dll. The API prototype is defined in the TERASIC_PCIE_AVMM.h.

Note: the Linux library terasic_pcie_qsys.so also use the same API and header file.

*

PCIE_Open

Function:

Open a specified PCIe card with vendor ID, device ID, and matched card index.

Prototype:

PCIE_HANDLE PCIE_Open(

uint8_t wVendorID,

uint8_t wDeviceID,

uint8_t wCardIndex);

Parameters:

wVendorID:

Specify the desired vendor ID. A zero value means to ignore the vendor ID.

wDeviceID:

Specify the desired device ID. A zero value means to ignore the device ID.

wCardIndex:

Specify the matched card index, a zero based index, based on the matched vendor ID and device ID.

Return Value:

Return a handle to presents specified PCIe card. A positive value is return if the PCIe card is opened successfully. A value zero means failed to connect the target PCIe card.

This handle value is used as a parameter for other functions, e.g. PCIE_Read32.

Users need to call PCIE_Close to release handle once the handle is no more used.

* PCIE_Close

Function:

Close a handle associated to the PCIe card.

Prototype:

void PCIE_Close(

PCIE_HANDLE hPCIE);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

Return Value:

None.

*

PCIE_Read32

Function:

Read a 32-bit data from the FPGA board.

Prototype:

bool PCIE_Read32(

PCIE_HANDLE hPCIE,

PCIE_BAR PcieBar,

PCIE_ADDRESS PcieAddress,

uint32_t *pdwData);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

PcieBar:

Specify the target BAR.

PcieAddress:

Specify the target address in FPGA.

pdwData:

A buffer to retrieve the 32-bit data.

Return Value:

Return true if read data is successful; otherwise false is returned.

*

PCIE_Write32

Function:

Write a 32-bit data to the FPGA Board.

Prototype:

bool PCIE_Write32(

PCIE_HANDLE hPCIE,

PCIE_BAR PcieBar,

PCIE_ADDRESS PcieAddress,

uint32_t dwData);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

PcieBar:

Specify the target BAR.

PcieAddress:

Specify the target address in FPGA.

dwData:

Specify a 32-bit data which will be written to FPGA board.

Return Value:

Return true if write data is successful; otherwise false is returned.

*

PCIE_Read8

Function:

Read an 8-bit data from the FPGA board.

Prototype:

bool PCIE_Read8(

PCIE_HANDLE hPCIE,

PCIE_BAR PcieBar,

PCIE_ADDRESS PcieAddress,

uint8_t *pByte);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

PcieBar:

Specify the target BAR.

PcieAddress:

Specify the target address in FPGA.

pByte:

A buffer to retrieve the 8-bit data.

Return Value:

Return true if read data is successful; otherwise false is returned.

*

PCIE_Write8

Function:

Write an 8-bit data to the FPGA Board.

Prototype:

bool PCIE_Write8(

PCIE_HANDLE hPCIE,

PCIE_BAR PcieBar,

PCIE_ADDRESS PcieAddress,

uint8_t Byte);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

PcieBar:

Specify the target BAR.

PcieAddress:

Specify the target address in FPGA.

Byte:

Specify an 8-bit data which will be written to FPGA board.

Return Value:

Return true if write data is successful; otherwise false is returned.

*

PCIE_DmaRead

Function:

Read data from the memory-mapped memory of FPGA board in DMA.

Maximal read size is (4GB-1) bytes.

Prototype:

bool PCIE_DmaRead(

PCIE_HANDLE hPCIE,

PCIE_LOCAL_ADDRESS LocalAddress,

void *pBuffer,

uint32_t dwBufSize

);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

LocalAddress:

Specify the target memory-mapped address in FPGA.

pBuffer:

A pointer to a memory buffer to retrieved the data from FPGA. The size of buffer should be equal or larger the dwBufSize.

dwBufSize:

Specify the byte number of data retrieved from FPGA.

Return Value:

Return true if read data is successful; otherwise false is returned.

*

PCIE_DmaWrite

Function:

Write data to the memory-mapped memory of FPGA board in DMA.

Prototype:

bool PCIE_DmaWrite(

PCIE_HANDLE hPCIE,

PCIE_LOCAL_ADDRESS LocalAddress,

void *pData,

uint32_t dwDataSize

);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

LocalAddress:

Specify the target memory mapped address in FPGA.

pData:

A pointer to a memory buffer to store the data which will be written to FPGA.

dwDataSize:

Specify the byte number of data which will be written to FPGA.

Return Value:

Return true if write data is successful; otherwise false is returned.

PCIE_ConfigRead32

Function:

Read PCIe Configuration Table. Read a 32-bit data by given a byte offset.

Prototype:

bool PCIE_ConfigRead32 (

PCIE_HANDLE hPCIE,

uint32_t Offset,

uint32_t *pdwData

);

Parameters:

hPCIE:

A PCIe handle return by PCIE_Open function.

Offset:

Specify the target byte of offset in PCIe configuration table.

pdwData:

A 4-bytes buffer to retrieve the 32-bit data.

Return Value:

Return true if read data is successful; otherwise false is returned.

1-0-5 7.5 PCIe Reference Design - Fundamental

The application reference design shows how to implement fundamental control and data transfer in DMA. In the design, basic I/O is used to control the BUTTON and LED on the FPGA board. High-speed data transfer is performed by DMA.

*

Demonstration Files Location

The demo file is located in the batch folder:

CDROM\Demonstrations\ PCIe_Fundamental\demo_batch

The folder includes following files:

* FPGA Configuration File: PCIe_Fundamental.sof

Download Batch file: test.bat
Windows Application Software folder : windows_app, includes

PCIE_FUNDAMENTAL.exe
TERASIC_PCIE_AVMM.DLL

*

Demonstration Setup

Install the FPGA board on your PC as shown in Figure 7-3.
Configure FPGA with PCIe_Fundamental.sof by executing the test.bat.
Install PCIe driver if necessary. The driver is located in the folder:

CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver.

# Restart Windows

Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in Figure 7-10.

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Figure 7-10 Screenshot for PCIe Driver

# Goto windows_app folder, execute PCIE_FUNDAMENTAL.exe. A menu will appear as shown in Figure 7-11.

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Figure 7-11 Screenshot of Program Menu

# Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in Figure 7-12. If input 0 (hex 0x00), all led will be turn off.

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Figure 7-12 Screenshot of LED Control

# Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in Figure 7-13.

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Figure 7-13 Screenshot of Button Status Report

# Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in Figure 7-14.

Figure 7-14 Screenshot of DMA Memory Test Result

# Type 99 followed by an ENTER key to exit this test program

Development Tools

Quartus Prime 18.0 Standard Edition
Visual C++ 2012

Demonstration Source Code Location

Quartus Project: Demonstrations\PCIe_Fundamental
C++ Project: Demonstrations\PCIe_SW_KIT\Windows\PCIE_FUNDAMENTAL

FPGA Application Design

Figure 7-15 shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.

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Figure 7-15 Hardware block diagram of the PCIe reference design

*

Windows Based Application Software Design

The application software project is built by Visual C++ 2012. The project includes the following major files:

Name	Description
PCIE_FUNDAMENTAL.cpp	Main program
PCIE.c	Implement dynamically load for TERAISC_PCIE_AVMM.DLL
PCIE.h
TERASIC_PCIE_AVMM.h	SDK library file, defines constant and data structure

The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.

500px

The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller.

Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the TERASIC_PCIE_AVMM.dll. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:

* The FPGA is configured with the associated bit-stream file and the host is rebooted.

The PCI express driver is loaded successfully.

The LED control is implemented by calling PCIE_Write32 API, as shown below:

500px

The button status query is implemented by calling the PCIE_Read32 API, as shown below:

500px

The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below:

1-0-6 7.6 PCIe Reference Design - DDR4

The application reference design shows how to add DDR4 Memory Controllers for DDR4-A SODIMM and on board DDR4-B into the PCIe Quartus project based on the PCIe_Fundamental Quartus project and perform 4GB data DMA for both SODIMM. Also, this demo shows how to call “PCIE_ConfigRead32” API to check PCIe link status.

*

Demonstration Files Location

The demo file is located in the batch folder:

CDROM\Demonstrations\PCIe_DDR4\demo_batch

The folder includes following files:

* FPGA Configuration File: PCIe_DDR4.sof

Download Batch file: test.bat
Windows Application Software folder : windows_app, includes

PCIE_DDR4.exe
TERASIC_PCIE_AVMM.dll

*

Demonstration Setup

Install DDR4 2400 4GB SODIMM on the FPGA board.
Install the FPGA board on your PC as shown in Figure 7-3.
Configure FPGA with PCIe_DDR4.sof by executing the test.bat.
Install PCIe driver if necessary.
Restart Windows
Make sure the Windows has detected the FPGA Board by checking the Windows Control panel.
Goto windows_app folder, execute PCIE_DDR4.exe. A menu will appear as shown in Figure 7-16.

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Figure 7-16 Screenshot of Program Menu

# Type 2 followed by a ENTER key to select Link Info item. The PCIe link information will be shown as in Figure 7-17. Gen3 link speed and x8 link width are expected.

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Figure 7-17 Screenshot of Link Info

# Type 3 followed by an ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in Figure 7-18.

500px

Figure 7-18 Screenshot of On-Chip Memory DMA Test Result

# Type 4 followed by an ENTER key to select DMA DDR4-A SODIMM Memory Test item. The DMA write and read test result will be report as shown in Figure 7-19.

500px

Figure 7-19 Screenshot of DDR4-A SOSIMM Memory DAM Test Result

# Type 5 followed by an ENTER key to select DMA DDR4-B Memory Test item. The DMA write and read test result will be report as shown in Figure 7-20.

500px

Figure 7-20 Screenshot of DDR4-B SOSIMM Memory DAM Test Result

# Type 99 followed by an ENTER key to exit this test program.

*

Development Tools

Quartus Prime 18.0 Standard Edition
Visual C++ 2012

Demonstration Source Code Location

Quartus Project: Demonstrations\PCIE_DDR4
Visual C++ Project: Demonstrations\PCIe_SW_KIT\Windows\PCIe_DDR4

FPGA Application Design

Figure 7-21 shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.

Figure 7-21 Hardware block diagram of the PCIe_DDR4 reference designWindows Based Application Software Design

The application software project is built by Visual C++ 2012. The project includes the following major files:

Name	Description
PCIE_DDR4.cpp	Main program
PCIE.c	Implement dynamically load for TERAISC_PCIE_AVMM.DLL
PCIE.h
TERASIC_PCIE_AVMM.h	SDK library file, defines constant and data structure

The main program PCIE_DDR4.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.

500px

The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. The above definition is the same as those in PCIe Fundamental demo.

Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the TERASIC_PCIE_AVMM.DLL. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:

* The FPGA is configured with the associated bit-stream file and the host is rebooted.

The PCI express driver is loaded successfully.

The LED control is implemented by calling PCIE_Write32 API, as shown below:

500px

The button status query is implemented by calling the PCIE_Read32 API, as shown below:

500px

The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below:

500px

The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below:

=

Chapter 8Chpater2 PCI Express Reference Design for Linux =

PCI Express is commonly used in consumer, server, and industrial applications, to link motherboard-mounted peripherals. From this demonstration, it will show how the PC Linux and FPGA communicate with each other through the PCI Express interface. Arria 10 Hard IP for PCI Express with Avalon-MM DMA IP is used in this demonstration. For detail about this IP, please refer to Altera document ug_a10_pcie_avmm_dma.pdf.

2-0-7 8.1 PCI Express System Infrastructure

Figure 8-1 shows the infrastructure of the PCI Express System in this demonstration. It consists of two primary components: FPGA System and PC System. The FPGA System is developed based on Arria 10 Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Altera’s PCIe kernel mode driver.

500px

Figure 8-1 Infrastructure of PCI Express System

2-0-8 8.2 PC PCI Express Software SDK

The FPGA System CD contains a PC Windows based SDK to allow users to develop their 64-bit software application on 64-bits Linux. CentOS 7.2 is recommended. The SDK is located in the “CDROM/Demonstrations/PCIe_SW_KIT/Linux” folder which includes:

* PCI Express Driver

PCI Express Library
PCI Express Examples

The kernel mode driver assumes the PCIe vendor ID (VID) is 0x1172 and the device ID (DID) is 0xE003. If different VID and DID are used in the design, users need to modify the PCIe vendor ID (VID) and device ID (DID) in the driver project and rebuild the driver. The ID is defined in the file PCIe_SW_KIT/Linux/PCIe_Driver/altera_pcie_cmd.h.

The PCI Express Library is implemented as a single .so file named terasic_pcie_qsys.so.This file is a 64-bit library file. With the library exported software API, users can easily communicate with the FPGA. The library provides the following functions:

* Basic data read and write

Data read and write by DMA

For high performance data transmission, Altera AVMM DMA is required as the read and write operations are specified under the hardware design on the FPGA.

2-0-9 8.3 PCI Express Software Stack

Figure 8-2 shows the software stack for the PCI Express application software on 64-bit Linux. The PCIe library module terasic_pcie_qys.so provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this .so library file. The altera_pcie.ko kernel driver is provided by Altera.

Figure 8-2 PCI Express Software Stack

*

Install PCI Express Driver on Linux

To make sure the PCIe driver can meet your kernel of Linux distribution, the driver altera_pcie.ko should be recompile before use it. The PCIe driver project is locate in the folder:

"CDROM/Demonstrations/PCIe_SW_KIT/Linux/PCIe_Driver"

The folder includes the following files:* altera_pcie.c

altera_pcie.h
altera_pcie_cmd.h
Makefile
load_driver
unload
config_file

To compile and install the PCI Express driver, please execute the steps below:

Make sure the DE10-Advanced and the PC are both powered off.
Plug the PCIe adapter card into the PCIe slot on the PC motherboard. Use the PCIe cable to connect to the DE10-Advanced PCIE connector and the PCIe adapter card (See Figure 8-3)

Figure 8-3 FPGA board connect to PC

# Power on your DE10-Advanced board and the host PC

Open a terminal and use "cd" command to goto the folder"CDROM/Demonstrations/PCIe_Fundamental/demo_batch".
Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path. Set QUARTUS_ROOTDIR variable by tying the following commands in terminal. Replace “/home/centos/intelFPGA/18.0/quartus” to your quartus installation path.

export QUARTUS_ROOTDIR=/home/centos/intelFPGA/18.0/quartus

Execute "sudo -E sh test.sh" command to configure the FPGA
Restart Linux operation system. In Linux, open a terminal and use “cd” command to goto the PCIe_Driver folder
Type the following commands to compile and install the driver altera_pcie.ko, and make sure driver is loaded successfully and FPGA is detected by the driver as shown in Figure 8-4.

make
sudo sh load_driver
dmesg | tail -n 15

Figure 8-4 Screenshot of install PCIe driver

*

Create a Software Application

All the files needed to create a PCIe software application are located in the directory CDROM/Demonstrations/PCIe_SW_KIT/Linux/PCIe_Library. It includes the following files:

* TERASIC_PCIE_AVMM.h

terasic_pcie_qsys.so (64-bit library)

Below lists the procedures to use the library in users’ C/C++ project:

# Create a 64-bit C/C++ project.

Include TERASIC_PCIE_AVMM.h in the C/C++ project.
Copy terasic_pcie_qsys.so to the folder where the project execution file is located.
Dynamically load terasic_pcie_qsys.so in C/C++ program. To load the terasic_pcie_qsys.so, please refer to the PCIe fundamental example below.
Call the library API to implement the desired application.

Users can easily communicate with the FPGA through the PCIe bus through the terasic_pcie_qsys.so API. The details of API are described below:

2-0-10 8.4 PCI Express Library API

The API is the same as Windows Library. Please refer to the section 7.4 PCI Express Library API in this document.

2-0-11 8.5 PCIe Reference Design – Fundamental

The application reference design shows how to implement fundamental control and data transfer in DMA. In the design, basic I/O is used to control the BUTTON and LED on the FPGA board. High-speed data transfer is performed by DMA.

*

Demonstration Files Location

The demo file is located in the batch folder:

CDROM/Demonstrations/PCIe_Fundamental/demo_batch

The folder includes following files:

* FPGA Configuration File: PCIe_Fundamental.sof

Download Batch file: test.sh
Linux Application Software folder : linux_app, includes

PCIE_FUNDAMENTAL
terasic_pcie_qsys.so

Demonstration Setup

Install the FPGA board on your PC as shown in Figure8-3.
Open a terminal and use "cd" command to goto "CDROM/Demonstrations/PCIe_Fundamental/demo_batch".
Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path. Set QUARTUS_ROOTDIR variable by tying the following commands in terminal. Replace /home/centos/intelFPGA/18.0/quartus to your quartus installation path.

export QUARTUS_ROOTDIR=/home/centos/intelFPGA/18.0/quartus

Execute "sudo -E sh test.sh" command to configure the FPGA
Restart Linux
Install PCIe driver. The driver is located in the folder:

CDROM/Demonstration/PCIe_SW_KIT/Linux/PCIe_Driver.

# Type “ls –l /dev/altera_pcie*” to make sure the Linux has detected the FPGA Board. If the FPGA board is detected, developers can find the /dev/altera_pcieX(where X is 0~255) in Linux file system as shown below.

500px.

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Figure 8-5 Screenshot of Program Menu

# Type 0 followed by a ENTER key to select Led Control item, then input 3 (hex 0x03) will make all led on as shown in Figure 8-6. If input 0 (hex 0x00), all led will be turn off.

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Figure 8-6 Screenshot of LED Control

#

Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in Figure 8-7.

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Figure 8-7 Screenshot of Button Status Report

#

Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in Figure 8-8.

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Figure 8-8 Screenshot of DMA Memory Test Result

# Type 99 followed by an ENTER key to exit this test program

Development Tools

Quartus Prime 18.0 Standard Edition
GNU Compiler Collection, Version 4.8 is recommend

Demonstration Source Code Location

Quartus Project: Demonstrations/PCIe_Fundamental
C++ Project: Demonstrations/PCIe_SW_KIT/Linux/PCIE_FUNDAMENTAL

FPGA Application Design

Figure 8-9 shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.

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Figure 8-9 Hardware block diagram of the PCIe reference design

*

Linux Based Application Software DesignThe application software project is built by GNU Toolchain. The project includes the following major files:

Name	Description
PCIE_FUNDAMENTAL.cpp	Main program
PCIE.c	Implement dynamically load for terasic_pcie_qsys.so library file
PCIE.h
TERASIC_PCIE_AVMM.h	SDK library file, defines constant and data structure

The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.

The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller.

Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the terasic_pcie_qsys.so. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:

* The FPGA is configured with the associated bit-stream file and the host is rebooted.

The PCI express driver is loaded successfully.

The LED control is implemented by calling PCIE_Write32 API, as shown below:

The button status query is implemented by calling the PCIE_Read32 API, as shown below:

The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below:

2-0-12 8.5 PCIe Reference Design - DDR4

The application reference design shows how to add DDR4 Memory Controllers for DDR4-A SODIMM and on board DDR4-B into the PCIe Quartus project based on the PCIe_Fundamental Quartus project and perform 4GB data DMA for both SODIMM. Also, this demo shows how to call “PCIE_ConfigRead32” API to check PCIe link status.

*

Demonstration Files Location

The demo file is located in the batch folder:

CDROM/Demonstrations/ PCIe_DDR4/demo_batch

The folder includes following files:

* FPGA Configuration File: PCIe_DDR4sof

Download Batch file: test.sh
Linux Application Software folder : linux_app, includes

PCIE_DDR4
terasic_pcie_qsys.so

Demonstration Setup

Install DDR4 2400 4GB SODIMM on the FPGA board.
Install the FPGA board on your PC as shown in Figure8-3.
Open a terminal and use "cd" command to goto "CDROM/Demonstrations/PCIe_Fundamental/demo_batch".
Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path. Set QUARTUS_ROOTDIR variable by tying the following commands in terminal. Replace /home/centos/intelFPGA/18.0/quartus to your quartus installation path.

export QUARTUS_ROOTDIR=/home/centos/intelFPGA/18.0/quartus

Execute "sudo -E sh test.sh" command to configure the FPGA
Restart Linux
Install PCIe driver.
Make sure the Linux has detected the FPGA Board.
Goto linux_app folder, execute PCIE_DDR4. A menu will appear as shown in Figure 8-10.

Figure 8-10 Screenshot of Program Menu

# Type 2 followed by an ENTER key to select Link Info item. The PCIe link information will be shown as in Figure 8-11. Gen3 link speed and x8 link width are expected.

500px

Figure 8-11 Screenshot of Link Info

#

Type 3 followed by an ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in Figure 8-12.

500px

Figure 8-12 Screenshot of On-Chip Memory DMA Test Result

# Type 4 followed by an ENTER key to select DMA DDR4-A SODIMM Memory Test item. The DMA write and read test result will be report as shown in Figure 8-14.

500px

Figure 8-14 Screenshot of DDR4-A SOSIMM Memory DAM Test Result

# Type 5 followed by an ENTER key to select DMA DDR4-B Memory Test item. The DMA write and read test result will be report as shown in Figure 8-15.

500px

Figure 8-15 Screenshot of DDR4-B SOSIMM Memory DAM Test Result

# Type 99 followed by an ENTER key to exit this test program.

Development Tools

Quartus Prime 18.0 Standard Edition
GNU Compiler Collection, Version 4.8 is recommended

Demonstration Source Code Location

Quartus Project: Demonstrations/PCIE_DDR4
C++ Project: Demonstrations/PCIe_SW_KIT/Linux/PCIe_DDR4

FPGA Application Design

Figure 8-16 shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.

500px

Figure 8-16 Hardware block diagram of the PCIe_DDR4 reference design

*

Linux Based Application Software Design

The application software project is built by GNU Toolchain. The project includes the following major files:

Name	Description
PCIE_DDR4.cpp	Main program
PCIE.c	Implement dynamically load for terasic_pcie_qsys.so library file
PCIE.h
TERASIC_PCIE_AVMM.h	SDK library file, defines constant and data structure

The main program PCIE_DDR4.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.

The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. The above definition is the same as those in PCIe Fundamental demo.

Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the terasic_pcie_qsys.so. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:

* The FPGA is configured with the associated bit-stream file and the host is rebooted.

The PCI express driver is loaded successfully.

The LED control is implemented by calling PCIE_Write32 API, as shown below:

500px

The button status query is implemented by calling the PCIE_Read32 API, as shown below:

The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below:

500px

The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below:

Word2wiki bal gsq

From Terasic Wiki

Latest revision as of 13:31, 27 August 2018

Contents

Chpater1 Chapter 7PCI Express Design for Windows =

1-0-1 7.1 PCI Express System Infrastructure

1-0-2 7.2 PC PCI Express Software SDK

1-0-3 7.3 PCI Express Software Stack

1-0-4 7.4 PCI Express Library API

1-0-5 7.5 PCIe Reference Design - Fundamental

1-0-6 7.6 PCIe Reference Design - DDR4

Chapter 8Chpater2 PCI Express Reference Design for Linux =

2-0-7 8.1 PCI Express System Infrastructure

2-0-8 8.2 PC PCI Express Software SDK

2-0-9 8.3 PCI Express Software Stack

2-0-10 8.4 PCI Express Library API

2-0-11 8.5 PCIe Reference Design – Fundamental

2-0-12 8.5 PCIe Reference Design - DDR4

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@@ Line 1: / Line 1: @@
-=  <span style="color:#000080;">Introduction</span>=
-Based on the Terasic DE10-Nano SoC board platform, designed and manufactured independently by Terasic, the Self-Balancing Robot is a Multi-functional kit. It can implement advanced features like object following, obstacle avoidance and so on. It can also be remote controlled by an Android Smartphone’s APP and IR remote control. This guide describes in detail how users can make the robot work.
-==  Package Contents ==
+=
+=  <span style="color:#000000;">Chpater1 Chapter 7</span>PCI Express Design for Windows ==
-<span style="color:#666699;">'''Figure  1 -1'''</span>shows the package contents of the Self-Balancing Robot kit
-<div style="text-align:center;color:#000000;">[[File:02 Getting Start Guide html 94619baf10419f6e.jpg|800px]]</div>
-<div style="text-align:center;"> '''Figure 1‑1 Self-Balancing Robot package'''</div>
-The Self-Balancing Robot kit package contents:
+<div style="color:#404040;">PCI Express is commonly used in consumer, server, and industrial applications, to link motherboard-mounted peripherals. From this demonstration, it will show how the PC Windows and FPGA communicate with each other through the PCI Express interface. Arria 10 Hard IP for PCI Express with Avalon-MM DMA IP is used in this demonstration. For detail about this IP, please refer to Altera document [https://www.altera.com/en_US/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf ug_a10_pcie_avmm_dma.pdf].</div>
-① Self-Balancing Robot
-② Lithium Battery
-③ Lithium Battery Charger
+=== 1-0-1 7.1 PCI Express System Infrastructure ===
-④ IR Remote Control
-⑤ Mini USB Cable
+[[#Figure71|Figure 7-1]] shows the infrastructure of the PCI Express System in this demonstration. It consists of two primary components: FPGA System and PC System. The FPGA System is developed based on Arria 10 Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Altera’s PCIe kernel mode driver.
-⑥ Micro USB Cable
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_1.jpg|500px]]</div>
-⑦ Quick Start Guide
+<div style="text-align:center;">'''Figure 7-1 Infrastructure of PCI Express System'''</div>
-=  <span style="color:#000080;">Components and Functions</span> =
-==  Parts and Functions ==
+=== 1-0-2 7.2 PC PCI Express Software SDK ===
-This chapter will describe the robot’s components and the functions of the components, such as the ultrasonic module, motors, wheels and driving board power interface. Figure  2 -2, Figure  2 -3, Figure  2 -4and Figure  2 -5show all the components and specify their function.
-<div style="text-align:center;color:#000000;">[[Image:图片 1.png|top]]</div>
+<div style="color:#404040;">The FPGA System CD contains a PC Windows based SDK to allow users to develop their 64-bit software application on 64-bits Windows XP/7/10. The SDK is located in the "CDROM\Demonstrations\PCIe_SW_KIT\Windows" folder which includes:</div>* PCI Express Driver
+* PCI Express Library
+* PCI Express Examples
-<div style="text-align:center;"> '''Figure 2‑2 Self-Balancing Robot components'''</div>
-⑴ Ultrasonic module：implements obstacle avoidance.
-⑵ Battery package：helps to protect the batteries and avoid bumping and damaging the battery.
+<div style="color:#404040;">The kernel mode driver assumes the PCIe vendor ID (VID) is 0x1172 and the device ID (DID) is 0xE003. If different VID and DID are used in the design, users need to modify the PCIe vendor ID (VID) and device ID (DID) in the driver INF file accordingly.</div>
-⑶ Motors：drive the Self-Balancing robot wheels.
-⑷ Wheels：implements the Self-Balancing robot’s movement.
+<div style="color:#404040;">The PCI Express Library is implemented as a single DLL named TERASIC_PCIE_AVMM.DLL.This file is a 64-bit DLL. With the DLL is exported to the software API, users can easily communicate with the FPGA. The library provides the following functions:</div>* Basic data read and write
+* Data read and write by DMA
-<div style="text-align:center;color:#000000;">[[Image:图片 3.png|top]]</div>
-<div style="text-align:center;"> '''Figure 2‑3 Self-Balancing Robot components'''</div>
-⑸ Ethernet port：implements connecting to the ethernet when users develop their own designs on the Self-Balancing robot.
+<div style="color:#404040;">For high performance data transmission, Altera AVMM DMA is required as the read and write operations are specified under the hardware design on the FPGA.</div>
-⑹ OTG port：implements Host or Device mode when users develop their own design on the Self-Balancing robot.
-⑺ UART serial port：implement the communication between the board and PC when users develop their own design on the Self-Balancing robot.
+=== 1-0-3 7.3 PCI Express Software Stack ===
-<div style="text-align:center;color:#000000;">[[Image:图片 4.png|top]]</div>
-<div style="text-align:center;"> '''Figure 2‑4 Self-Balancing Robot components'''</div>
+[[#Figure72|Figure 7-2]]<span style="color:#1f4e79;"> '''</span>shows the software stack for the PCI Express application software on 64-bit Windows. The PCIe library module TERASIC_PCIE_AVMM.dll provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this DLL. The altera_pcie_win_driver.sys kernel driver is provided by Altera.
-⑻ DE10-Nano Development Board power supply jack：5V power supply port.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_2.jpg|500px]]</div>
-⑼ HDMI TX port：users can connect the Displayer to HDMI interface when they make image processing designs.
+<div style="text-align:center;">'''Figure 7-2 PCI Express Software Stack'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Install PCI Express Driver on Windows'''</div>
-⑽ USB Blaster II port：users can download their own programs to the board through the connector.
-⑾ Motor driver board power jack：connects to the battery power supply port and provides power for the Self-Balancing robot.
-⑿ Main power Switch：power on or power off the Self-Balancing robot.
+<div style="color:#404040;">The PCIe driver is locate in the folder:</div>
-⒀ Battery power output plug：connect to motor driver board power port.
+<div style="text-align:center;">"CDROM\Demonstrations\PCIe_SW_KIT\Windows\PCIe_Driver"</div>
-<div style="text-align:center;color:#000000;">   [[Image:图片 5.png|top]]</div>
+<div style="color:#404040;">The folder includes the following four files:</div>* Altera_pcie_win_driver.cat
+* Altera_pcie_win_driver.inf
+* Altera_pcie_win_driver.sys
+* WdfCoinstaller01011.dll
-<div style="text-align:center;"> '''Figure 2‑5 Self-Balancing robot components'''</div>
-⒁ Battery charging jack：connects the charger to charge the battery.
-⒂ Battery：the Self-Balancing robot’s power source.
+<div style="color:#404040;">To install the PCI Express driver, please execute the steps below: </div># Make sure the  DE10-Advanced and the PC are both powered off.
+# Plug the PCIe adapter card into the PCIe slot on the PC motherboard. Use the PCIe cable to connect to the  DE10-Advanced PCIE connector and the PCIe adapter card (See<span style="color:#1f4e79;">''' </span>[[#Figure73|Figure 7-3]])
+<div style="margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_3.jpg|500px]]</div>
-==  DE10-Nano Kit and Motor Driver Board ==
+<div style="text-align:center;">'''Figure 7-3 FPGA board connect to PC'''</div># Power on your DE10-Advanced board and the host PC
+# Make sure Altera Programmer and USB-Blaster II driver are installed
+# Execute test.bat in "CDROM\Demonstrations\PCIe_Fundamental\demo_batch" to configure the FPGA
+# Restart windows operation system
+# Click Control Panel menu from Windows Start menu. Click Hardware and Sound item before clicking the Device Manager to launch the Device Manager dialog. There will be a PCI Device item in the dialog, as shown in [[#Figure74|Figure 7-4]]. Move the mouse cursor to the PCI Device item and right click it to select the Update Driver Software... item.
-The Self-Balancing Robot control system consist two boards, Terasic DE10-Nano FPGA board and Motor Driver board (BAL board) as shown in Figure  2 -6. The FPGA on the DE10-Nano is responsible for all the functions of the balance and control system. The motor driver board receives the control signal from the de10-nano to control the motor rotation. There are also some sensors and communication devices on the motor driver board. These devices can provide the status data of the robot and external communication interface to FPGA. For detailed hardware information, please refer to 03_Hardware_Manual.pdf which can be found in the CD package.
-<div style="text-align:center;color:#ff0000;">[[Image:SNAGHTML299ca13.png|top]]</div>
-<div style="text-align:center;"> '''Figure 2‑6 DE10-Nano and Motor Driver Board'''</div>
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_4.jpg|500px]]</div>
-=  <span style="color:#000080;">Setup Elements</span> =
+<div style="text-align:center;">'''Figure 7-4 Screenshot of launching Update Driver Software… dialog'''</div># In the '''How do you want to search for driver software''' dialog, click '''Browse my computer for driver software''' item, as shown in [[#Figure75|Figure 7-5]]<span style="color:#1f4e79;">.'''</span>
-This chapter will introduce the switches and buttons that can be set on the Self-Balancing Robot. It explains the meaning and function of the setting.  ==  Configuration Mode Switches ==
-The Self-Balancing Robot equips a Cyclone SoC FPGA, which means that the ARM processor is embedded in the FPGA. Therefore, there are two processor options available to control the Robot. One is to use the ARM processor and the other is implement a NIOS II processor in the FPGA. The kit provides the factory code for both processor. To switch between these two processor modes, user need to select via the mode select switch(MSEL[4:0]).
-If user want to select ARM to control the robot, the MSEL[4:0] needs to switch to "01010" , as shown in Figure  3 -7. Thus, when the robot is power on, the FPGA will boot from the Micro SD card and run the Linux by ARM processor to control the robot.
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_5.jpg|500px]]. Click the '''Next''' button.
-<div style="text-align:center;"> [[Image:图片 33.png|top]]</div>
-<div style="text-align:center;"> '''Figure 3‑7 Set MSEL[4:0] to 01010'''</div>
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_6.jpg|500px]], click the '''Install''' button.
-When MSEL[4:0] is set to "10010", as shown in Figure  3 -8.The FPGA will boot from the configuration device(EPCS). Then, after FPGA is configured, the NIOS II processor will control the robot. For users who is beginners to learn FPGA, using NIOS II processor will be easier than deal with the ARM processor.
-<div style="text-align:center;">  [[Image:图片 32.png|top]]</div>
-<div style="text-align:center;"> '''Figure 3‑8 Set MSEL[4:0] to 10010''' </div>==  Operation Mode Switches ==
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_7.jpg|500px]]. Click the '''Close''' button.
-Figure  3 -9shows the SW0 and SW1 on the DE10-Nano board, Table  3 -1describes the corresponding modes and functions when SW0 and SW1 are set to different positions.
-<div style="text-align:center;color:#ff0000;">[[Image:图片 6.png|top]]</div>
-<div style="text-align:center;"> '''Figure 3‑9 SW0 and SW1 on DE10-Nano board'''</div>
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_8.jpg|500px]].
-<div style="color:#000000;margin-left:0cm;margin-right:0cm;">     '''Table 3‑1 SW0 and SW1 purpose'''</div>
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_9.jpg|500px]]</div>
-{| align="center" style="border-spacing:0;width:14.762cm;"
+<div style="text-align:center;">'''Figure 7-9 Altera PCI API Driver in Device Manager'''</div>
+* <div style="margin-left:0cm;margin-right:0cm;">'''Create a Software Application'''</div>
+<div style="color:#404040;">All the files needed to create a PCIe software application are located in the directory CDROM\demonstration\PCIe_SW_KIT\Windows\PCIe_Library. It includes the following files:</div>* TERASIC_PCIE_AVMM.h
+* TERASIC_PCIE_AVMM.dll (64-bit dll)
+<div style="color:#404040;">Below lists the procedures to use the SDK files in users’ C/C++ project :</div># Create a 64-bit C/C++ project.
+# Include TERASIC_PCIE_AVMM.h in the C/C++ project.
+# Copy TERASIC_PCIE_AVMM.dll to the folder where the project.exe is located.
+# Dynamically load TERASIC_PCIE_AVMM.dll in C/C++ program. To load the dll, please refer to the PCIe fundamental example below.
+# Call the SDK API to implement the desired application.
+<div style="color:#404040;">Users can easily communicate with the FPGA through the PCIe bus through the TERASIC_PCIE_AVMM.dll API. The details of API are described below:</div>
+=== 1-0-4 7.4 PCI Express Library API ===
+<div style="color:#404040;">Below shows the exported API in the TERASIC_PCIE_AVMM.dll. The API prototype is defined in the TERASIC_PCIE_AVMM.h. </div>
+<div style="color:#404040;">Note: the Linux library terasic_pcie_qsys.so also use the same API and header file.</div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Open'''</div>
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Open a specified PCIe card with vendor ID, device ID, and matched card index.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+PCIE_HANDLE PCIE_Open(
+uint8_t wVendorID,
+uint8_t wDeviceID,
+uint8_t wCardIndex);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+wVendorID:
+Specify the desired vendor ID. A zero value means to ignore the vendor ID.
+wDeviceID:
+Specify the desired device ID. A zero value means to ignore the device ID.
+wCardIndex:
+Specify the matched card index, a zero based index, based on the matched vendor ID and device ID.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return a handle to presents specified PCIe card. A positive value is return if the PCIe card is opened successfully. A value zero means failed to connect the target PCIe card.
+This handle value is used as a parameter for other functions, e.g. PCIE_Read32.
+Users need to call PCIE_Close to release handle once the handle is no more used.
 |-
-| style="background-color:#bfbfbf;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;" | <span style="color:#000000;">'''S</span><span style="color:#000000;">W[1:0]</span><span style="color:#000000;"> Setting'''</span>
+|}
-| style="background-color:#bfbfbf;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''Robot mode and function'''
+<div style="margin-left:0cm;margin-right:0cm;"></div>* '''PCIE_Close'''
-| style="background-color:#bfbfbf;border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''Description'''
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Close a handle associated to the PCIe card.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+void PCIE_Close(
+PCIE_HANDLE hPCIE);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+None.
 |-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 00
+|}
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;" | <span style="color:#000000;">Default mode (Bluetooth and IR mode) </span>
+<div style="margin-left:0cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Read32'''</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | The robot can be controlled by smartphone APP and IR remote control
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Read a 32-bit data from the FPGA board.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+bool PCIE_Read32(
+PCIE_HANDLE hPCIE,
+PCIE_BAR PcieBar,
+PCIE_ADDRESS PcieAddress,
+uint32_t *pdwData);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+PcieBar:
+Specify the target BAR.
+PcieAddress:
+Specify the target address in FPGA.
+pdwData:
+A buffer to retrieve the 32-bit data.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if read data is successful; otherwise '''false''' is returned.
 |-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 10
+|}
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;" | <span style="color:#000000;">Default mode and Obstacle Avoidance</span>
+<div style="margin-left:0cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Write32'''</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | The robot can be controlled by a smartphone’s APP and IR remote control, it implements the obstacle avoidance function
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Write a 32-bit data to the FPGA Board.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+bool PCIE_Write32(
+PCIE_HANDLE hPCIE,
+PCIE_BAR PcieBar,
+PCIE_ADDRESS PcieAddress,
+uint32_t dwData);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+PcieBar:
+Specify the target BAR.
+PcieAddress:
+Specify the target address in FPGA.
+dwData:
+Specify a 32-bit data which will be written to FPGA board.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if write data is successful; otherwise '''false''' is returned.
 |-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 01
+|}
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Object following and obstacle avoidance
+<div style="margin-left:0cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Read8'''</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;" | <span style="color:#000000;">The robot implements the object following and obstacle avoidance </span><span style="color:#0000ff;">(In this mode, the robot will not be controlled by smartphone APP and IR remote control)</span>
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Read an 8-bit data from the FPGA board.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+bool PCIE_Read8(
+PCIE_HANDLE hPCIE,
+PCIE_BAR PcieBar,
+PCIE_ADDRESS PcieAddress,
+uint8_t *pByte);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+PcieBar:
+Specify the target BAR.
+PcieAddress:
+Specify the target address in FPGA.
+pByte:
+A buffer to retrieve the 8-bit data.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if read data is successful; otherwise '''false''' is returned.
 |-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 11
+|}
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Debug mode
+<div style="margin-left:0cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_Write8'''</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Only supports ARM version robot, the control program will stop running, users need to reboot the robot or run the program again to control the robot. Normally it is used to debug the robot.
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Write an 8-bit data to the FPGA Board.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+bool PCIE_Write8(
+PCIE_HANDLE hPCIE,
+PCIE_BAR PcieBar,
+PCIE_ADDRESS PcieAddress,
+uint8_t Byte);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+PcieBar:
+Specify the target BAR.
+PcieAddress:
+Specify the target address in FPGA.
+Byte:
+Specify an 8-bit data which will be written to FPGA board.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if write data is successful; otherwise '''false''' is returned.
 |-
 |}
+<div style="margin-left:0cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_DmaRead'''</div>
-==  LEDs on the Motor Driver Board   ==
-Figure  3 -10shows the LED1 and LED2 on the motor driver board, Table  3 -2describes the functions of LED1 and LED2.
-<div style="text-align:center;color:#ff0000;"><span style="color:#000000;">[[Image:图片 7.png|top]]</span><span style="color:#000000;"></span></div>
-<div style="text-align:center;"> '''Figure 3‑10 LED1 and LED2 on the motor driver board'''</div>
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
-<div style="margin-left:0cm;margin-right:0cm;"> <span style="color:#000000;">'''Table </span><span style="color:#000000;">3</span><span style="color:#000000;">‑</span><span style="color:#000000;">2</span><span style="color:#000000;"> '''</span>Motor driver board LEDs functions</div>
+Read data from the memory-mapped memory of FPGA board in DMA.
+Maximal read size is (4GB-1) bytes.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
-{| align="center" style="border-spacing:0;width:14.651cm;"
+bool PCIE_DmaRead(
+PCIE_HANDLE hPCIE,
+PCIE_LOCAL_ADDRESS LocalAddress,
+void *pBuffer,
+uint32_t dwBufSize
+);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+LocalAddress:
+Specify the target memory-mapped address in FPGA.
+pBuffer:
+A pointer to a memory buffer to retrieved the data from FPGA. The size of buffer should be equal or larger the dwBufSize.
+dwBufSize:
+Specify the byte number of data retrieved from FPGA.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if read data is successful; otherwise '''false''' is returned.
 |-
-| style="background-color:#bfbfbf;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''LED name'''
+|}
-| style="background-color:#bfbfbf;border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''Description'''
+<div style="margin-left:0cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_DmaWrite'''</div>
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED1
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Indicates the power supply status to motor driver board
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED2
+{| style="border-spacing:0;width:15.251cm;"
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Indicates the motor driver board provides 5V power to the DE10-Nano board
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Write data to the memory-mapped memory of FPGA board in DMA.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+bool PCIE_DmaWrite(
+PCIE_HANDLE hPCIE,
+PCIE_LOCAL_ADDRESS LocalAddress,
+void *pData,
+uint32_t dwDataSize
+);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+LocalAddress:
+Specify the target memory mapped address in FPGA.
+pData:
+A pointer to a memory buffer to store the data which will be written to FPGA.
+dwDataSize:
+Specify the byte number of data which will be written to FPGA.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if write data is successful; otherwise '''false''' is returned.
 |-
 |}
-==  LEDs on DE10-Nano Board ==
+* <div style="margin-left:0cm;margin-right:0cm;"></div>
+* <div style="margin-left:0cm;margin-right:0cm;">'''PCIE_ConfigRead32'''</div>
-Figure  3 -11shows the 3.3V power LED, CONF_D LED and other LEDS on the DE10-Nano board, Table  3 -3describes the LEDs functions.
-<div style="text-align:center;"> [[Image:图像2.png|top]]</div>
-<div style="text-align:center;"> '''Figure 3‑11 Indicator LEDs on DE10-Nano board'''</div>
-<div style="text-align:center;margin-left:0.423cm;margin-right:0cm;"> <span style="color:#000000;">'''Table </span><span style="color:#000000;">3</span><span style="color:#000000;">‑</span><span style="color:#000000;">3</span><span style="color:#000000;"> '''</span>Indicator LEDs on the DE10-Nano board</div>
+{| style="border-spacing:0;width:15.251cm;"
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Function:'''
+Read PCIe Configuration Table. Read a 32-bit data by given a byte offset.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Prototype:'''
+bool PCIE_ConfigRead32 (
+PCIE_HANDLE hPCIE,
+uint32_t Offset,
+uint32_t *pdwData
+);
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Parameters:'''
+hPCIE:
+A PCIe handle return by PCIE_Open function.
+Offset:
+Specify the target byte of offset in PCIe configuration table.
+pdwData:
+A 4-bytes buffer to retrieve the 32-bit data.
+|- style="background-color:#e6e6e6;border:0.5pt solid #00000a;padding:0cm;"
+|| '''Return Value:'''
+Return '''true''' if read data is successful; otherwise '''false''' is returned.
-{| style="border-spacing:0;width:15.512cm;"
 |-
-| style="background-color:#bfbfbf;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''LED name'''
+|}
-| style="background-color:#bfbfbf;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''LED status'''
-| style="background-color:#bfbfbf;border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''Description'''
+=== 1-0-5 7.5 PCIe Reference Design - Fundamental ===
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 3.3V power LED
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
+<div style="color:#404040;">The application reference design shows how to implement fundamental control and data transfer in DMA. In the design, basic I/O is used to control the BUTTON and LED on the FPGA board. High-speed data transfer is performed by DMA.</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Files Location'''</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Power the DE10-Nano board with 3.3V from the GPIO interface
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | CONF_D
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
+<div style="color:#404040;">The demo file is located in the batch folder: </div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | DE10-Nano board Configuration done
+<div style="text-align:center;">CDROM\Demonstrations\ PCIe_Fundamental\demo_batch</div>
+<div style="color:#404040;">The folder includes following files:</div>* FPGA Configuration File: PCIe_Fundamental.sof
+* Download Batch file: test.bat
+* Windows Application Software folder : windows_app, includes
+* PCIE_FUNDAMENTAL.exe
+* TERASIC_PCIE_AVMM.DLL
+<div style="margin-left:1.693cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Setup'''</div>
+# Install the FPGA board on your PC as shown in [[#Figure73|Figure 7-3]].
+# Configure FPGA with PCIe_Fundamental.sof by executing the test.bat.
+# Install PCIe driver if necessary. The driver is located in the folder:
+<div style="text-align:center;margin-left:0.635cm;margin-right:0cm;">CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver.</div># Restart Windows
+# Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in [[#Figure710|Figure 7-10]].
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_10.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 7-10 Screenshot for PCIe Driver'''</div># Goto windows_app folder, execute PCIE_FUNDAMENTAL.exe. A menu will appear as shown in [[#Figure711|Figure 7-11]].
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_11.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 7-11 Screenshot of Program Menu'''</div># Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in [[#Figure712|Figure 7-12]]. If input 0 (hex 0x00), all led will be turn off.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_12.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 7-12 Screenshot of LED Control'''</div># Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in [[#Figure713|Figure 7-13]].
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_13.jpg|500px]]</div>
+<div style="text-align:center;"><span style="color:#404040;">'''Figure 7-13 Screenshot of Button Status Report'''</span></div># Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in [[#Figure714|Figure 7-14]].
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_14.jpg|500px]]</div>
+<div style="text-align:center;"><span style="color:#404040;">'''Figure 7-14 Screenshot of DMA Memory Test Result'''</span></div># Type 99 followed by an ENTER key to exit this test program
+* <div style="margin-left:0cm;margin-right:0cm;">'''Development Tools'''</div>
+* Quartus Prime 18.0 Standard Edition
+* Visual C++ 2012
+* <div style="margin-left:0cm;margin-right:0cm;"><span style="color:#404040;">'''Demonstration Source Code Location'''</span></div>
+* Quartus Project: Demonstrations\PCIe_Fundamental
+* C++ Project: Demonstrations\PCIe_SW_KIT\Windows\PCIE_FUNDAMENTAL
+* <div style="margin-left:0cm;margin-right:0cm;">'''FPGA Application Design'''</div>
+[[#Figure715|Figure 7-15]] shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_15.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 7-15 Hardware block diagram of the PCIe reference design'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Windows Based Application Software Design'''</div>
+<div style="color:#404040;">The application software project is built by Visual C++ 2012. The project includes the following major files:</div>
+{| align="center" style="border-spacing:0;width:14.633cm;"
+|- style="background-color:#666633;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| <span style="color:#ffffff;">'''Name'''</span>
+| align=center| <span style="color:#ffffff;">'''Description'''</span>
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE_FUNDAMENTAL.cpp
+|| Main program
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.c
+|| Implement dynamically load for TERAISC_PCIE_AVMM.DLL
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.h
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| TERASIC_PCIE_AVMM.h
+|| SDK library file, defines constant and data structure
 |-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED7
+|}
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
+<div style="color:#404040;">The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Robot is keeping balanced status
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED6~5
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;" | <div style="color:#000000;">0--Light On</div>
-<div style="color:#000000;">1--Light off</div>
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_16.jpg|500px]]</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;" | <div style="color:#000000;">00--robot is in default mode (Bluetooth & IR control)</div>
-<div style="color:#000000;">01--robot is in default mode and implements obstacle avoidance function</div>
+<div style="color:#404040;">The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. </div>
-<div style="color:#000000;">10--robot implements object following function</div>
+<div style="color:#404040;">Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the TERASIC_PCIE_AVMM.dll. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:</div>* The FPGA is configured with the associated bit-stream file and the host is rebooted.
+* The PCI express driver is loaded successfully.
+<div style="color:#404040;">The LED control is implemented by calling PCIE_Write32 API, as shown below:</div>
+{| align="center" style="border-spacing:0;width:15.333cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_17.jpg|500px]]
 |-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED4
+|}
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
+<div style="color:#404040;">The button status query is implemented by calling the PCIE_Read32 API, as shown below:</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Battery power supply voltage is lower than 10V
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED3
+{| align="center" style="border-spacing:0;width:15.134cm;"
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Robot is turning right
+|| [[Image: DE10-Advanced_revC_PCIE_pic_18.jpg|500px]]
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED2
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Robot is turning left
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED1
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Robot is moving backward
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | LED0
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Light On
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Robot is moving forward
 |-
 |}
-<span style="color:#ff0000;">Note: When LED3~0 are all lit indicates the robot is in DEMO mode.</span>
+<div style="color:#404040;">The memory-mapped memory read and write test is implemented by '''PCIE_DmaWrite''' and '''PCIE_DmaRead''' API, as shown below:</div>
-=  <span style="color:#000080;">Basic Operations</span> =
-This chapter illustrates the basic operations on how to start the robot when users receive it.
-==  Connect Power Port ==
+=== 1-0-6 7.6 PCIe Reference Design - DDR4 ===
-Remove the red protective cap from the output plug of the battery power, as shown in Figure  4 -12.
-<div style="text-align:center;color:#000000;"> [[Image:图片 16.png|top]]</div>
+<div style="color:#404040;">The application reference design shows how to add DDR4 Memory Controllers for DDR4-A SODIMM and on board DDR4-B into the PCIe Quartus project based on the PCIe_Fundamental Quartus project and perform 4GB data DMA for both SODIMM. Also, this demo shows how to call “PCIE_ConfigRead32” API to check PCIe link status.</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Files Location'''</div>
-<div style="text-align:center;"> '''Figure 4‑12 Remove the protective cap'''</div>
-Insert the output plug of battery power into the input port of the motor driver board, as shown in Figure  4 -13.
-<div style="text-align:center;color:#000000;"> [[Image:图片 17.png|top]]</div>
+<div style="color:#404040;">The demo file is located in the batch folder: </div>
-<div style="text-align:center;"> '''Figure 4‑13  Connect the battery power connector to the power input port'''</div>
+<div style="text-align:center;">CDROM\Demonstrations\PCIe_DDR4\demo_batch</div>
-==  Power on the Robot ==
+<div style="color:#404040;">The folder includes following files:</div>* FPGA Configuration File:  PCIe_DDR4.sof
+* Download Batch file: test.bat
+* Windows Application Software folder : windows_app, includes
-Place the robot on the plane, keep it in a horizontal state, then set the power switch of the motor driver board to ON position, as shown in Figure  4 -14<span style="color:#666699;"><span style="color:#000000;">.</span></span>
+* PCIE_DDR4.exe
+* TERASIC_PCIE_AVMM.dll
-<div style="text-align:center;color:#000000;">  [[Image:图片 14.png|top]]</div>
-<div style="text-align:center;"> '''Figure 4‑14 Set SW1 to ON position'''</div>
-==  Keep a Balanced State ==
+<div style="margin-left:0.847cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Setup'''</div>
-When the LED7 on the DE10-Nano board is lit, please release the robot, it will keep   balance automatically, as shown in Figure  4 -15.
+# Install DDR4 2400 4GB SODIMM on the FPGA board.
+# Install the FPGA board on your PC as shown in [[#Figure73|Figure 7-3]].
+# Configure FPGA with PCIe_DDR4.sof by executing the test.bat.
+# Install PCIe driver if necessary.
+# Restart Windows
+# Make sure the Windows has detected the FPGA Board by checking the Windows Control panel.
+# Goto windows_app folder, execute PCIE_DDR4.exe. A menu will appear as shown in [[#Figure716|Figure 7-16]].
-<div style="text-align:center;color:#000000;"> [[Image:图片 15.png|top]]</div>
-<div style="text-align:center;"> '''Figure 4‑15 LED7 lights on shows the robot is in balance state'''</div>==  Attitude Control ==
-The robot can perform posture recognition in real time through the acceleration sensor and the gyroscope and achieve balance by controlling the motors and adjusting the posture. For example, pick up the robot, it will detect that its current state is not in a horizontal state, when the robot is placed on a horizontal plane, the robot will access its current balance status and adjust accordingly and keeping it in balanced state without any external help. If an external force causes the robot to tilt forward, the motors will quickly produce the forward motion torque to compensate for the angle of the tilt and maintain the balance of the robot. If an irregular object is placed on the robot, the robot body will maintain balance.=  <span style="color:#000080;">Advanced Features Demonstration</span> =
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_19.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 7-16 Screenshot of Program Menu'''</div># Type 2 followed by a ENTER key to select Link Info item. The PCIe link information will be shown as in [[#Figure717|Figure 7-17]]. Gen3 link speed and x8 link width are expected.
-Based on the DE10-Nano SoC FPGA platform, Terasic’s Self-Balancing Robot can implement attitude algorithm, perform motion control, and execute movements autonomously, such as moving forward, turning right & left, power monitoring, object following and obstacle avoidance. Line following and obstacle avoidance are described below.  ==  Obstacle avoidance demonstrate ==
-Once the ultrasonic module is assembled on the robot, object following and obstacle avoidance can be implemented with the module.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_20.jpg|500px]]</div>
-When the robot is in default mode and obstacle avoidance is on (SW[1:0] is on “10” position, as shown in Table  3 -1), if the ultrasonic sensor detects the obstacle is in front of the robot and the distance is within 10 cm, the robot will stop automatically, which will implement the obstacle avoidance function, as shown in Figure  5 -16.
+<div style="text-align:center;">'''Figure 7-17 Screenshot of Link Info'''</div># Type 3 followed by an ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in [[#Figure718|Figure 7-18]].
-<div style="text-align:center;color:#000000;"> [[Image:图片 30.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑16 Obstacle avoidance demonstrate'''</div>
-When the robot is in object following and obstacle avoidance mode (SW[10] is on “01” position, as shown in Table  3 -1), and if the ultrasonic sensor detects the object is in front of the robot and the distance is within 10 cm, the robot will automatically move backward to avoiding object. When an object is in front of the ultrasonic module and moves slowly and the distance is within 10 cm~20 cm, the robot will continue to move along with the object, which will implement the object following function, as shown in Figure  5 -17.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_21.jpg|500px]]</div>
-<div style="text-align:center;color:#000000;"> [[Image:图片 31.png|top]]</div>
+<div style="text-align:center;">'''Figure 7-18 Screenshot of On-Chip Memory DMA Test Result'''</div># Type 4 followed by an ENTER key to select DMA DDR4-A SODIMM Memory Test item. The DMA write and read test result will be report as shown in [[#Figure719|Figure 7-19]].
-<div style="text-align:center;"> '''Figure 5‑17 Object following demonstrate'''  </div>==     Smartphone APP Control ==
-    The robot can be remote controlled by a Smartphone APP, this section describes how to control the robot by APP .=== Android APP Control ===
-* <div style="margin-left:0.85cm;margin-right:0cm;"> '''Download APP '''</div>
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_22.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 7-19 Screenshot of DDR4-A SOSIMM Memory DAM Test Result'''</div># Type 5 followed by an ENTER key to select DMA DDR4-B Memory Test item. The DMA write and read test result will be report as shown in [[#Figure720|Figure 7-20]].
-Users can download and install the Android Smartphone APP by scanning the QR code below (See Figure  5 -18) or download the APP file from the link:
-[http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=238&No=1096&PartNo=4%20 http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=238&No=1096&PartNo=4 ]
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_23.jpg|500px]]</div>
-After the installation is completed, the APP icon is shown as Figure  5 -19,
+<div style="text-align:center;"><span style="color:#404040;">'''Figure 7-20 Screenshot of DDR4-B SOSIMM Memory DAM Test Result'''</span></div># Type 99 followed by an ENTER key to exit this test program.
-<div style="text-align:center;"> [[Image:图像3.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑18 Download QR code of the APP'''</div>
-<div style="text-align:center;color:#000000;">[[Image:图片 10.png|top]]</div>
+<div style="margin-left:0.635cm;margin-right:0cm;"></div>* <div style="margin-left:0cm;margin-right:0cm;">'''Development Tools'''</div>
-<div style="text-align:center;"> '''Figure 5‑19 Android APP icon'''</div>* <div style="margin-left:0.85cm;margin-right:0cm;">'''Connect APP and Robot '''</div>
+* Quartus Prime 18.0 Standard Edition
+* Visual C++ 2012
+* <div style="margin-left:0cm;margin-right:0cm;"><span style="color:#404040;">'''Demonstration Source Code Location'''</span></div>
+* Quartus Project: Demonstrations\PCIE_DDR4
+* Visual C++ Project: Demonstrations\PCIe_SW_KIT\Windows\PCIe_DDR4
- Power on the robot, set SW0~3 of the DE10-Nano to Down position, as shown in Figure  5 -20.
-<div style="text-align:center;color:#000000;"> [[Image:图片 11.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑20 Set SW0~3 to Down position'''</div>
+* <div style="margin-left:0cm;margin-right:0cm;">'''FPGA Application Design'''</div>
-Turn on phone Bluetooth switch, scan for available devices, normally the robot Bluetooth device name begins with “30”, as shown in Figure  5 -21.
-<div style="text-align:center;">[[Image:图像4.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑21 Scan for robot Bluetooth device'''</div>
+[[#Figure721|Figure 7-21]] shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.
-Click the “'''30:...'''”available device to pair the robot, after they are paired successfully, the phone will show the actual name of the Bluetooth device, such as “Terasic Bal-Car 0XX”, as shown in Figure  5 -22.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_24.jpg|500px]]</div>
-<div style="text-align:center;">[[Image:图像5.png|top]]</div>
+<div style="text-align:center;">'''Figure 7-21 Hardware block diagram of the PCIe_DDR4 reference designWindows Based Application Software Design'''</div>
-<div style="text-align:center;"> '''Figure 5‑22 Bluetooth device paired'''</div>
+<div style="color:#404040;">The application software project is built by Visual C++ 2012. The project includes the following major files:</div>
-Run the robot APP, click the search icon on the upper right corner of the APP GUI, as shown in Figure  5 -23.
-<div style="text-align:center;">[[Image:图像6.png|top]]</div>
+{| align="center" style="border-spacing:0;width:14.633cm;"
+|- style="background-color:#666633;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| <span style="color:#ffffff;">'''Name'''</span>
+| align=center| <span style="color:#ffffff;">'''Description'''</span>
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE_DDR4.cpp
+|| Main program
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.c
+|| Implement dynamically load for TERAISC_PCIE_AVMM.DLL
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.h
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| TERASIC_PCIE_AVMM.h
+|| SDK library file, defines constant and data structure
+|-
+|}
+<div style="color:#404040;">The main program PCIE_DDR4.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.</div>
-<div style="text-align:center;"> '''Figure 5‑23 Click the search icon on the APP GUI'''</div>
-When the actual robot device name appears, select it as the device to connect, as shown in Figure  5 -24.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_25.jpg|500px]]</div>
-<div style="text-align:center;"> [[Image:图像7.png|top]]</div>
+<div style="color:#404040;">The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. <span style="color:#ff0000;">The above definition is the same as those in PCIe Fundamental demo.</span></div>
-<div style="text-align:center;"> '''Figure 5‑24 Connect to robot Bluetooth device'''</div>
-After connecting to the robot successfully, it will display connection status "connected to Terasic Bal-Car 0XX" at the top left corner of the APP, as shown in Figure  5 -25.
+<div style="color:#404040;">Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the TERASIC_PCIE_AVMM.DLL. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:</div>* The FPGA is configured with the associated bit-stream file and the host is rebooted.
+* The PCI express driver is loaded successfully.
-<div style="text-align:center;">[[Image:图像8.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑25 Connected to the robot successfully'''</div>* <div style="margin-left:0.85cm;margin-right:0cm;">'''Control the Robot '''</div>
+<div style="color:#404040;">The LED control is implemented by calling PCIE_Write32 API, as shown below:</div>
-Now users can click the yellow direction keys, STOP key and DEMO key to control the robot, Figure  5 -26shows the direction keys functions.
+{| align="center" style="border-spacing:0;width:15.039cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_26.jpg|500px]]
+|-
+|}
-<div style="text-align:center;">[[Image:图像9.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑26 APP GUI'''</div>* Forward：robot moves forward (Ensure the ultrasonic module is installed)
+<div style="color:#404040;">The button status query is implemented by calling the '''PCIE_Read32''' API, as shown below:</div>
-* Backward：robot moves backward
-* Turn left：robot turns left
-* Turn right：robot turns right
-* STOP：robot stops moving
-* Ultrasonic On/Off: Enable/Disable ultrasonic module for '''obstacle avoidance''' function
-* DEMO mode：when clicking the DEMO button, the robot will perform the scheduled action. After finishing the action, it will exit the DEMO mode automatically; if you click DEMO button again or click Stop button during DEMO mode, the robot will exit the DEMO mode automatically and keep balance where it is; if you click Forward/Backward/Left/Right button during the DEMO mode, the robot will exit the DEMO mode immediately, and perform the action according to the button
-=== <span style="color:#000080;">i</span><span style="color:#000080;">OS APP Control</span> ===
-* <div style="margin-left:0.85cm;margin-right:0cm;">'''Install the APP '''</div>
+{| align="center" style="border-spacing:0;width:15.134cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_27.jpg|500px]]
+|-
+|}
+<div style="color:#404040;"></div>
+<div style="color:#404040;">The memory-mapped memory read and write test is implemented by '''PCIE_DmaWrite''' and '''PCIE_DmaRead''' API, as shown below:</div>
+[[Image: DE10-Advanced_revC_PCIE_pic_28.jpg|500px]]
-  Open the App Store on your iPhone and search for “bal_car” as shown in Figure  5 -27, then install the app:
-<div style="text-align:center;">[[Image:图像10.png|top]]</div>
+The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below:
-<div style="text-align:center;"> '''Figure 5‑27 iOS APP icon'''</div>* <div style="margin-left:0.85cm;margin-right:0cm;">'''Connect APP and Robot '''</div>
+=
+=  <span style="color:#000000;">Chapter 8</span><span style="color:#000080;"><span style="color:#002060;">Chpater2 PCI Express Reference Design for Linux</span></span> ==
-Turn on phone Bluetooth switch then run the APP, the initial APP GUI is shown as Figure  5 -28.
+<div style="color:#404040;">PCI Express is commonly used in consumer, server, and industrial applications, to link motherboard-mounted peripherals. From this demonstration, it will show how the PC Linux and FPGA communicate with each other through the PCI Express interface. Arria 10 Hard IP for PCI Express with Avalon-MM DMA IP is used in this demonstration. For detail about this IP, please refer to Altera document [https://www.altera.com/en_US/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf ug_a10_pcie_avmm_dma.pdf].</div>
-<div style="text-align:center;margin-left:0.85cm;margin-right:0cm;">[[Image:图像11.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑28 Initial iOS APP GUI '''</div>
+=== 2-0-7 8.1 PCI Express System Infrastructure ===
-Power on the robot, set SW0~3 of the DE10-Nano to Down position, as shown in Figure  5 -20<span style="color:#666699;">'''.'''</span>
-As shown in Figure  5 -28, click the refresh icon on the top right corner of the APP GUI, the APP can detect the robot Bluetooth device, it is shown as Figure  5 -29'''.'''
+[[#Figure81|Figure 8-1]] shows the infrastructure of the PCI Express System in this demonstration. It consists of two primary components: FPGA System and PC System. The FPGA System is developed based on Arria 10 Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Altera’s PCIe kernel mode driver.
-<div style="text-align:center;">[[Image:图像12.png|top]]</div>
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_29.jpg|500px]]</div>
-<div style="text-align:center;"> '''Figure 5‑29 The robot is shown in the APP GUI'''</div>
+<div style="text-align:center;"> '''Figure 8-1 Infrastructure of PCI Express System'''</div>
-Click the Bluetooth device (BAL_CAR_XX), the APP will connect to the robot and shows the interactive interface for robot control, as shown in Figure  5 -30'''.'''
-<div style="text-align:center;">[[Image:图像13.png|top]]</div>
+=== 2-0-8 8.2 PC PCI Express Software SDK ===
-<div style="text-align:center;"> '''Figure 5‑30 APP is connected to robot'''</div>* <div style="margin-left:0.85cm;margin-right:0cm;">'''Control the Robot '''</div>
+<div style="color:#404040;">The FPGA System CD contains a PC Windows based SDK to allow users to develop their 64-bit software application on 64-bits Linux. CentOS 7.2 is recommended. The SDK is located in the “CDROM/Demonstrations/PCIe_SW_KIT/Linux” folder which includes:</div>* PCI Express Driver
+* PCI Express Library
+* PCI Express Examples
-Now users can click the yellow direction keys, STOP key to control the robot (The latest iOS version APP hasn’t DEMO key temporary), Figure  5 -31shows all the keys functions.
-<div style="text-align:center;">[[Image:图像14.png|top]]</div>
+<div style="color:#404040;">The kernel mode driver assumes the PCIe vendor ID (VID) is 0x1172 and the device ID (DID) is 0xE003. If different VID and DID are used in the design, users need to modify the PCIe vendor ID (VID) and device ID (DID) in the driver project and rebuild the driver. The ID is defined in the file PCIe_SW_KIT/Linux/PCIe_Driver/altera_pcie_cmd.h.</div>
-<div style="text-align:center;"> '''Figure 5‑31 iOS APP Control GUI'''</div>* Forward：robot moves forward (Ensure the ultrasonic module is installed)
-* Backward：robot moves backward
-* Turn left：robot turns left
-* Turn right：robot turns right
-* STOP：robot stops moving
-* Ultrasonic On/Off: Enable/Disable ultrasonic module for '''obstacle avoidance''' function
-==  IR Remote Control ==
+<div style="color:#404040;">The PCI Express Library is implemented as a single .so file named terasic_pcie_qsys.so.This file is a 64-bit library file. With the library exported software API, users can easily communicate with the FPGA. The library provides the following functions:</div>* Basic data read and write
+* Data read and write by DMA
-<span style="color:#666699;">'''Figure  5 -32'''</span>shows the remote control for the robot, point IR remote control to the robot, the robot will move forward when users press key 2, the robot will stop moving when user press key 5. The key 8 is used to move the robot backward, key 4 is used to turn the robot to the left, and key 6 is used to turn the robot to the right. Table  5 -4shows the functions of each key number on the controls.
-<div style="text-align:center;color:#000000;"> [[Image:图片 23.png|top]]</div>
-<div style="text-align:center;"> '''Figure 5‑32 Robot remote control'''</div>
+<div style="color:#404040;">For high performance data transmission, Altera AVMM DMA is required as the read and write operations are specified under the hardware design on the FPGA.</div>
-<div style="text-align:center;margin-left:0.423cm;margin-right:0cm;"> <span style="color:#000000;">'''Table </span><span style="color:#000000;">5</span><span style="color:#000000;">‑</span><span style="color:#000000;">4</span><span style="color:#000000;"> '''</span>Remote control function keys</div>
+=== 2-0-9 8.3 PCI Express Software Stack ===
-{| align="center" style="border-spacing:0;width:8.451cm;"
-|-
+[[#Figure82|Figure 8-2]] shows the software stack for the PCI Express application software on 64-bit Linux. The PCIe library module terasic_pcie_qys.so provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this .so library file. The altera_pcie.ko kernel driver is provided by Altera.
-| style="background-color:#bfbfbf;border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''Key numbers'''
-| style="background-color:#bfbfbf;border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | '''Function'''
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_30.jpg|500px]]</div>
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 2
+<div style="text-align:center;"> '''Figure 8-2 PCI Express Software Stack'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Install PCI Express Driver on Linux'''</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Forward
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 5
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Stop
+<div style="color:#404040;">To make sure the PCIe driver can meet your kernel of Linux distribution, the driver altera_pcie.ko should be recompile before use it. The PCIe driver project is locate in the folder:</div>
-|-
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 8
+<div style="text-align:center;">"CDROM/Demonstrations/PCIe_SW_KIT/Linux/PCIe_Driver"</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Backward
-|-
+The folder includes the following files:* altera_pcie.c
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 4
+* altera_pcie.h
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Turn left
+* altera_pcie_cmd.h
-|-
+* <div style="margin-left:1.7cm;margin-right:0cm;">Makefile</div>
-| style="border-top:0.5pt solid #000000;border-bottom:0.5pt solid #000000;border-left:0.5pt solid #000000;border-right:none;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | 6
+* <div style="margin-left:1.7cm;margin-right:0cm;">load_driver</div>
-| style="border:0.5pt solid #000000;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;color:#000000;" | Turn right
+* <div style="margin-left:1.7cm;margin-right:0cm;">unload</div>
+* <div style="margin-left:1.7cm;margin-right:0cm;">config_file</div>
+<div style="color:#404040;">To compile and install the PCI Express driver, please execute the steps below: </div>
+# Make sure the DE10-Advanced and the PC are both powered off.
+# Plug the PCIe adapter card into the PCIe slot on the PC motherboard. Use the PCIe cable to connect to the DE10-Advanced PCIE connector and the PCIe adapter card (See [[#Figure83|Figure 8-3]])
+<div style="text-align:center;margin-left:1.27cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_31.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 8-3 FPGA board connect to PC'''</div># Power on your DE10-Advanced board and the host PC
+# Open a terminal and use "cd" command to goto the folder"CDROM/Demonstrations/PCIe_Fundamental/demo_batch".
+# Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path. Set QUARTUS_ROOTDIR variable by tying the following commands in terminal. Replace “/home/centos/intelFPGA/18.0/quartus” to your quartus installation path.
+{| style="border-spacing:0;width:13.938cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| export QUARTUS_ROOTDIR=/home/centos/intelFPGA/18.0/quartus
 |-
 |}
+# Execute "sudo -E sh test.sh" command to configure the FPGA
+# Restart Linux operation system. In Linux, open a terminal and use “cd” command to goto the PCIe_Driver folder
+# Type the following commands to compile and install the driver altera_pcie.ko, and make sure driver is loaded successfully and FPGA is detected by the driver as shown in [[#Figure84|Figure 8-4]].'''
-=  <span style="color:#000080;">Charging the battery</span> =
+* make
+* sudo sh load_driver
+* dmesg | tail -n 15
-The robot is powered by a three-section of lithium battery (the specific parameters of the battery can be seen outside the battery package). When the power is less than 10V, the LED4 on DE10-Nano board will light up, indicating that the battery needs to be charged in time; and the APP will also show the battery power level. If the lithium battery starts charging after it is completely drained and is completely unable to supply power to the robot, it will take up to 2 hours the battery to be fully charged. The battery charging steps are as follows:
-Power off the robot, pull out the power cable, and take the battery out of the robot’s onboard battery storage space, as shown in Figure  6 -33.
-<div style="text-align:center;color:#000000;">[[Image:图片 24.png|top]]</div>
+[[Image: DE10-Advanced_revC_PCIE_pic_32.jpg|500px]]
-<div style="text-align:center;"> '''Figure 6‑33 Robot battery'''</div>
+<div style="text-align:center;">'''Figure 8-4 Screenshot of install PCIe driver'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Create a Software Application'''</div>
-As shown in Figure  6 -34, connect the charger to battery connector.
-<div style="text-align:center;color:#000000;"> [[Image:图片 25.png|top]]</div>
-<div style="text-align:center;"> '''Figure 6‑34 Connect charger to battery connector'''</div>
+<div style="color:#404040;">All the files needed to create a PCIe software application are located in the directory CDROM/Demonstrations/PCIe_SW_KIT/Linux/PCIe_Library. It includes the following files:</div>* TERASIC_PCIE_AVMM.h
+* terasic_pcie_qsys.so (64-bit library)
-As shown in Figure  6 -35, plug the charger into the AC 220V or 110V power outlets, after the power is fully charged, the LED on the charger will light up green, then unplug the charger.
-<div style="text-align:center;color:#000000;">[[Image:图片 26.png|top]]</div>
-<div style="text-align:center;"> '''Figure 6‑35 Charge the battery'''</div>
+<div style="color:#404040;">Below lists the procedures to use the library in users’ C/C++ project:</div># Create a 64-bit C/C++ project.
+# Include TERASIC_PCIE_AVMM.h in the C/C++ project.
+# Copy terasic_pcie_qsys.so to the folder where the project execution file is located.
+# Dynamically load terasic_pcie_qsys.so in C/C++ program. To load the terasic_pcie_qsys.so, please refer to the PCIe fundamental example below.
+# Call the library API to implement the desired application.
-<div style="text-align:center;"></div>
-<div style="text-align:center;"> </div>
+<div style="color:#404040;">Users can easily communicate with the FPGA through the PCIe bus through the terasic_pcie_qsys.so API. The details of API are described below:</div>
-=  <span style="color:#000080;">Restore Factory Setting</span> =
+=== 2-0-10 8.4 PCI Express Library API ===
-This chapter will introduce the switches and buttons that can be set on the Self-Balancing Robot. It explains the meaning and function of the setting. There are two versions of factory code: ARM and NIOS CPU-controlled version. So that, the following will describe the two methods of restoring.==   ARM Version Restoring ==
+<div style="color:#404040;">The API is the same as Windows Library. Please refer to the section 7.4 PCI Express Library API in this document.</div>
-The factory code of AMR version is stored in the Micro SD Card. The following will describe how to restore factory code in the Micro SD Card.* <div style="margin-left:0.847cm;margin-right:0cm;">  '''Required Equipment: '''</div>
-**  PC: Write Linux image file into SD card
-** Micro SD Card: 8GB minimum
-** Micro SD Card reader: Write the SD Micro SD card
+=== 2-0-11 8.5 PCIe Reference Design – Fundamental ===
-<div style="margin-left:1.693cm;margin-right:0cm;"></div>* <div style="margin-left:0.847cm;margin-right:0cm;"> '''Software and file requirements:'''</div>
+<div style="color:#404040;">The application reference design shows how to implement fundamental control and data transfer in DMA. In the design, basic I/O is used to control the BUTTON and LED on the FPGA board. High-speed data transfer is performed by DMA.</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Files Location'''</div>
-** Win32DiskImager.zip: the tool which is used to write image file to Micro SD Card, it’s located at CD\Tool\
-** ''de10_nano_balance_car.zip'': the compressed demo image file for ARM version robot, it’s located at [http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1096&PartNo=4 http://www.terasic.com.tw/cgi-bin/page/archive.pl?][http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1096&PartNo=4 Language=English&No=1096&PartNo=4]
-<div style="margin-left:1.693cm;margin-right:0cm;"></div>* <div style="margin-left:0.847cm;margin-right:0cm;">'''Steps:'''</div>
+<div style="color:#404040;">The demo file is located in the batch folder: </div>
-** Copy the ''de10_nano_balance_car.zip'' to PC and unzip it to get ''balance_car.img'' file.
-** Insert the Micro SD card into SD card reader and connect the card reader to PC USB port.
-** Copy ''Win32DiskImager.zip'' to PC and unzip it, execute ''Win32DiskImager.exe'' in the unzipped Win32DiskImager folder.
-** As shown in Figure  7 -36, choose ''de10_nano_balance_car.img'' for Image File.
+<div style="text-align:center;">CDROM/Demonstrations/PCIe_Fundamental/demo_batch</div>
-<div style="text-align:center;"> [[Image:图像15.png|top]]</div>
+<div style="color:#404040;">The folder includes following files:</div>* FPGA Configuration File: PCIe_Fundamental.sof
+* Download Batch file: test.sh
+* Linux Application Software folder : linux_app, includes
-<div style="text-align:center;"> '''Figure 7‑36 Win32DiskImager window'''</div>*
+* PCIE_FUNDAMENTAL
-** Choose the drive disk of Micro SD card for Device.
+* terasic_pcie_qsys.so
-** Click “write” to start writing the image file to the microSD card. Wait until the image is written successfully.
-** As shown in Figure  7 -37, insert the Micro SD card into the robot. And set the mode switch(SW10) MSEL[4:0] to "01010", as shown in Figure  7 -38.
+* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Setup'''</div>
+# Install the FPGA board on your PC as shown in [[#Figure83|Figure8-3]].
+# Open a terminal and use "cd" command to goto "CDROM/Demonstrations/PCIe_Fundamental/demo_batch".
+# Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path. Set QUARTUS_ROOTDIR variable by tying the following commands in terminal. Replace /home/centos/intelFPGA/18.0/quartus to your quartus installation path.
-<div style="text-align:center;color:#4a4a4a;">[[Image:图像16.png|top]]</div>
-<div style="text-align:center;"> '''Figure 7‑37 Insert the Micro SD card into the robot'''</div>*
-** Power on the robot then start using it.
+{| style="border-spacing:0;width:13.938cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| export QUARTUS_ROOTDIR=/home/centos/intelFPGA/18.0/quartus
+|-
+|}
+# Execute "sudo -E sh test.sh" command to configure the FPGA
+# Restart Linux
+# Install PCIe driver. The driver is located in the folder:
-<div style="text-align:center;color:#4a4a4a;"> [[Image:图像17.png|top]]</div>
-<div style="text-align:center;"> '''Figure 7‑38 Set MSEL[4:0] to "01010" for ARM Version Mode'''</div>==  NIOS Version Restoring ==
-The factory code of NIOS version is stored in the ECPS device. The following will describe how to restore factory code in the EPCS.* <div style="margin-left:0.847cm;margin-right:0cm;">'''Required Equipment: '''</div>
+<div style="text-align:center;margin-left:0.635cm;margin-right:0cm;">CDROM/Demonstration/PCIe_SW_KIT/Linux/PCIe_Driver.</div># Type “ls –l /dev/altera_pcie*” to make sure the Linux has detected the FPGA Board. If the FPGA board is detected, developers can find the /dev/altera_pcieX(where X is 0~255) in Linux file system as shown below.
-** PC: configuring the jic file to EPCS device on the robot
-** Mini USB Cable x 1: Connect robot to PC for configuring the file
-<div style="margin-left:1.693cm;margin-right:0cm;"></div>* <div style="margin-left:0.847cm;margin-right:0cm;">'''Software and file requirements:'''</div>
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_33.jpg|500px]].
-** Ensure the Intel Quartus tools is installed properly.
-** The compressed .jic file for Nios version robot, it’s located at CD\Demonstration\factory\nios\
-<div style="margin-left:1.693cm;margin-right:0cm;"></div>* <div style="margin-left:0.847cm;margin-right:0cm;">'''Steps:'''</div>
+[[Image: DE10-Advanced_revC_PCIE_pic_34.jpg|500px]]
-** As shown in Figure  7 -39, Connect a USB cable to the USB Blaster II connector on the robot and the PC.
+<div style="text-align:center;">'''Figure 8-5 Screenshot of Program Menu'''</div># Type 0 followed by a ENTER key to select Led Control item, then input 3 (hex 0x03) will make all led on as shown in [[#Figure86|Figure 8-6]]. If input 0 (hex 0x00), all led will be turn off.
-<div style="text-align:center;color:#4a4a4a;">[[Image:图像18.png|top]]</div>
-<div style="text-align:center;"> '''Figure 7‑39 Connect the robot to PC via USB Mini Cable'''</div>*
+[[Image: DE10-Advanced_revC_PCIE_pic_35.jpg|500px]]
-** As shown in Figure  7 -40, set the mode switch (SW10) MSEL[4:0] to "10010".
+<div style="text-align:center;">'''Figure 8-6 Screenshot of LED Control'''</div># <div style="margin-left:0.63cm;margin-right:0cm;">Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in [[#Figure87|Figure 8-7]].</div>
-<div style="text-align:center;color:#4a4a4a;">[[Image:图像19.png|top]]</div>
-<div style="text-align:center;"> '''Figure 7‑40 Set MSEL[4:0] to "10010" for NIOS Version Mode'''</div>*
+<div style="text-align:center;margin-left:-0.005cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_36.jpg|500px]]</div>
-** Copy demo_batch_jic.zip to PC and unzip it to get demo_batch_jic folder.
-** As shown in Figure  7 -41, input number 3 in the pop-up command window and click Enter key, it will start to configure the .jic file to EPCS device.
-** After the configuration is completed, remove the USB cable. Power on the robot and verify if the code is written right.
+<div style="text-align:center;">'''Figure 8-7 Screenshot of Button Status Report'''</div># <div style="margin-left:0.63cm;margin-right:0cm;">Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in [[#Figure88|Figure 8-8]].</div>
+<div style="text-align:center;margin-left:-0.005cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_37.jpg|500px]]</div>
-<div style="text-align:center;color:#4a4a4a;">[[Image:图像20.png|top]]</div>
+<div style="text-align:center;">'''Figure 8-8 Screenshot of DMA Memory Test Result'''</div># Type 99 followed by an ENTER key to exit this test program
-<div style="text-align:center;"> '''Figure 7‑41 Command shell for write .jic file into EPCS device'''</div>
+* <div style="margin-left:0cm;margin-right:0cm;">'''Development Tools'''</div>
-=  <span style="color:#000080;">Additional Information</span> =
+* Quartus Prime 18.0 Standard Edition
+* GNU Compiler Collection, Version 4.8 is recommend
+* <div style="margin-left:0cm;margin-right:0cm;"><span style="color:#404040;">'''Demonstration Source Code Location'''</span></div>
+* Quartus Project: Demonstrations/PCIe_Fundamental
+* C++ Project: Demonstrations/PCIe_SW_KIT/Linux/PCIE_FUNDAMENTAL
-<span style="color:#000080;">'''Getting Help'''</span>
+* <div style="margin-left:0cm;margin-right:0cm;">'''FPGA Application Design'''</div>
-Here is the contact information where you can get help if you encounter problems:*
-** Terasic Technologies9F, No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, Taiwan 300-70Email&nbsp;: [mailto:support@terasic.com support@terasic.com]Web&nbsp;: [http://www.terasic.com/ www.terasic.com]
+[[#Figure89|Figure 8-9]] shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_38.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 8-9 Hardware block diagram of the PCIe reference design'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Linux Based Application Software Design'''The application software project is built by GNU Toolchain. The project includes the following major files:</div>
-Revision History
-{| align="center" style="border-spacing:0;width:13.781cm;"
+{| align="center" style="border-spacing:0;width:14.633cm;"
+|- style="background-color:#666633;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| <span style="color:#ffffff;">'''Name'''</span>
+| align=center| <span style="color:#ffffff;">'''Description'''</span>
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE_FUNDAMENTAL.cpp
+|| Main program
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.c
+|| Implement dynamically load for terasic_pcie_qsys.so library file
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.h
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| TERASIC_PCIE_AVMM.h
+|| SDK library file, defines constant and data structure
 |-
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" | '''Date'''
+|}
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" | '''Version'''
+<div style="color:#404040;">The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.</div>
-| style="border:0.5pt solid #999999;padding:0cm;" | '''Changes'''
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_39.jpg|500px]]</div>
+<div style="color:#404040;">The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. </div>
+<div style="color:#404040;">Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the terasic_pcie_qsys.so. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:</div>* The FPGA is configured with the associated bit-stream file and the host is rebooted.
+* The PCI express driver is loaded successfully.
+<div style="color:#404040;">The LED control is implemented by calling PCIE_Write32 API, as shown below:</div>
+{| align="center" style="border-spacing:0;width:15.333cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_40.jpg|500px]]
 |-
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" | '''2018.03.16'''
+|}
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" | '''First publication'''
+<div style="color:#404040;"></div>
-| style="border:0.5pt solid #999999;padding:0cm;" |
+<div style="color:#404040;">The button status query is implemented by calling the '''PCIE_Read32''' API, as shown below:</div>
+{| align="center" style="border-spacing:0;width:15.134cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_41.jpg|500px]]
 |-
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
+|}
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
+<div style="color:#404040;">The memory-mapped memory read and write test is implemented by '''PCIE_DmaWrite''' and '''PCIE_DmaRead''' API, as shown below:</div>
-| style="border:0.5pt solid #999999;padding:0cm;" |
+=== 2-0-12 8.5 PCIe Reference Design - DDR4 ===
+<div style="color:#404040;">The application reference design shows how to add DDR4 Memory Controllers for DDR4-A SODIMM and on board DDR4-B into the PCIe Quartus project based on the PCIe_Fundamental Quartus project and perform 4GB data DMA for both SODIMM. Also, this demo shows how to call “PCIE_ConfigRead32” API to check PCIe link status.</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Files Location'''</div>
+<div style="color:#404040;">The demo file is located in the batch folder: </div>
+<div style="text-align:center;">CDROM/Demonstrations/ PCIe_DDR4/demo_batch</div>
+<div style="color:#404040;">The folder includes following files:</div>* FPGA Configuration File: PCIe_DDR4sof
+* Download Batch file: test.sh
+* Linux Application Software folder : linux_app, includes
+* PCIE_DDR4
+* terasic_pcie_qsys.so
+* <div style="margin-left:0cm;margin-right:0cm;">'''Demonstration Setup'''</div>
+# Install DDR4 2400 4GB SODIMM on the FPGA board.
+# Install the FPGA board on your PC as shown in [[#Figure83|Figure8-3]].
+# Open a terminal and use "cd" command to goto "CDROM/Demonstrations/PCIe_Fundamental/demo_batch".
+# Set QUARTUS_ROOTDIR variable pointing to the Quartus installation path. Set QUARTUS_ROOTDIR variable by tying the following commands in terminal. Replace /home/centos/intelFPGA/18.0/quartus to your quartus installation path.
+{| style="border-spacing:0;width:13.938cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| export QUARTUS_ROOTDIR=/home/centos/intelFPGA/18.0/quartus
 |-
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
+|}
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
+# Execute "sudo -E sh test.sh" command to configure the FPGA
-| style="border:0.5pt solid #999999;padding:0cm;" |
+# Restart Linux
-|-
+# Install PCIe driver.
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
+# Make sure the Linux has detected the FPGA Board.
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
+# Goto linux_app folder, execute PCIE_DDR4. A menu will appear as shown in [[#Figure810|Figure 8-10]].
-| style="border:0.5pt solid #999999;padding:0cm;" |
-|-
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
+[[Image: DE10-Advanced_revC_PCIE_pic_42.jpg|500px]]
-| style="border:0.5pt solid #999999;padding:0cm;" |
-|-
+<div style="text-align:center;">'''Figure 8-10 Screenshot of Program Menu'''</div># Type 2 followed by an ENTER key to select Link Info item. The PCIe link information will be shown as in [[#Figure811|Figure 8-11]]. Gen3 link speed and x8 link width are expected.
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
-| style="border:0.5pt solid #999999;padding:0cm;" |
-|-
+[[Image: DE10-Advanced_revC_PCIE_pic_43.jpg|500px]]
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
+<div style="text-align:center;">'''Figure 8-11 Screenshot of Link Info'''</div># <div style="margin-left:0.63cm;margin-right:0cm;">Type 3 followed by an ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in [[#Figure812|Figure 8-12]].</div>
-| style="border:0.5pt solid #999999;padding:0cm;" |
-|-
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
+<div style="margin-left:-0.005cm;margin-right:0cm;">[[Image: DE10-Advanced_revC_PCIE_pic_44.jpg|500px]]</div>
-| style="border:0.5pt solid #999999;padding:0cm;" |
-|-
+<div style="text-align:center;"><span style="color:#404040;">'''Figure 8-12 Screenshot of On-Chip Memory DMA Test Result'''</span></div># Type 4 followed by an ENTER key to select DMA DDR4-A SODIMM Memory Test item. The DMA write and read test result will be report as shown in [[#Figure814|Figure 8-14]].
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;color:#ff0000;" |
-| style="border-top:0.5pt solid #999999;border-bottom:0.5pt solid #999999;border-left:0.5pt solid #999999;border-right:none;padding:0cm;" |
-| style="border:0.5pt solid #999999;padding:0cm;" |
+[[Image: DE10-Advanced_revC_PCIE_pic_45.jpg|500px]]
+<div style="text-align:center;"><span style="color:#404040;">'''Figure 8-14 Screenshot of DDR4-A SOSIMM Memory DAM Test Result'''</span></div># Type 5 followed by an ENTER key to select DMA DDR4-B Memory Test item. The DMA write and read test result will be report as shown in [[#Figure815|Figure 8-15]].
+[[Image: DE10-Advanced_revC_PCIE_pic_46.jpg|500px]]
+<div style="text-align:center;"><span style="color:#404040;">'''Figure 8-15 Screenshot of DDR4-B SOSIMM Memory DAM Test Result'''</span></div># Type 99 followed by an ENTER key to exit this test program.
+* <div style="margin-left:0cm;margin-right:0cm;">'''Development Tools'''</div>
+* Quartus Prime 18.0 Standard Edition
+* GNU Compiler Collection, Version 4.8 is recommended
+* <div style="margin-left:0cm;margin-right:0cm;"><span style="color:#404040;">'''Demonstration Source Code Location'''</span></div>
+* Quartus Project: Demonstrations/PCIE_DDR4
+* C++ Project: Demonstrations/PCIe_SW_KIT/Linux/PCIe_DDR4
+* <div style="margin-left:0cm;margin-right:0cm;">'''FPGA Application Design'''</div>
+<div style="color:#404040;">[[#Figure816|Figure 8-16]] shows the system block diagram in the FPGA system. In the Qsys, Altera PIO controller is used to control the LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface.</div>
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_47.jpg|500px]]</div>
+<div style="text-align:center;">'''Figure 8-16 Hardware block diagram of the PCIe_DDR4 reference design'''</div>* <div style="margin-left:0cm;margin-right:0cm;">'''Linux Based Application Software Design'''</div>
+<div style="color:#404040;">The application software project is built by GNU Toolchain. The project includes the following major files:</div>
+{| align="center" style="border-spacing:0;width:14.633cm;"
+|- style="background-color:#666633;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| <span style="color:#ffffff;">'''Name'''</span>
+| align=center| <span style="color:#ffffff;">'''Description'''</span>
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE_DDR4.cpp
+|| Main program
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.c
+|| Implement dynamically load for terasic_pcie_qsys.so library file
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| PCIE.h
+|- style="background-color:#ffffcc;border:0.5pt solid #a6a6a6;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+| align=center| TERASIC_PCIE_AVMM.h
+|| SDK library file, defines constant and data structure
 |-
 |}
+<div style="color:#404040;">The main program PCIE_DDR4.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design.</div>
+<div style="text-align:center;">[[Image: DE10-Advanced_revC_PCIE_pic_48.jpg|500px]]</div>
+<div style="color:#404040;">The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the DMA controller. <span style="color:#ff0000;">The above definition is the same as those in PCIe Fundamental demo.</span></div>
+<div style="color:#404040;">Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the terasic_pcie_qsys.so. Then, it call PCIE_Open to open the PCI Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and Device ID and PCI Express IP, they also need to change the ID value define in TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be accessed successfully. In this case, please make sure:</div>* The FPGA is configured with the associated bit-stream file and the host is rebooted.
+* The PCI express driver is loaded successfully.
+<div style="color:#404040;">The LED control is implemented by calling PCIE_Write32 API, as shown below:</div>
+{| align="center" style="border-spacing:0;width:15.039cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_49.jpg|500px]]
+|-
+|}
+<div style="color:#404040;">The button status query is implemented by calling the '''PCIE_Read32''' API, as shown below:</div>
+{| align="center" style="border-spacing:0;width:15.134cm;"
+|- style="border:0.5pt solid #00000a;padding-top:0cm;padding-bottom:0cm;padding-left:0.191cm;padding-right:0.191cm;"
+|| [[Image: DE10-Advanced_revC_PCIE_pic_50.jpg|500px]]
+|-
+|}
+<div style="color:#404040;">The memory-mapped memory read and write test is implemented by '''PCIE_DmaWrite''' and '''PCIE_DmaRead''' API, as shown below:</div>
+[[Image: DE10-Advanced_revC_PCIE_pic_51.jpg|500px]]
-<div style="text-align:center;"> </div>
+The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below: