Time : 2012.3.20 10:10~17:45
Place : The Chinese University of Hong Kong ( MAP
)
Room 410 Design and Project Laboratory
William W.M. Mong Engineering Building
Eligibility : ARC enrolled attendees & Professors
Introduction
The purpose of this workshop is to be familiar with Altera FPGA software and implement Verilog and Nios examples on DE2 platform - the most popular development kit in the history of FPGA, which has been widely adopted in courses of many top universities such as MIT, University of Toronto, and University of Cambridge etc.
The session in the morning will introduce Quartus, SOPC Builder, and Nios II to be used in the afternoon. We'll also talk about various resources available on DE2. In the afternoon we'll leverage comprehensive interfaces of DE2 and guide users to build projects in Verilog and Nios II step by step.
Schedule
Time | Program | Plenary Speaker |
10:10 ~ 11:50 | Introduction | David Wei |
11:50 ~ 13:15 | Lunch Time | |
13:15 ~ 14:45 | Session I | David Wei |
14:45 ~ 15:00 | Break | |
15:00 ~ 16:30 | Session II | David Wei |
16:30 ~ 16:45 | Break | |
16:45 ~ 17:45 | Wrap Up | David Wei |