Terasic USB Blaster revB Manual
From Terasic Wiki
The main function of the Terasic USB Blaster Download Cable (UBT) is to allow users to download configuration data to the system during prototype development, or to program data into the system during production. The UBT connects the Host and the FPGA on the user's board through the USB Port and 10-Pin cable. At the same time, it can support several target board voltage standards, allowing UBT to be widely used in various FPGA boards.
Supported Devices and Host System
The Intel FPGA , Serial configuration device and host systems that UBT supported are list in Table 1-1, Table 1-2 and Table 1-3
|Stratix Series||Stratix 10, Stratix V, Stratix IV, Stratix III, Stratix II GX and Stratix GX|
|Arria Series||Arria 10, Arria V, Arria II, Arria GX|
|Cyclone Series||Cyclone 10,Cyclone V, Cyclone IV, Cyclone III, Cyclone II, Cyclone|
|MAX series||MAX10,MAX V, MAXII , MAX3000, MAX7000 and MAX9000|
|Other||FLEX10K, ACEX1K, APEX 20K|
UBT can support several voltage standard of the target board. Table 1-4 shows the supported voltage. Users need to pay attention to whether the JTAG voltage standard of the target board is within the range of Table 1-4.
|Support Target board supply voltage|
(*1) Only Rev .B can support .
The following picture and table list the pins of the Terasic Download Cable female plug and describes their functions in the JTAG and passive serial modes.
|Pin Number||Pin Define||JTAG Mode Descriptions||PS Mode Descriptions|
|1||TRGTCK||Clock signal||Clock signal|
|2||GND||Signal ground||Signal ground|
|3||TRGTDO||Data from||Configuration done|
|4||TRGVCC||Target power supplied by the device board||Target power supplied by the device board|
|5||TRGTMS||JTAG state machine control.||Configuration control.|
|7||TRGNST||-||Active serial data out|
|8||TRGNCSO||-||Serial configuration device chip select|
|9||TRGASDO||Data to device.||Active serial data in|
|10||GND||Signal ground.||Signal ground|
Dimension of the Terasic USB Download Cable
Using the Terasic USB Download Cable
To start using the Intel FPGA Download Cable, user need to install the drivers on your system and set up the hardware in the Intel Quartus® Prime software.
To program or configure the device, connect the host system to the device board using the Terasic Download Cable and initiate the programming or configuration using the Intel Quartus Prime Programmer. You can also use the cable with the Intel Quartus Prime Signal Tap Logic Analyzer for logic analysis.
- Install the Driver for windows
- Install the driver for Linux
USB Blaster Self Test
This section describes users how to test whether the on-board USB blaster or USB blaster cable is properly installed and operated
- Power on the FPGA board and connect USB blaster port or USB blaster cable to PC.
Check if the Universal Serial Bus controllers in the Windows Device Manager has an Altera USB Blaster.
If yes, users can use Quartus programmer and download FPGA code.
- If Altera USB Blaster isn’t showed in Universal Serial Bus controllers, please check whether the Other devices has Unknown device.
If yes, please install the USB blaster driver refer to this link:Altera USB Blaster Driver Installation Instructions
- If no Unknown device:
- i.Make sure the board power is on and the port on board which connected to PC is USB blaster port.
- ii.If step i is OK:
- a.Test with another PC to see if the OS can detect unknown device.
- b.Test with another usb blaster cable.
- c.If still with the same problem, please contact our technical support team via email@example.com and provide below information:
- PC OS version: Win10-32bit or Win7-64bit or Linux-64bit.
- Whether you tested follow the above processes.
- The Quartus version you installed: Q16.1 or others.
1. Q：What is the difference between UBT and AUB2?
A: The main difference is the JTAG circuit, the UBT(USB Blaster Download Cable) supports USB Blaster I circuit and JTAG Voltage: 2.5V ~ 3.3V. The AUB2 (USB-Blaster II Download Cable) supports USB Blaster II circuit and JTAG Voltage: 5.0-V TTL, 3.3-V LVTTL/LVCMOS ,Single-ended I/O standards from 1.5 V to 3.3 V.
Customers can refer to Intel Cyclone 10 LP device handbook: https://www.intel.com/content/www/us/en/programmable/documentation/sxm1481253171919.html?wapkw=cyclone+10+lp+handbook and check your board JTAG voltage to see which cable is compatible with their board.
2. Q: What is the TCK Clock Frequency for UBT and AUB2 respectively?
A: The USB Blaster Cable works with the Jtag clock 6M, while the USB Blaster II Cable works at 24M.
3. Q: What is the difference between the UBT and Altera USB Blaster Download Cable (UBA)?
A: The main difference is the JTAG circuit, Terasic UBT supports JTAG voltage 2.5v~3.3V, the Altera USB Blaster supports 1.8V~3.3V, they are compatible with other features.
Please note that UBT can't detect the JTAG chain on the Intel Arria 10 GX FPGA Development Kit.
4. Q: What is the operating temperature specification of the UBT?
A:The UBT is designed to operate in the commercial temperature range (0 to 85C).
5.Q: Will USB-Blaster work under Windows 10 64-bit?
A: Yes, the USB-Blaster work under Windows 10 64-bit. And you can use either of the Quartus software version later than 10.1 to work with the Windows 10 64-bit.
A:It may be caused by the MAX10 device. Customer can try to download the .sof file to the MAX 10 device first, then download the pof file into the device with the board keeping powering on.
7.Q: How long is the UBT?
A: It is about two meters.
8. Q: I can the UBT to download the .pof file to his own board under Quartus II 11.0SP1 successfully，however, when he checked the Verify tab, it failed to download and reported that "verification failed for device number 1" ,how should I solve the problem?
A: You can try the following approaches to solve this problem:
1. Uninstall the current usb blaster driver, then try to update the driver to the higher version, such as usb blaster driver for 17.1 or later version.
2. If it is impossible to update the usb blaster driver ,we recommend you to modify the JTAG circuit on your board, and adjust the pull-up resistor of TCK TMS to modify jtag timing.