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Introduction

Compared with the Section 2.7 HDMI Retransmit demo, the difference of this demonstration is that only the TX of the Intel® FPGA HDMI IP cores is used in the FPGA. This demo also has a video test pattern generator built into the FPGA. The highest resolution 4K image is sent to the HDMI TX IP. It is displayed via an external HDMI monitor.

System Block Diagram

Figure 1-1 shows the system block diagram of the demo. First, Nios is used to generate the test pattern output to the HDMI TX IP. The resolution of the generated pattern can be 4K or Full HD(1080). User can switch the output resolution instantly through the Switch on the DE10-Advanced. The HDMI TX IP is identical to Section 2.7.

Figure 1-1 The System Block Diagram of the demonstration